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Red Hat Bugzilla – Attachment 671945 Details for
Bug 891565
[abrt] xorg-x11-server-Xorg-1.12.4-1.fc17: Xorg server crashed
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File: Xorg.0.log
Xorg.0.log (text/plain), 731.73 KB, created by
Tad
on 2013-01-03 09:59:51 UTC
(
hide
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Description:
File: Xorg.0.log
Filename:
MIME Type:
Creator:
Tad
Created:
2013-01-03 09:59:51 UTC
Size:
731.73 KB
patch
obsolete
>[ 22.970] >X.Org X Server 1.12.4 >Release Date: 2012-08-27 >[ 22.970] X Protocol Version 11, Revision 0 >[ 22.970] Build Operating System: 2.6.32-279.9.1.el6.x86_64 >[ 22.970] Current Operating System: Linux localhost.localdomain 3.6.10-2.fc17.x86_64 #1 SMP Tue Dec 11 18:07:34 UTC 2012 x86_64 >[ 22.971] Kernel command line: BOOT_IMAGE=/vmlinuz-3.6.10-2.fc17.x86_64 root=UUID=2af1cdbe-fc86-4ea3-93c4-68e5c6707f64 ro rd.md=0 rd.lvm=0 rd.dm=0 SYSFONT=True KEYTABLE=pl2 rd.luks=0 LANG=pl_PL.UTF-8 rhgb quiet >[ 22.971] Build Date: 28 November 2012 05:10:39PM >[ 22.971] Build ID: xorg-x11-server 1.12.4-1.fc17 >[ 22.971] Current version of pixman: 0.24.4 >[ 22.971] Before reporting problems, check http://wiki.x.org > to make sure that you have the latest version. >[ 22.971] Markers: (--) probed, (**) from config file, (==) default setting, > (++) from command line, (!!) notice, (II) informational, > (WW) warning, (EE) error, (NI) not implemented, (??) unknown. >[ 22.971] (==) Log file: "/var/log/Xorg.0.log", Time: Wed Jan 2 07:47:37 2013 >[ 22.986] (==) Using config directory: "/etc/X11/xorg.conf.d" >[ 22.986] (==) Using system config directory "/usr/share/X11/xorg.conf.d" >[ 22.986] (==) No Layout section. Using the first Screen section. >[ 22.986] (==) No screen section available. Using defaults. >[ 22.986] (**) |-->Screen "Default Screen Section" (0) >[ 22.986] (**) | |-->Monitor "<default monitor>" >[ 22.986] (==) No monitor specified for screen "Default Screen Section". > Using a default monitor configuration. >[ 22.986] (==) Automatically adding devices >[ 22.986] (==) Automatically enabling devices >[ 22.986] (==) FontPath set to: > catalogue:/etc/X11/fontpath.d, > built-ins >[ 22.986] (==) ModulePath set to "/usr/lib64/xorg/modules" >[ 22.986] (II) The server relies on udev to provide the list of input devices. > If no devices become available, reconfigure udev or disable AutoAddDevices. >[ 22.986] (II) Loader magic: 0x7c6ac0 >[ 22.986] (II) Module ABI versions: >[ 22.986] X.Org ANSI C Emulation: 0.4 >[ 22.986] X.Org Video Driver: 12.1 >[ 22.986] X.Org XInput driver : 16.0 >[ 22.986] X.Org Server Extension : 6.0 >[ 22.988] (--) PCI:*(0:1:5:0) 1002:791e:1043:826d rev 0, Mem @ 0xf0000000/134217728, 0xfdce0000/65536, 0xfdb00000/1048576, I/O @ 0x0000de00/256, BIOS @ 0x????????/131072 >[ 22.988] (II) LoadModule: "extmod" >[ 22.988] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so >[ 22.992] (II) Module extmod: vendor="X.Org Foundation" >[ 22.992] compiled for 1.12.4, module version = 1.0.0 >[ 22.992] Module class: X.Org Server Extension >[ 22.992] ABI class: X.Org Server Extension, version 6.0 >[ 22.992] (II) Loading extension SELinux >[ 22.992] (II) Loading extension MIT-SCREEN-SAVER >[ 22.992] (II) Loading extension XFree86-VidModeExtension >[ 22.992] (II) Loading extension XFree86-DGA >[ 22.992] (II) Loading extension DPMS >[ 22.992] (II) Loading extension XVideo >[ 22.992] (II) Loading extension XVideo-MotionCompensation >[ 22.992] (II) Loading extension X-Resource >[ 22.992] (II) LoadModule: "dbe" >[ 22.993] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so >[ 22.993] (II) Module dbe: vendor="X.Org Foundation" >[ 22.993] compiled for 1.12.4, module version = 1.0.0 >[ 22.993] Module class: X.Org Server Extension >[ 22.993] ABI class: X.Org Server Extension, version 6.0 >[ 22.993] (II) Loading extension DOUBLE-BUFFER >[ 22.993] (II) LoadModule: "glx" >[ 22.993] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so >[ 22.993] (II) Module glx: vendor="X.Org Foundation" >[ 22.993] compiled for 1.12.4, module version = 1.0.0 >[ 22.993] ABI class: X.Org Server Extension, version 6.0 >[ 22.993] (==) AIGLX enabled >[ 22.993] (II) Loading extension GLX >[ 22.993] (II) LoadModule: "record" >[ 23.003] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so >[ 23.003] (II) Module record: vendor="X.Org Foundation" >[ 23.003] compiled for 1.12.4, module version = 1.13.0 >[ 23.003] Module class: X.Org Server Extension >[ 23.003] ABI class: X.Org Server Extension, version 6.0 >[ 23.003] (II) Loading extension RECORD >[ 23.003] (II) LoadModule: "dri" >[ 23.009] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so >[ 23.010] (II) Module dri: vendor="X.Org Foundation" >[ 23.010] compiled for 1.12.4, module version = 1.0.0 >[ 23.010] ABI class: X.Org Server Extension, version 6.0 >[ 23.010] (II) Loading extension XFree86-DRI >[ 23.010] (II) LoadModule: "dri2" >[ 23.013] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so >[ 23.024] (II) Module dri2: vendor="X.Org Foundation" >[ 23.024] compiled for 1.12.4, module version = 1.2.0 >[ 23.024] ABI class: X.Org Server Extension, version 6.0 >[ 23.024] (II) Loading extension DRI2 >[ 23.024] (==) Matched ati as autoconfigured driver 0 >[ 23.024] (==) Matched vesa as autoconfigured driver 1 >[ 23.024] (==) Matched modesetting as autoconfigured driver 2 >[ 23.024] (==) Matched fbdev as autoconfigured driver 3 >[ 23.024] (==) Assigned the driver to the xf86ConfigLayout >[ 23.024] (II) LoadModule: "ati" >[ 23.025] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so >[ 23.026] (II) Module ati: vendor="X.Org Foundation" >[ 23.026] compiled for 1.12.0, module version = 6.14.99 >[ 23.026] Module class: X.Org Video Driver >[ 23.026] ABI class: X.Org Video Driver, version 12.0 >[ 23.026] (II) LoadModule: "radeon" >[ 23.028] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so >[ 23.028] (II) Module radeon: vendor="X.Org Foundation" >[ 23.028] compiled for 1.12.0, module version = 6.14.99 >[ 23.028] Module class: X.Org Video Driver >[ 23.028] ABI class: X.Org Video Driver, version 12.0 >[ 23.028] (II) LoadModule: "vesa" >[ 23.029] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so >[ 23.029] (II) Module vesa: vendor="X.Org Foundation" >[ 23.029] compiled for 1.12.0, module version = 2.3.1 >[ 23.029] Module class: X.Org Video Driver >[ 23.029] ABI class: X.Org Video Driver, version 12.0 >[ 23.029] (II) LoadModule: "modesetting" >[ 23.029] (WW) Warning, couldn't open module modesetting >[ 23.029] (II) UnloadModule: "modesetting" >[ 23.029] (II) Unloading modesetting >[ 23.029] (EE) Failed to load module "modesetting" (module does not exist, 0) >[ 23.029] (II) LoadModule: "fbdev" >[ 23.029] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so >[ 23.029] (II) Module fbdev: vendor="X.Org Foundation" >[ 23.029] compiled for 1.11.99.901, module version = 0.4.2 >[ 23.029] ABI class: X.Org Video Driver, version 12.0 >[ 23.029] (II) RADEON: Driver for ATI Radeon chipsets: > ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI), > ATI Radeon Mobility X300 (M24) 3152 (PCIE), > ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI), > ATI Radeon X600 (RV380) 3E50 (PCIE), > ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136, > ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP), > ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), > ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP), > ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), > ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP), > ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), > ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650, > ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237, > ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336, > ATI Radeon IGP330M/340M/350M (U2) 4337, > ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI), > ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP), > ATI Radeon X800PRO (R420) JI (AGP), > ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP), > ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP), > ATI Radeon Mobility 9800 (M18) JN (AGP), > ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP), > ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP), > ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP), > ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP), > ATI Radeon Mobility M7 LW (AGP), > ATI Mobility FireGL 7800 M7 LX (AGP), > ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), > ATI FireGL Mobility 9000 (M9) Ld (AGP), > ATI Radeon Mobility 9000 (M9) Lf (AGP), > ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI, > ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), > ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP), > ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), > ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP), > ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP), > ATI Radeon Mobility 9600 (M10) NQ (AGP), > ATI Radeon Mobility 9600 (M11) NR (AGP), > ATI Radeon Mobility 9600 (M10) NS (AGP), > ATI FireGL Mobility T2 (M10) NT (AGP), > ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP), > ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), > ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), > ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI), > ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI), > ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI), > ATI Radeon Mobility X300 (M22) 5460 (PCIE), > ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE), > ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE), > ATI Radeon X800PRO (R423) UI (PCIE), > ATI Radeon X800LE (R423) UJ (PCIE), > ATI Radeon X800SE (R423) UK (PCIE), > ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE), > ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE), > ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE), > ATI FireGL unknown (R423) UR (PCIE), > ATI FireGL unknown (R423) UT (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility Radeon X700 XL (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834, > ATI Radeon Mobility 9100 IGP (U3) 5835, > ATI Radeon XPRESS 200 5954 (PCIE), > ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP), > ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), > ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI), > ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE), > ATI Radeon XPRESS 200M 5975 (PCIE), > ATI Radeon XPRESS 200 5A41 (PCIE), > ATI Radeon XPRESS 200M 5A42 (PCIE), > ATI Radeon XPRESS 200 5A61 (PCIE), > ATI Radeon XPRESS 200M 5A62 (PCIE), > ATI Radeon X300 (RV370) 5B60 (PCIE), > ATI Radeon X600 (RV370) 5B62 (PCIE), > ATI Radeon X550 (RV370) 5B63 (PCIE), > ATI FireGL V3100 (RV370) 5B64 (PCIE), > ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE), > ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), > ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), > ATI Mobility Radeon X800 XT (M28) (PCIE), > ATI Mobility FireGL V5100 (M28) (PCIE), > ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE), > ATI Radeon X850 XT PE (R480) (PCIE), > ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE), > ATI unknown Radeon / FireGL (R480) 5D50 (PCIE), > ATI Radeon X850 XT (R480) (PCIE), > ATI Radeon X800XT (R423) 5D57 (PCIE), > ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE), > ATI Radeon X700 PRO (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800, > ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800, > ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300, > ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800, > ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800, > ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505, > ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL, > ATI Mobility Radeon X1400, ATI Radeon X1300/X1550, > ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300, > ATI Mobility Radeon X1300, ATI Mobility Radeon X1300, > ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300, > ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350, > ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550, > ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450, > ATI Radeon X1300/X1550, ATI Mobility Radeon X2300, > ATI Mobility Radeon X2300, ATI Mobility Radeon X1350, > ATI Mobility Radeon X1350, ATI Mobility Radeon X1450, > ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350, > ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600, > ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600, > ATI Mobility FireGL V5200, ATI Mobility Radeon X1600, > ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600, > ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400, > ATI Mobility FireGL V5250, ATI Mobility Radeon X1700, > ATI Mobility Radeon X1700 XT, ATI FireGL V5200, > ATI Mobility Radeon X1700, ATI Radeon X2300HD, > ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300, > ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950, > ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560, > ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400, > ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560, > ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835, > ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200, > ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740, > ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT, > ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT, > ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600, > ATI Radeon 4800 Series, ATI Radeon HD 4870 x2, > ATI Radeon 4800 Series, ATI Radeon HD 4850 x2, > ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL), > ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2, > ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270, > AMD FireStream 9250, ATI FirePro V8700 (FireGL), > ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98, > ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series, > ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98, > ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP), > ATI Mobility Radeon HD 4670, ATI FirePro M5750, > ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP), > ATI RV730XT [Radeon HD 4670], ATI RADEON E4600, > ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650], > ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL), > ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830, > ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740, > ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770, > ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT, > ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000, > ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT, > ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610, > ATI FireMV 2260, ATI RV670, ATI Radeon HD3870, > ATI Mobility Radeon HD 3850, ATI Radeon HD3850, > ATI Mobility Radeon HD 3850 X2, ATI RV670, > ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2, > ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850, > ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550, > ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710, > ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series, > ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series, > ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630, > ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT, > ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP, > ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630, > ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600, > ATI FireGL V3600, ATI Radeon HD 2600 LE, > ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470, > ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series, > ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430, > ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450, > ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series, > ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO, > ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO, > ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670, > ATI Mobility FireGL V5700, ATI Mobility FireGL V5725, > ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics, > ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics, > ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics, > ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2, > SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200, > ATI Radeon 4100, ATI Mobility Radeon HD 4200, > ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250, > AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics, > AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics, > AMD Radeon HD 6300 Series Graphics, > AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370, > AMD Firestream 9350, ATI Radeon HD 5800 Series, > ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series, > ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series, > ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series, > ATI Mobility Radeon HD 5800 Series, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, > ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series, > ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series, > ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series, > ATI Mobility Radeon HD 5000 Series, > ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670, > ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD, > ATI Mobility Radeon HD 5000 Series, > ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics, > ATI Mobility Radeon Graphics, CEDAR, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR, > ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN, > CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, > AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN, > CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series, > BARTS, BARTS, Mobility Radeon HD 6000 Series, > Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS, > AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series, > AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, > CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA, > ARUBA, ARUBA, ARUBA, ARUBA >[ 23.068] (II) VESA: driver for VESA chipsets: vesa >[ 23.068] (II) FBDEV: driver for framebuffer: fbdev >[ 23.068] (++) using VT number 1 > >[ 23.070] (II) [KMS] Kernel modesetting enabled. >[ 23.070] (WW) Falling back to old probe method for vesa >[ 23.070] (WW) Falling back to old probe method for fbdev >[ 23.070] (II) Loading sub module "fbdevhw" >[ 23.070] (II) LoadModule: "fbdevhw" >[ 23.070] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so >[ 23.071] (II) Module fbdevhw: vendor="X.Org Foundation" >[ 23.071] compiled for 1.12.4, module version = 0.0.2 >[ 23.071] ABI class: X.Org Video Driver, version 12.1 >[ 23.071] (II) RADEON(0): RADEONPreInit_KMS >[ 23.071] (II) RADEON(0): Creating default Display subsection in Screen section > "Default Screen Section" for depth/fbbpp 24/32 >[ 23.071] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32 >[ 23.071] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) >[ 23.071] (==) RADEON(0): Default visual is TrueColor >[ 23.071] (==) RADEON(0): RGB weight 888 >[ 23.071] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC) >[ 23.071] (--) RADEON(0): Chipset: "ATI Radeon X1200" (ChipID = 0x791e) >[ 23.071] (II) RADEON(0): PCI card detected >[ 23.071] drmOpenDevice: node name is /dev/dri/card0 >[ 23.071] drmOpenDevice: open result is 8, (OK) >[ 23.071] drmOpenByBusid: Searching for BusID pci:0000:01:05.0 >[ 23.071] drmOpenDevice: node name is /dev/dri/card0 >[ 23.071] drmOpenDevice: open result is 8, (OK) >[ 23.071] drmOpenByBusid: drmOpenMinor returns 8 >[ 23.071] drmOpenByBusid: drmGetBusid reports pci:0000:01:05.0 >[ 23.071] (II) Loading sub module "exa" >[ 23.071] (II) LoadModule: "exa" >[ 23.079] (II) Loading /usr/lib64/xorg/modules/libexa.so >[ 23.079] (II) Module exa: vendor="X.Org Foundation" >[ 23.079] compiled for 1.12.4, module version = 2.5.0 >[ 23.079] ABI class: X.Org Video Driver, version 12.1 >[ 23.079] (II) RADEON(0): KMS Color Tiling: enabled >[ 23.079] (II) RADEON(0): KMS Pageflipping: enabled >[ 23.079] (II) RADEON(0): SwapBuffers wait for vsync: enabled >[ 23.215] (II) RADEON(0): Output VGA-0 has no monitor section >[ 23.347] (II) RADEON(0): Output S-video has no monitor section >[ 23.349] (II) RADEON(0): Output HDMI-0 has no monitor section >[ 23.379] (II) RADEON(0): Output DVI-0 has no monitor section >[ 23.514] (II) RADEON(0): EDID for output VGA-0 >[ 23.646] (II) RADEON(0): EDID for output S-video >[ 23.648] (II) RADEON(0): EDID for output HDMI-0 >[ 23.678] (II) RADEON(0): EDID for output DVI-0 >[ 23.678] (II) RADEON(0): Manufacturer: ENC Model: 1837 Serial#: 16843009 >[ 23.678] (II) RADEON(0): Year: 2007 Week: 23 >[ 23.678] (II) RADEON(0): EDID Version: 1.3 >[ 23.678] (II) RADEON(0): Digital Display Input >[ 23.678] (II) RADEON(0): Max Image Size [cm]: horiz.: 38 vert.: 30 >[ 23.678] (II) RADEON(0): Gamma: 2.20 >[ 23.678] (II) RADEON(0): DPMS capabilities: StandBy Suspend Off >[ 23.678] (II) RADEON(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 >[ 23.678] (II) RADEON(0): First detailed timing is preferred mode >[ 23.678] (II) RADEON(0): redX: 0.640 redY: 0.340 greenX: 0.290 greenY: 0.610 >[ 23.679] (II) RADEON(0): blueX: 0.140 blueY: 0.070 whiteX: 0.313 whiteY: 0.329 >[ 23.679] (II) RADEON(0): Supported established timings: >[ 23.679] (II) RADEON(0): 720x400@70Hz >[ 23.679] (II) RADEON(0): 640x480@60Hz >[ 23.679] (II) RADEON(0): 800x600@60Hz >[ 23.679] (II) RADEON(0): 1024x768@60Hz >[ 23.679] (II) RADEON(0): Manufacturer's mask: 0 >[ 23.679] (II) RADEON(0): Supported standard timings: >[ 23.679] (II) RADEON(0): #0: hsize: 1280 vsize 1024 refresh: 60 vid: 32897 >[ 23.679] (II) RADEON(0): Supported detailed timing: >[ 23.679] (II) RADEON(0): clock: 108.0 MHz Image Size: 376 x 301 mm >[ 23.679] (II) RADEON(0): h_active: 1280 h_sync: 1328 h_sync_end 1440 h_blank_end 1688 h_border: 0 >[ 23.679] (II) RADEON(0): v_active: 1024 v_sync: 1025 v_sync_end 1028 v_blanking: 1066 v_border: 0 >[ 23.679] (II) RADEON(0): Serial No: 52441067 >[ 23.679] (II) RADEON(0): Ranges: V min: 59 V max: 61 Hz, H min: 31 H max: 64 kHz, PixClock max 115 MHz >[ 23.679] (II) RADEON(0): Monitor name: S1901 >[ 23.679] (II) RADEON(0): EDID (in hex): >[ 23.679] (II) RADEON(0): 00ffffffffffff0015c3371801010101 >[ 23.679] (II) RADEON(0): 1711010380261e78eac5c5a3574a9c23 >[ 23.679] (II) RADEON(0): 125054a1080081800101010101010101 >[ 23.679] (II) RADEON(0): 010101010101302a009851002a403070 >[ 23.679] (II) RADEON(0): 1300782d1100001e000000ff00353234 >[ 23.679] (II) RADEON(0): 34313036370a20202020000000fd003b >[ 23.679] (II) RADEON(0): 3d1f400b000a202020202020000000fc >[ 23.679] (II) RADEON(0): 0053313930310a202020202020200087 >[ 23.679] (II) RADEON(0): Printing probed modes for output DVI-0 >[ 23.679] (II) RADEON(0): Modeline "1280x1024"x60.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 23.679] (II) RADEON(0): Modeline "1280x960"x60.0 108.00 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync (60.0 kHz e) >[ 23.679] (II) RADEON(0): Modeline "1280x800"x59.9 71.00 1280 1328 1360 1440 800 803 809 823 +hsync -vsync (49.3 kHz e) >[ 23.679] (II) RADEON(0): Modeline "1280x768"x60.0 68.25 1280 1328 1360 1440 768 771 778 790 +hsync -vsync (47.4 kHz e) >[ 23.679] (II) RADEON(0): Modeline "1024x768"x60.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 23.679] (II) RADEON(0): Modeline "1024x576"x60.0 46.97 1024 1064 1168 1312 576 577 580 597 -hsync +vsync (35.8 kHz) >[ 23.680] (II) RADEON(0): Modeline "800x600"x60.3 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 23.680] (II) RADEON(0): Modeline "848x480"x60.0 33.75 848 864 976 1088 480 486 494 517 +hsync +vsync (31.0 kHz e) >[ 23.680] (II) RADEON(0): Modeline "640x480"x60.0 25.20 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 23.680] (II) RADEON(0): Modeline "720x400"x70.1 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 23.680] (II) RADEON(0): Output VGA-0 disconnected >[ 23.680] (II) RADEON(0): Output S-video disconnected >[ 23.680] (II) RADEON(0): Output HDMI-0 disconnected >[ 23.680] (II) RADEON(0): Output DVI-0 connected >[ 23.680] (II) RADEON(0): Using exact sizes for initial modes >[ 23.680] (II) RADEON(0): Output DVI-0 using initial mode 1280x1024 +0+0 >[ 23.680] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated. >[ 23.680] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:10000000 visible:fac0000 >[ 23.680] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM >[ 23.680] (==) RADEON(0): DPI set to (96, 96) >[ 23.680] (II) Loading sub module "fb" >[ 23.680] (II) LoadModule: "fb" >[ 23.681] (II) Loading /usr/lib64/xorg/modules/libfb.so >[ 23.682] (II) Module fb: vendor="X.Org Foundation" >[ 23.682] compiled for 1.12.4, module version = 1.0.0 >[ 23.682] ABI class: X.Org ANSI C Emulation, version 0.4 >[ 23.682] (II) Loading sub module "ramdac" >[ 23.682] (II) LoadModule: "ramdac" >[ 23.682] (II) Module "ramdac" already built-in >[ 23.682] (II) UnloadModule: "vesa" >[ 23.682] (II) Unloading vesa >[ 23.682] (II) UnloadModule: "fbdev" >[ 23.682] (II) Unloading fbdev >[ 23.682] (II) UnloadSubModule: "fbdevhw" >[ 23.682] (II) Unloading fbdevhw >[ 23.682] (--) Depth 24 pixmap format is 32 bpp >[ 23.683] (II) RADEON(0): [DRI2] Setup complete >[ 23.683] (II) RADEON(0): [DRI2] DRI driver: r300 >[ 23.683] (II) RADEON(0): [DRI2] VDPAU driver: r300 >[ 23.683] (II) RADEON(0): Front buffer size: 5120K >[ 23.683] (II) RADEON(0): VRAM usage limit set to 226483K >[ 23.684] (II) RADEON(0): Initializing backing store >[ 23.684] (==) RADEON(0): Backing store disabled >[ 23.684] (II) RADEON(0): Direct rendering enabled >[ 23.684] (II) RADEON(0): Initializing Acceleration >[ 23.684] (II) RADEON(0): Render acceleration enabled for R300/R400/R500 type cards. >[ 23.684] (II) RADEON(0): Setting EXA maxPitchBytes >[ 23.684] (II) RADEON(0): EngineInit (32/32) >[ 23.684] (II) EXA(0): Driver allocated offscreen pixmaps >[ 23.684] (II) EXA(0): Driver registered support for the following operations: >[ 23.684] (II) Solid >[ 23.684] (II) Copy >[ 23.684] (II) Composite (RENDER acceleration) >[ 23.684] (II) UploadToScreen >[ 23.684] (II) DownloadFromScreen >[ 23.684] (II) RADEON(0): Acceleration enabled >[ 23.684] (II) RADEON(0): Initializing DPMS >[ 23.684] (==) RADEON(0): DPMS enabled >[ 23.684] (II) RADEON(0): Initializing Cursor >[ 23.684] (==) RADEON(0): Silken mouse enabled >[ 23.684] (II) RADEON(0): Initializing Xv >[ 23.684] (II) RADEON(0): Set up textured video >[ 23.685] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video. >[ 23.685] (II) RADEON(0): [XvMC] Extension initialized. >[ 23.685] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message. >[ 23.685] (II) RADEON(0): Initializing kms color map >[ 23.685] (II) RADEON(0): RADEONScreenInit finished >[ 23.685] (--) RandR disabled >[ 23.685] (II) Initializing built-in extension Generic Event Extension >[ 23.685] (II) Initializing built-in extension SHAPE >[ 23.685] (II) Initializing built-in extension MIT-SHM >[ 23.685] (II) Initializing built-in extension XInputExtension >[ 23.685] (II) Initializing built-in extension XTEST >[ 23.685] (II) Initializing built-in extension BIG-REQUESTS >[ 23.685] (II) Initializing built-in extension SYNC >[ 23.686] (II) Initializing built-in extension XKEYBOARD >[ 23.686] (II) Initializing built-in extension XC-MISC >[ 23.686] (II) Initializing built-in extension XINERAMA >[ 23.686] (II) Initializing built-in extension XFIXES >[ 23.686] (II) Initializing built-in extension RENDER >[ 23.686] (II) Initializing built-in extension RANDR >[ 23.686] (II) Initializing built-in extension COMPOSITE >[ 23.686] (II) Initializing built-in extension DAMAGE >[ 23.690] (II) SELinux: Disabled by boolean >[ 26.713] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer >[ 26.713] (II) AIGLX: enabled GLX_INTEL_swap_event >[ 26.714] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control >[ 26.714] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects >[ 26.715] (II) AIGLX: Loaded and initialized r300 >[ 26.715] (II) GLX: Initialized DRI2 GL provider for screen 0 >[ 26.719] (II) RADEON(0): Setting screen physical size to 338 x 270 >[ 28.603] (II) XKB: Reusing cached keymap >[ 28.612] (II) config/udev: Adding input device Power Button (/dev/input/event1) >[ 28.612] (**) Power Button: Applying InputClass "evdev keyboard catchall" >[ 28.612] (**) Power Button: Applying InputClass "system-setup-keyboard" >[ 28.612] (II) LoadModule: "evdev" >[ 28.612] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so >[ 28.613] (II) Module evdev: vendor="X.Org Foundation" >[ 28.613] compiled for 1.12.0, module version = 2.7.0 >[ 28.613] Module class: X.Org XInput Driver >[ 28.613] ABI class: X.Org XInput driver, version 16.0 >[ 28.613] (II) Using input driver 'evdev' for 'Power Button' >[ 28.613] Option "XkbRules" "evdev" >[ 28.613] Option "XkbModel" "pc105" >[ 28.613] Option "XkbLayout" "pl" >[ 28.613] Option "_source" "server/udev" >[ 28.613] Option "name" "Power Button" >[ 28.614] Option "path" "/dev/input/event1" >[ 28.614] Option "device" "/dev/input/event1" >[ 28.614] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1" >[ 28.614] Option "driver" "evdev" >[ 28.614] Option "XkbOptions" "terminate:ctrl_alt_bksp," >[ 28.614] (**) Power Button: always reports core events >[ 28.614] (**) evdev: Power Button: Device: "/dev/input/event1" >[ 28.614] (--) evdev: Power Button: Vendor 0 Product 0x1 >[ 28.614] (--) evdev: Power Button: Found keys >[ 28.614] (II) evdev: Power Button: Configuring as keyboard >[ 28.614] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1" >[ 28.614] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6) >[ 28.614] (**) Option "xkb_rules" "evdev" >[ 28.614] (**) Option "xkb_model" "pc105" >[ 28.615] (**) Option "xkb_layout" "pl" >[ 28.615] (**) Option "xkb_options" "terminate:ctrl_alt_bksp," >[ 28.690] (II) config/udev: Adding input device Power Button (/dev/input/event0) >[ 28.690] (**) Power Button: Applying InputClass "evdev keyboard catchall" >[ 28.690] (**) Power Button: Applying InputClass "system-setup-keyboard" >[ 28.690] (II) Using input driver 'evdev' for 'Power Button' >[ 28.690] Option "XkbRules" "evdev" >[ 28.690] Option "XkbModel" "pc105" >[ 28.690] Option "XkbLayout" "pl" >[ 28.690] Option "_source" "server/udev" >[ 28.690] Option "name" "Power Button" >[ 28.690] Option "path" "/dev/input/event0" >[ 28.690] Option "device" "/dev/input/event0" >[ 28.690] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0" >[ 28.690] Option "driver" "evdev" >[ 28.690] Option "XkbOptions" "terminate:ctrl_alt_bksp," >[ 28.690] (**) Power Button: always reports core events >[ 28.690] (**) evdev: Power Button: Device: "/dev/input/event0" >[ 28.690] (--) evdev: Power Button: Vendor 0 Product 0x1 >[ 28.690] (--) evdev: Power Button: Found keys >[ 28.690] (II) evdev: Power Button: Configuring as keyboard >[ 28.690] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0" >[ 28.690] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 7) >[ 28.690] (**) Option "xkb_rules" "evdev" >[ 28.690] (**) Option "xkb_model" "pc105" >[ 28.691] (**) Option "xkb_layout" "pl" >[ 28.691] (**) Option "xkb_options" "terminate:ctrl_alt_bksp," >[ 28.691] (II) XKB: Reusing cached keymap >[ 28.692] (II) config/udev: Adding input device HDA ATI HDMI HDMI/DP,pcm=3 (/dev/input/event9) >[ 28.693] (II) No input driver specified, ignoring this device. >[ 28.693] (II) This device may have been added with another device file. >[ 28.693] (II) config/udev: Adding input device Logitech Logitech USB Keyboard (/dev/input/event2) >[ 28.693] (**) Logitech Logitech USB Keyboard: Applying InputClass "evdev keyboard catchall" >[ 28.694] (**) Logitech Logitech USB Keyboard: Applying InputClass "system-setup-keyboard" >[ 28.694] (II) Using input driver 'evdev' for 'Logitech Logitech USB Keyboard' >[ 28.694] Option "XkbRules" "evdev" >[ 28.694] Option "XkbModel" "pc105" >[ 28.694] Option "XkbLayout" "pl" >[ 28.694] Option "_source" "server/udev" >[ 28.694] Option "name" "Logitech Logitech USB Keyboard" >[ 28.694] Option "path" "/dev/input/event2" >[ 28.694] Option "device" "/dev/input/event2" >[ 28.694] Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:13.1/usb3/3-1/3-1:1.0/input/input2/event2" >[ 28.694] Option "driver" "evdev" >[ 28.694] Option "XkbOptions" "terminate:ctrl_alt_bksp," >[ 28.694] (**) Logitech Logitech USB Keyboard: always reports core events >[ 28.694] (**) evdev: Logitech Logitech USB Keyboard: Device: "/dev/input/event2" >[ 28.694] (--) evdev: Logitech Logitech USB Keyboard: Vendor 0x46d Product 0xc315 >[ 28.694] (--) evdev: Logitech Logitech USB Keyboard: Found keys >[ 28.694] (II) evdev: Logitech Logitech USB Keyboard: Configuring as keyboard >[ 28.694] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:13.1/usb3/3-1/3-1:1.0/input/input2/event2" >[ 28.694] (II) XINPUT: Adding extended input device "Logitech Logitech USB Keyboard" (type: KEYBOARD, id 8) >[ 28.694] (**) Option "xkb_rules" "evdev" >[ 28.694] (**) Option "xkb_model" "pc105" >[ 28.694] (**) Option "xkb_layout" "pl" >[ 28.694] (**) Option "xkb_options" "terminate:ctrl_alt_bksp," >[ 28.694] (II) XKB: Reusing cached keymap >[ 28.700] (II) config/udev: Adding input device A4Tech USB Mouse (/dev/input/event3) >[ 28.701] (**) A4Tech USB Mouse: Applying InputClass "evdev pointer catchall" >[ 28.701] (II) Using input driver 'evdev' for 'A4Tech USB Mouse' >[ 28.701] Option "XkbRules" "evdev" >[ 28.701] Option "XkbModel" "evdev" >[ 28.701] Option "XkbLayout" "us" >[ 28.701] Option "_source" "server/udev" >[ 28.701] Option "name" "A4Tech USB Mouse" >[ 28.701] Option "path" "/dev/input/event3" >[ 28.701] Option "device" "/dev/input/event3" >[ 28.701] Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:13.1/usb3/3-2/3-2:1.0/input/input3/event3" >[ 28.701] Option "driver" "evdev" >[ 28.701] (**) A4Tech USB Mouse: always reports core events >[ 28.701] (**) evdev: A4Tech USB Mouse: Device: "/dev/input/event3" >[ 28.701] (--) evdev: A4Tech USB Mouse: Vendor 0x9da Product 0xa >[ 28.701] (--) evdev: A4Tech USB Mouse: Found 12 mouse buttons >[ 28.701] (--) evdev: A4Tech USB Mouse: Found scroll wheel(s) >[ 28.702] (--) evdev: A4Tech USB Mouse: Found relative axes >[ 28.702] (--) evdev: A4Tech USB Mouse: Found x and y relative axes >[ 28.702] (II) evdev: A4Tech USB Mouse: Configuring as mouse >[ 28.702] (II) evdev: A4Tech USB Mouse: Adding scrollwheel support >[ 28.702] (**) evdev: A4Tech USB Mouse: YAxisMapping: buttons 4 and 5 >[ 28.702] (**) evdev: A4Tech USB Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200 >[ 28.702] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:13.1/usb3/3-2/3-2:1.0/input/input3/event3" >[ 28.702] (II) XINPUT: Adding extended input device "A4Tech USB Mouse" (type: MOUSE, id 9) >[ 28.704] (II) evdev: A4Tech USB Mouse: initialized for relative axes. >[ 28.705] (**) A4Tech USB Mouse: (accel) keeping acceleration scheme 1 >[ 28.705] (**) A4Tech USB Mouse: (accel) acceleration profile 0 >[ 28.705] (**) A4Tech USB Mouse: (accel) acceleration factor: 2.000 >[ 28.706] (**) A4Tech USB Mouse: (accel) acceleration threshold: 4 >[ 28.707] (II) config/udev: Adding input device A4Tech USB Mouse (/dev/input/mouse0) >[ 28.707] (II) No input driver specified, ignoring this device. >[ 28.707] (II) This device may have been added with another device file. >[ 28.708] (II) config/udev: Adding input device HDA ATI SB Line (/dev/input/event4) >[ 28.708] (II) No input driver specified, ignoring this device. >[ 28.708] (II) This device may have been added with another device file. >[ 28.708] (II) config/udev: Adding input device HDA ATI SB Front Mic (/dev/input/event5) >[ 28.709] (II) No input driver specified, ignoring this device. >[ 28.709] (II) This device may have been added with another device file. >[ 28.710] (II) config/udev: Adding input device HDA ATI SB Rear Mic (/dev/input/event6) >[ 28.710] (II) No input driver specified, ignoring this device. >[ 28.710] (II) This device may have been added with another device file. >[ 28.711] (II) config/udev: Adding input device HDA ATI SB Front Headphone (/dev/input/event7) >[ 28.711] (II) No input driver specified, ignoring this device. >[ 28.711] (II) This device may have been added with another device file. >[ 28.711] (II) config/udev: Adding input device HDA ATI SB Line Out (/dev/input/event8) >[ 28.712] (II) No input driver specified, ignoring this device. >[ 28.712] (II) This device may have been added with another device file. >[ 28.726] (II) RADEON(0): RADEONSaveScreen(2) >[ 29.041] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 29.041] (II) RADEON(0): Using EDID range info for horizontal sync >[ 29.041] (II) RADEON(0): Using EDID range info for vertical refresh >[ 29.041] (II) RADEON(0): Printing DDC gathered Modelines: >[ 29.041] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 29.041] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 29.041] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 29.041] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 29.041] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 30.904] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 30.904] (II) RADEON(0): Using hsync ranges from config file >[ 30.904] (II) RADEON(0): Using vrefresh ranges from config file >[ 30.904] (II) RADEON(0): Printing DDC gathered Modelines: >[ 30.904] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 30.904] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 30.904] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 30.904] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 30.904] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 34.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x297fd10] >[ 35.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x297fd10] width 1280 pitch 5120 (/4 1280) >[ 35.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x297fcb0] >[ 35.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x297fcb0] width 1280 pitch 5120 (/4 1280) >[ 35.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x297fd10] >[ 35.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x297fd10] width 1280 pitch 5120 (/4 1280) >[ 35.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 35.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 35.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 35.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 35.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 35.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 35.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 35.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 35.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 35.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 35.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 35.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 35.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 35.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 35.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 35.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 35.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 35.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 35.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 35.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 35.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 35.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 35.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 35.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 36.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 36.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 36.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 36.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 36.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 36.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 36.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 36.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 36.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 36.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 36.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 36.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 36.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 36.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 36.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982810] >[ 36.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982810] width 1280 pitch 5120 (/4 1280) >[ 36.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982870] >[ 36.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982870] width 1280 pitch 5120 (/4 1280) >[ 37.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982830] >[ 37.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982830] width 1280 pitch 5120 (/4 1280) >[ 37.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982760] >[ 37.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982760] width 1280 pitch 5120 (/4 1280) >[ 37.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982830] >[ 37.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982830] width 1280 pitch 5120 (/4 1280) >[ 37.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982760] >[ 37.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982760] width 1280 pitch 5120 (/4 1280) >[ 37.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982830] >[ 37.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982830] width 1280 pitch 5120 (/4 1280) >[ 37.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982760] >[ 37.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982760] width 1280 pitch 5120 (/4 1280) >[ 37.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982830] >[ 37.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982830] width 1280 pitch 5120 (/4 1280) >[ 37.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982760] >[ 37.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982760] width 1280 pitch 5120 (/4 1280) >[ 37.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982830] >[ 37.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982830] width 1280 pitch 5120 (/4 1280) >[ 37.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982760] >[ 38.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982760] width 1280 pitch 5120 (/4 1280) >[ 38.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982830] >[ 38.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982830] width 1280 pitch 5120 (/4 1280) >[ 38.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982760] >[ 38.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982760] width 1280 pitch 5120 (/4 1280) >[ 38.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982830] >[ 38.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982830] width 1280 pitch 5120 (/4 1280) >[ 38.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982760] >[ 38.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982760] width 1280 pitch 5120 (/4 1280) >[ 38.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982830] >[ 38.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982830] width 1280 pitch 5120 (/4 1280) >[ 40.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982000] >[ 40.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982000] width 1280 pitch 5120 (/4 1280) >[ 40.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f440] >[ 40.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f440] width 1280 pitch 5120 (/4 1280) >[ 40.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982000] >[ 40.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982000] width 1280 pitch 5120 (/4 1280) >[ 41.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f440] >[ 41.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f440] width 1280 pitch 5120 (/4 1280) >[ 41.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982000] >[ 41.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982000] width 1280 pitch 5120 (/4 1280) >[ 42.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f440] >[ 42.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f440] width 1280 pitch 5120 (/4 1280) >[ 42.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982000] >[ 42.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982000] width 1280 pitch 5120 (/4 1280) >[ 42.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f440] >[ 42.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f440] width 1280 pitch 5120 (/4 1280) >[ 43.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2982000] >[ 43.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2982000] width 1280 pitch 5120 (/4 1280) >[ 43.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f440] >[ 43.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f440] width 1280 pitch 5120 (/4 1280) >[ 46.850] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 46.850] (II) RADEON(0): Using hsync ranges from config file >[ 46.850] (II) RADEON(0): Using vrefresh ranges from config file >[ 46.850] (II) RADEON(0): Printing DDC gathered Modelines: >[ 46.850] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 46.850] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 46.850] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 46.850] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 46.850] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 49.774] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 49.774] (II) RADEON(0): Using hsync ranges from config file >[ 49.774] (II) RADEON(0): Using vrefresh ranges from config file >[ 49.774] (II) RADEON(0): Printing DDC gathered Modelines: >[ 49.774] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 49.774] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 49.774] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 49.774] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 49.774] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 54.262] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 54.262] (II) RADEON(0): Using hsync ranges from config file >[ 54.262] (II) RADEON(0): Using vrefresh ranges from config file >[ 54.262] (II) RADEON(0): Printing DDC gathered Modelines: >[ 54.262] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 54.262] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 54.262] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 54.263] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 54.263] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 60.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e6cb0] >[ 60.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e6cb0] width 1280 pitch 5120 (/4 1280) >[ 66.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ec630] >[ 66.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ec630] width 1280 pitch 5120 (/4 1280) >[ 66.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34086f0] >[ 66.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34086f0] width 1280 pitch 5120 (/4 1280) >[ 66.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406b60] >[ 66.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406b60] width 1280 pitch 5120 (/4 1280) >[ 66.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34086f0] >[ 66.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34086f0] width 1280 pitch 5120 (/4 1280) >[ 76.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ac00] >[ 77.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ac00] width 1280 pitch 5120 (/4 1280) >[ 78.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 78.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 81.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ac00] >[ 81.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ac00] width 1280 pitch 5120 (/4 1280) >[ 81.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 81.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 82.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 82.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 82.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 82.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 82.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 82.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 82.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 82.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 82.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 82.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 82.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 82.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 82.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 82.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 82.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 82.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 83.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 83.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 83.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 83.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 84.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 84.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 84.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 84.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 84.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 84.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 84.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 84.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 84.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 84.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 86.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 86.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 86.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 86.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 86.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 86.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 86.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340adb0] >[ 86.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340adb0] width 1280 pitch 5120 (/4 1280) >[ 87.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 87.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 87.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340adb0] >[ 87.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340adb0] width 1280 pitch 5120 (/4 1280) >[ 87.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 87.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 87.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a030] >[ 87.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a030] width 1280 pitch 5120 (/4 1280) >[ 89.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340adb0] >[ 89.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340adb0] width 1280 pitch 5120 (/4 1280) >[ 89.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab20] >[ 89.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab20] width 1280 pitch 5120 (/4 1280) >[ 89.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340abf0] >[ 89.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340abf0] width 1280 pitch 5120 (/4 1280) >[ 89.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ebc60] >[ 89.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ebc60] width 1280 pitch 5120 (/4 1280) >[ 90.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340abf0] >[ 90.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340abf0] width 1280 pitch 5120 (/4 1280) >[ 90.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ebc60] >[ 90.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ebc60] width 1280 pitch 5120 (/4 1280) >[ 90.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340abf0] >[ 90.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340abf0] width 1280 pitch 5120 (/4 1280) >[ 98.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3441a60] >[ 98.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3441a60] width 1280 pitch 5120 (/4 1280) >[ 148.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3408690] >[ 148.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3408690] width 1280 pitch 5120 (/4 1280) >[ 1182.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1182.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1183.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1183.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1183.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1183.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1183.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1183.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1183.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1183.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1183.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1183.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1183.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1183.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1183.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1183.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1183.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1183.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1184.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1184.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1184.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1184.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1189.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1189.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1189.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1189.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1189.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1190.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1190.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1190.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1190.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1190.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1190.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1190.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1190.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1190.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1191.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1191.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1191.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1191.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1191.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351faa0] >[ 1191.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351faa0] width 1280 pitch 5120 (/4 1280) >[ 1191.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3523000] >[ 1191.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3523000] width 1280 pitch 5120 (/4 1280) >[ 1192.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3504b60] >[ 1192.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3504b60] width 1280 pitch 5120 (/4 1280) >[ 1192.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3440c20] >[ 1192.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3440c20] width 1280 pitch 5120 (/4 1280) >[ 1192.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3411400] >[ 1192.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3411400] width 1280 pitch 5120 (/4 1280) >[ 1192.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3523000] >[ 1192.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3523000] width 1280 pitch 5120 (/4 1280) >[ 1192.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3411400] >[ 1192.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3411400] width 1280 pitch 5120 (/4 1280) >[ 1192.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3523000] >[ 1192.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3523000] width 1280 pitch 5120 (/4 1280) >[ 1192.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3411400] >[ 1192.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3411400] width 1280 pitch 5120 (/4 1280) >[ 1192.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351faa0] >[ 1192.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351faa0] width 1280 pitch 5120 (/4 1280) >[ 1196.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352dde0] >[ 1196.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352dde0] width 1280 pitch 5120 (/4 1280) >[ 1196.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352dde0] >[ 1196.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352dde0] width 1280 pitch 5120 (/4 1280) >[ 1196.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3523000] >[ 1196.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3523000] width 1280 pitch 5120 (/4 1280) >[ 1196.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352dde0] >[ 1196.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352dde0] width 1280 pitch 5120 (/4 1280) >[ 1196.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3523000] >[ 1196.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3523000] width 1280 pitch 5120 (/4 1280) >[ 1196.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352dde0] >[ 1196.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352dde0] width 1280 pitch 5120 (/4 1280) >[ 1196.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352dbf0] >[ 1196.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352dbf0] width 1280 pitch 5120 (/4 1280) >[ 1196.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352daa0] >[ 1196.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352daa0] width 1280 pitch 5120 (/4 1280) >[ 1196.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352d780] >[ 1196.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352d780] width 1280 pitch 5120 (/4 1280) >[ 1204.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3689710] >[ 1204.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3689710] width 1280 pitch 5120 (/4 1280) >[ 1231.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31b80] >[ 1231.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31b80] width 1280 pitch 5120 (/4 1280) >[ 1231.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3694d60] >[ 1231.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3694d60] width 1280 pitch 5120 (/4 1280) >[ 1231.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31b80] >[ 1231.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31b80] width 1280 pitch 5120 (/4 1280) >[ 1231.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3694d60] >[ 1231.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3694d60] width 1280 pitch 5120 (/4 1280) >[ 1231.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31b80] >[ 1231.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31b80] width 1280 pitch 5120 (/4 1280) >[ 1231.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d0e0] >[ 1231.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d0e0] width 1280 pitch 5120 (/4 1280) >[ 1234.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1db60] >[ 1234.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1db60] width 1280 pitch 5120 (/4 1280) >[ 1234.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3754730] >[ 1234.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3754730] width 1280 pitch 5120 (/4 1280) >[ 1234.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bbc80] >[ 1234.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bbc80] width 1280 pitch 5120 (/4 1280) >[ 1234.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1bec0] >[ 1234.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1bec0] width 1280 pitch 5120 (/4 1280) >[ 1234.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3750980] >[ 1234.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3750980] width 1280 pitch 5120 (/4 1280) >[ 1234.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1bec0] >[ 1234.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1bec0] width 1280 pitch 5120 (/4 1280) >[ 1235.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375c430] >[ 1235.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375c430] width 1280 pitch 5120 (/4 1280) >[ 1235.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1bec0] >[ 1235.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1bec0] width 1280 pitch 5120 (/4 1280) >[ 1235.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1bec0] >[ 1235.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1bec0] width 1280 pitch 5120 (/4 1280) >[ 1235.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1bec0] >[ 1235.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1bec0] width 1280 pitch 5120 (/4 1280) >[ 1235.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d2e0] >[ 1235.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d2e0] width 1280 pitch 5120 (/4 1280) >[ 1235.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3750850] >[ 1236.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3750850] width 1280 pitch 5120 (/4 1280) >[ 1236.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d2e0] >[ 1236.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d2e0] width 1280 pitch 5120 (/4 1280) >[ 1236.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3750850] >[ 1236.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3750850] width 1280 pitch 5120 (/4 1280) >[ 1236.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751230] >[ 1236.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751230] width 1280 pitch 5120 (/4 1280) >[ 1236.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3750850] >[ 1236.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3750850] width 1280 pitch 5120 (/4 1280) >[ 1236.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3751230] >[ 1236.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3751230] width 1280 pitch 5120 (/4 1280) >[ 1457.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37484f0] >[ 1457.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37484f0] width 1280 pitch 5120 (/4 1280) >[ 1457.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49bc0] >[ 1457.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49bc0] width 1280 pitch 5120 (/4 1280) >[ 1457.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49bc0] >[ 1457.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49bc0] width 1280 pitch 5120 (/4 1280) >[ 1457.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37435f0] >[ 1458.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37435f0] width 1280 pitch 5120 (/4 1280) >[ 1458.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49bc0] >[ 1458.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49bc0] width 1280 pitch 5120 (/4 1280) >[ 1458.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d430] >[ 1458.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d430] width 1280 pitch 5120 (/4 1280) >[ 1458.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f500] >[ 1458.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f500] width 1280 pitch 5120 (/4 1280) >[ 1458.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f680] >[ 1458.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f680] width 1280 pitch 5120 (/4 1280) >[ 1458.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d240] >[ 1458.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d240] width 1280 pitch 5120 (/4 1280) >[ 1459.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f500] >[ 1459.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f500] width 1280 pitch 5120 (/4 1280) >[ 1460.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49bc0] >[ 1460.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49bc0] width 1280 pitch 5120 (/4 1280) >[ 1460.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f500] >[ 1460.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f500] width 1280 pitch 5120 (/4 1280) >[ 1460.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c417c0] >[ 1460.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c417c0] width 1280 pitch 5120 (/4 1280) >[ 1460.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49bc0] >[ 1460.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49bc0] width 1280 pitch 5120 (/4 1280) >[ 1461.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49bc0] >[ 1461.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49bc0] width 1280 pitch 5120 (/4 1280) >[ 1461.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c417c0] >[ 1461.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c417c0] width 1280 pitch 5120 (/4 1280) >[ 1461.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49bc0] >[ 1461.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49bc0] width 1280 pitch 5120 (/4 1280) >[ 1461.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c417c0] >[ 1461.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c417c0] width 1280 pitch 5120 (/4 1280) >[ 1461.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49bc0] >[ 1461.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49bc0] width 1280 pitch 5120 (/4 1280) >[ 1684.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c57d80] >[ 1684.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c57d80] width 1280 pitch 5120 (/4 1280) >[ 1684.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1684.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 1684.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c57d80] >[ 1684.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c57d80] width 1280 pitch 5120 (/4 1280) >[ 1684.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1684.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 1684.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c57d80] >[ 1684.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c57d80] width 1280 pitch 5120 (/4 1280) >[ 1686.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88480] >[ 1686.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88480] width 1280 pitch 5120 (/4 1280) >[ 1686.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8e6f0] >[ 1686.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8e6f0] width 1280 pitch 5120 (/4 1280) >[ 1686.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8e450] >[ 1686.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8e450] width 1280 pitch 5120 (/4 1280) >[ 1687.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8e2f0] >[ 1687.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8e2f0] width 1280 pitch 5120 (/4 1280) >[ 1687.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8e350] >[ 1687.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8e350] width 1280 pitch 5120 (/4 1280) >[ 1687.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8e2f0] >[ 1687.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8e2f0] width 1280 pitch 5120 (/4 1280) >[ 1687.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88880] >[ 1687.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88880] width 1280 pitch 5120 (/4 1280) >[ 1687.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb2000] >[ 1687.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb2000] width 1280 pitch 5120 (/4 1280) >[ 1687.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb4350] >[ 1687.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb4350] width 1280 pitch 5120 (/4 1280) >[ 1687.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb2000] >[ 1687.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb2000] width 1280 pitch 5120 (/4 1280) >[ 1687.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f500] >[ 1687.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f500] width 1280 pitch 5120 (/4 1280) >[ 1687.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb2000] >[ 1687.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb2000] width 1280 pitch 5120 (/4 1280) >[ 1687.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c306e0] >[ 1687.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c306e0] width 1280 pitch 5120 (/4 1280) >[ 1688.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88480] >[ 1688.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88480] width 1280 pitch 5120 (/4 1280) >[ 1688.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c252a0] >[ 1688.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c252a0] width 1280 pitch 5120 (/4 1280) >[ 1688.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb2000] >[ 1688.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb2000] width 1280 pitch 5120 (/4 1280) >[ 1688.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c252a0] >[ 1688.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c252a0] width 1280 pitch 5120 (/4 1280) >[ 1688.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb2000] >[ 1688.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb2000] width 1280 pitch 5120 (/4 1280) >[ 1688.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c252a0] >[ 1688.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c252a0] width 1280 pitch 5120 (/4 1280) >[ 1688.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb2000] >[ 1688.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb2000] width 1280 pitch 5120 (/4 1280) >[ 1688.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c252a0] >[ 1688.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c252a0] width 1280 pitch 5120 (/4 1280) >[ 1892.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c08f0] >[ 1892.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c08f0] width 1280 pitch 5120 (/4 1280) >[ 1892.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c17a0] >[ 1892.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c17a0] width 1280 pitch 5120 (/4 1280) >[ 1892.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b64b0] >[ 1892.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b64b0] width 1280 pitch 5120 (/4 1280) >[ 1892.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1892.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 1892.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b64b0] >[ 1892.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b64b0] width 1280 pitch 5120 (/4 1280) >[ 1892.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1892.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 1892.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b64b0] >[ 1893.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b64b0] width 1280 pitch 5120 (/4 1280) >[ 1893.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1893.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 1893.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b64b0] >[ 1893.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b64b0] width 1280 pitch 5120 (/4 1280) >[ 1893.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1893.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 1893.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b64b0] >[ 1893.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b64b0] width 1280 pitch 5120 (/4 1280) >[ 1894.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1894.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 1894.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b64b0] >[ 1894.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b64b0] width 1280 pitch 5120 (/4 1280) >[ 1894.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1894.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 1895.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b64b0] >[ 1896.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b64b0] width 1280 pitch 5120 (/4 1280) >[ 1896.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34873d0] >[ 1896.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34873d0] width 1280 pitch 5120 (/4 1280) >[ 1896.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3501e20] >[ 1896.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3501e20] width 1280 pitch 5120 (/4 1280) >[ 1896.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3408690] >[ 1896.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3408690] width 1280 pitch 5120 (/4 1280) >[ 1896.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1c770] >[ 1897.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1c770] width 1280 pitch 5120 (/4 1280) >[ 2036.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947f0] >[ 2036.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947f0] width 1280 pitch 5120 (/4 1280) >[ 2036.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d14e0] >[ 2036.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d14e0] width 1280 pitch 5120 (/4 1280) >[ 2557.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f7200] >[ 2557.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f7200] width 1280 pitch 5120 (/4 1280) >[ 2557.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f7010] >[ 2557.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f7010] width 1280 pitch 5120 (/4 1280) >[ 2768.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716230] >[ 2768.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716230] width 1280 pitch 5120 (/4 1280) >[ 2768.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2768.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2768.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716230] >[ 2768.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716230] width 1280 pitch 5120 (/4 1280) >[ 2768.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2768.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2769.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716230] >[ 2769.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716230] width 1280 pitch 5120 (/4 1280) >[ 2769.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2769.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2769.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 2769.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 2769.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2769.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2769.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 2769.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 2769.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2770.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2770.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 2770.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 2770.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2770.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2770.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716230] >[ 2770.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716230] width 1280 pitch 5120 (/4 1280) >[ 2770.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2770.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2770.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716230] >[ 2770.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716230] width 1280 pitch 5120 (/4 1280) >[ 2770.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2770.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2771.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716230] >[ 2771.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716230] width 1280 pitch 5120 (/4 1280) >[ 2771.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 2771.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 2773.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 2773.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 2773.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3720cd0] >[ 2773.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3720cd0] width 1280 pitch 5120 (/4 1280) >[ 2786.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371a040] >[ 2786.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371a040] width 1280 pitch 5120 (/4 1280) >[ 2809.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e490] >[ 2809.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e490] width 1280 pitch 5120 (/4 1280) >[ 2821.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c534e0] >[ 2821.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c534e0] width 1280 pitch 5120 (/4 1280) >[ 2821.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371f260] >[ 2821.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371f260] width 1280 pitch 5120 (/4 1280) >[ 3135.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31be0] >[ 3135.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31be0] width 1280 pitch 5120 (/4 1280) >[ 3135.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f260] >[ 3135.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f260] width 1280 pitch 5120 (/4 1280) >[ 3135.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31be0] >[ 3135.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31be0] width 1280 pitch 5120 (/4 1280) >[ 3135.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f260] >[ 3136.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f260] width 1280 pitch 5120 (/4 1280) >[ 3136.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31be0] >[ 3136.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31be0] width 1280 pitch 5120 (/4 1280) >[ 3136.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f260] >[ 3136.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f260] width 1280 pitch 5120 (/4 1280) >[ 3155.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f950] >[ 3155.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f950] width 1280 pitch 5120 (/4 1280) >[ 3155.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f950] >[ 3155.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f950] width 1280 pitch 5120 (/4 1280) >[ 3155.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c283a0] >[ 3155.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c283a0] width 1280 pitch 5120 (/4 1280) >[ 3155.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f950] >[ 3155.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f950] width 1280 pitch 5120 (/4 1280) >[ 3155.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f950] >[ 3155.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f950] width 1280 pitch 5120 (/4 1280) >[ 3155.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c283a0] >[ 3155.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c283a0] width 1280 pitch 5120 (/4 1280) >[ 3155.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733ec0] >[ 3156.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733ec0] width 1280 pitch 5120 (/4 1280) >[ 3156.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f260] >[ 3156.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f260] width 1280 pitch 5120 (/4 1280) >[ 3156.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733ec0] >[ 3156.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733ec0] width 1280 pitch 5120 (/4 1280) >[ 3156.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f260] >[ 3156.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f260] width 1280 pitch 5120 (/4 1280) >[ 3156.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733ec0] >[ 3156.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733ec0] width 1280 pitch 5120 (/4 1280) >[ 3156.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f260] >[ 3156.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f260] width 1280 pitch 5120 (/4 1280) >[ 3156.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733ec0] >[ 3156.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733ec0] width 1280 pitch 5120 (/4 1280) >[ 3156.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f260] >[ 3156.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f260] width 1280 pitch 5120 (/4 1280) >[ 3156.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733ec0] >[ 3156.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733ec0] width 1280 pitch 5120 (/4 1280) >[ 3289.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a5b0] >[ 3289.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a5b0] width 1280 pitch 5120 (/4 1280) >[ 3289.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2ea50] >[ 3289.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2ea50] width 1280 pitch 5120 (/4 1280) >[ 3312.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1f4b0] >[ 3312.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1f4b0] width 1280 pitch 5120 (/4 1280) >[ 3312.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3312.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3312.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1f4b0] >[ 3312.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1f4b0] width 1280 pitch 5120 (/4 1280) >[ 3313.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1f510] >[ 3313.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1f510] width 1280 pitch 5120 (/4 1280) >[ 3313.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1f4b0] >[ 3313.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1f4b0] width 1280 pitch 5120 (/4 1280) >[ 3313.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1f510] >[ 3313.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1f510] width 1280 pitch 5120 (/4 1280) >[ 3313.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3313.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3313.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1f4b0] >[ 3313.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1f4b0] width 1280 pitch 5120 (/4 1280) >[ 3313.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68500] >[ 3313.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68500] width 1280 pitch 5120 (/4 1280) >[ 3313.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68600] >[ 3313.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68600] width 1280 pitch 5120 (/4 1280) >[ 3313.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68500] >[ 3313.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68500] width 1280 pitch 5120 (/4 1280) >[ 3313.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68600] >[ 3313.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68600] width 1280 pitch 5120 (/4 1280) >[ 3313.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68500] >[ 3313.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68500] width 1280 pitch 5120 (/4 1280) >[ 3313.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68600] >[ 3313.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68600] width 1280 pitch 5120 (/4 1280) >[ 3313.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68500] >[ 3313.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68500] width 1280 pitch 5120 (/4 1280) >[ 3313.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68600] >[ 3314.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68600] width 1280 pitch 5120 (/4 1280) >[ 3314.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3314.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3314.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c68500] >[ 3314.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c68500] width 1280 pitch 5120 (/4 1280) >[ 3316.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fd230] >[ 3316.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fd230] width 1280 pitch 5120 (/4 1280) >[ 3316.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3316.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3316.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fd230] >[ 3316.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fd230] width 1280 pitch 5120 (/4 1280) >[ 3317.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fd290] >[ 3317.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fd290] width 1280 pitch 5120 (/4 1280) >[ 3317.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3317.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3318.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fd230] >[ 3318.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fd230] width 1280 pitch 5120 (/4 1280) >[ 3318.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3318.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3318.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fd230] >[ 3318.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fd230] width 1280 pitch 5120 (/4 1280) >[ 3318.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3318.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3319.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fd230] >[ 3319.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fd230] width 1280 pitch 5120 (/4 1280) >[ 3319.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3319.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3320.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46fd2a0] >[ 3320.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46fd2a0] width 1280 pitch 5120 (/4 1280) >[ 3320.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e860] >[ 3320.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e860] width 1280 pitch 5120 (/4 1280) >[ 3320.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4737480] >[ 3320.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4737480] width 1280 pitch 5120 (/4 1280) >[ 4006.286] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 4006.311] (II) RADEON(0): Using hsync ranges from config file >[ 4006.311] (II) RADEON(0): Using vrefresh ranges from config file >[ 4006.311] (II) RADEON(0): Printing DDC gathered Modelines: >[ 4006.311] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 4006.311] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 4006.311] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 4006.311] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 4006.311] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 4095.421] (II) RADEON(0): RADEONSaveScreen(2) >[ 4095.422] (II) RADEON(0): RADEONSaveScreen(0) >[ 5484.720] (II) RADEON(0): RADEONSaveScreen(1) >[ 5497.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d361d0] >[ 5497.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d361d0] width 1280 pitch 5120 (/4 1280) >[ 5507.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2951380] >[ 5507.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2951380] width 1280 pitch 5120 (/4 1280) >[ 5507.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a530] >[ 5507.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a530] width 1280 pitch 5120 (/4 1280) >[ 5513.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470d140] >[ 5513.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470d140] width 1280 pitch 5120 (/4 1280) >[ 5514.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d362a0] >[ 5514.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d362a0] width 1280 pitch 5120 (/4 1280) >[ 5514.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470d140] >[ 5514.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470d140] width 1280 pitch 5120 (/4 1280) >[ 5514.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d362a0] >[ 5514.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d362a0] width 1280 pitch 5120 (/4 1280) >[ 5514.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470d140] >[ 5514.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470d140] width 1280 pitch 5120 (/4 1280) >[ 5515.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d362a0] >[ 5515.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d362a0] width 1280 pitch 5120 (/4 1280) >[ 5515.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470d140] >[ 5515.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470d140] width 1280 pitch 5120 (/4 1280) >[ 5515.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d362a0] >[ 5515.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d362a0] width 1280 pitch 5120 (/4 1280) >[ 5515.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470d140] >[ 5515.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470d140] width 1280 pitch 5120 (/4 1280) >[ 5515.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d362a0] >[ 5516.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d362a0] width 1280 pitch 5120 (/4 1280) >[ 5516.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x470d140] >[ 5516.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x470d140] width 1280 pitch 5120 (/4 1280) >[ 5516.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d362a0] >[ 5516.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d362a0] width 1280 pitch 5120 (/4 1280) >[ 5516.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c57330] >[ 5517.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c57330] width 1280 pitch 5120 (/4 1280) >[ 5568.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5198860] >[ 5568.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5198860] width 1280 pitch 5120 (/4 1280) >[ 5606.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5198860] >[ 5606.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5198860] width 1280 pitch 5120 (/4 1280) >[ 5608.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519c3f0] >[ 5608.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519c3f0] width 1280 pitch 5120 (/4 1280) >[ 5636.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51c0380] >[ 5636.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51c0380] width 1280 pitch 5120 (/4 1280) >[ 5639.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519d9d0] >[ 5639.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519d9d0] width 1280 pitch 5120 (/4 1280) >[ 5671.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f4c0] >[ 5671.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f4c0] width 1280 pitch 5120 (/4 1280) >[ 5673.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51be050] >[ 5673.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51be050] width 1280 pitch 5120 (/4 1280) >[ 5697.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f4c0] >[ 5697.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f4c0] width 1280 pitch 5120 (/4 1280) >[ 5705.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3720c50] >[ 5705.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3720c50] width 1280 pitch 5120 (/4 1280) >[ 5713.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1e310] >[ 5713.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1e310] width 1280 pitch 5120 (/4 1280) >[ 5715.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b2510] >[ 5715.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b2510] width 1280 pitch 5120 (/4 1280) >[ 5732.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519e210] >[ 5732.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519e210] width 1280 pitch 5120 (/4 1280) >[ 5735.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d685f0] >[ 5735.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d685f0] width 1280 pitch 5120 (/4 1280) >[ 5761.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c72310] >[ 5761.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c72310] width 1280 pitch 5120 (/4 1280) >[ 5765.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c980] >[ 5765.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c980] width 1280 pitch 5120 (/4 1280) >[ 5795.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6f240] >[ 5795.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6f240] width 1280 pitch 5120 (/4 1280) >[ 5797.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b5d10] >[ 5797.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b5d10] width 1280 pitch 5120 (/4 1280) >[ 5841.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51c8b00] >[ 5841.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51c8b00] width 1280 pitch 5120 (/4 1280) >[ 5843.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b76b0] >[ 5844.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b76b0] width 1280 pitch 5120 (/4 1280) >[ 5889.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1e310] >[ 5889.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1e310] width 1280 pitch 5120 (/4 1280) >[ 5889.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c72310] >[ 5889.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c72310] width 1280 pitch 5120 (/4 1280) >[ 5889.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a3d0] >[ 5889.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a3d0] width 1280 pitch 5120 (/4 1280) >[ 5889.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1e310] >[ 5890.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1e310] width 1280 pitch 5120 (/4 1280) >[ 5890.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a3d0] >[ 5890.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a3d0] width 1280 pitch 5120 (/4 1280) >[ 5890.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1e310] >[ 5890.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1e310] width 1280 pitch 5120 (/4 1280) >[ 5890.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a3d0] >[ 5890.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a3d0] width 1280 pitch 5120 (/4 1280) >[ 5890.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1e310] >[ 5890.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1e310] width 1280 pitch 5120 (/4 1280) >[ 5893.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1e310] >[ 5893.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1e310] width 1280 pitch 5120 (/4 1280) >[ 5894.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c72310] >[ 5894.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c72310] width 1280 pitch 5120 (/4 1280) >[ 5894.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1e310] >[ 5894.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1e310] width 1280 pitch 5120 (/4 1280) >[ 5894.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519a3d0] >[ 5894.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519a3d0] width 1280 pitch 5120 (/4 1280) >[ 5894.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c72310] >[ 5894.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c72310] width 1280 pitch 5120 (/4 1280) >[ 6106.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372a950] >[ 6106.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372a950] width 1280 pitch 5120 (/4 1280) >[ 6120.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2951380] >[ 6120.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2951380] width 1280 pitch 5120 (/4 1280) >[ 6120.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2951380] >[ 6120.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2951380] width 1280 pitch 5120 (/4 1280) >[ 6120.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2951380] >[ 6120.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2951380] width 1280 pitch 5120 (/4 1280) >[ 6120.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371df60] >[ 6120.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371df60] width 1280 pitch 5120 (/4 1280) >[ 6120.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371df60] >[ 6120.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371df60] width 1280 pitch 5120 (/4 1280) >[ 6120.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371df60] >[ 6121.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371df60] width 1280 pitch 5120 (/4 1280) >[ 6121.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371df60] >[ 6121.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371df60] width 1280 pitch 5120 (/4 1280) >[ 6121.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371df60] >[ 6121.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371df60] width 1280 pitch 5120 (/4 1280) >[ 6121.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371df60] >[ 6121.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371df60] width 1280 pitch 5120 (/4 1280) >[ 6121.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2951380] >[ 6122.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2951380] width 1280 pitch 5120 (/4 1280) >[ 6122.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51a00d0] >[ 6122.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51a00d0] width 1280 pitch 5120 (/4 1280) >[ 6135.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c532d0] >[ 6135.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c532d0] width 1280 pitch 5120 (/4 1280) >[ 6135.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3518c30] >[ 6135.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3518c30] width 1280 pitch 5120 (/4 1280) >[ 6170.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371d8d0] >[ 6170.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371d8d0] width 1280 pitch 5120 (/4 1280) >[ 6170.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51bbe80] >[ 6170.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51bbe80] width 1280 pitch 5120 (/4 1280) >[ 6170.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51bbe80] >[ 6170.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51bbe80] width 1280 pitch 5120 (/4 1280) >[ 6170.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51bbe80] >[ 6170.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51bbe80] width 1280 pitch 5120 (/4 1280) >[ 6187.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d850] >[ 6187.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d850] width 1280 pitch 5120 (/4 1280) >[ 6187.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5199ae0] >[ 6187.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5199ae0] width 1280 pitch 5120 (/4 1280) >[ 6412.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b930] >[ 6412.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b930] width 1280 pitch 5120 (/4 1280) >[ 6412.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347eeb0] >[ 6412.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347eeb0] width 1280 pitch 5120 (/4 1280) >[ 6412.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b930] >[ 6412.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b930] width 1280 pitch 5120 (/4 1280) >[ 6412.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347eeb0] >[ 6412.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347eeb0] width 1280 pitch 5120 (/4 1280) >[ 6413.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b930] >[ 6413.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b930] width 1280 pitch 5120 (/4 1280) >[ 6413.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347eeb0] >[ 6413.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347eeb0] width 1280 pitch 5120 (/4 1280) >[ 6413.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b930] >[ 6413.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b930] width 1280 pitch 5120 (/4 1280) >[ 6413.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347eeb0] >[ 6414.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347eeb0] width 1280 pitch 5120 (/4 1280) >[ 6414.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b930] >[ 6414.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b930] width 1280 pitch 5120 (/4 1280) >[ 6414.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347eeb0] >[ 6414.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347eeb0] width 1280 pitch 5120 (/4 1280) >[ 6414.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b930] >[ 6415.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b930] width 1280 pitch 5120 (/4 1280) >[ 6415.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347eeb0] >[ 6415.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347eeb0] width 1280 pitch 5120 (/4 1280) >[ 6415.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b930] >[ 6415.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b930] width 1280 pitch 5120 (/4 1280) >[ 6415.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347eeb0] >[ 6415.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347eeb0] width 1280 pitch 5120 (/4 1280) >[ 6415.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5206970] >[ 6416.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5206970] width 1280 pitch 5120 (/4 1280) >[ 6416.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347eeb0] >[ 6416.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347eeb0] width 1280 pitch 5120 (/4 1280) >[ 6416.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51cc8d0] >[ 6416.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51cc8d0] width 1280 pitch 5120 (/4 1280) >[ 6416.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x519b930] >[ 6416.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x519b930] width 1280 pitch 5120 (/4 1280) >[ 6440.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d15d0] >[ 6440.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d15d0] width 1280 pitch 5120 (/4 1280) >[ 6440.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d15d0] >[ 6440.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d15d0] width 1280 pitch 5120 (/4 1280) >[ 6440.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c3400] >[ 6441.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c3400] width 1280 pitch 5120 (/4 1280) >[ 6441.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d15d0] >[ 6441.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d15d0] width 1280 pitch 5120 (/4 1280) >[ 6580.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d626a0] >[ 6580.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d626a0] width 1280 pitch 5120 (/4 1280) >[ 6580.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51c2650] >[ 6580.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51c2650] width 1280 pitch 5120 (/4 1280) >[ 6580.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51c2650] >[ 6580.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51c2650] width 1280 pitch 5120 (/4 1280) >[ 6580.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d626a0] >[ 6580.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d626a0] width 1280 pitch 5120 (/4 1280) >[ 6581.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d626a0] >[ 6581.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d626a0] width 1280 pitch 5120 (/4 1280) >[ 6581.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d651a0] >[ 6581.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d651a0] width 1280 pitch 5120 (/4 1280) >[ 6581.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d651a0] >[ 6581.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d651a0] width 1280 pitch 5120 (/4 1280) >[ 6581.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3720b20] >[ 6581.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3720b20] width 1280 pitch 5120 (/4 1280) >[ 6581.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d651a0] >[ 6581.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d651a0] width 1280 pitch 5120 (/4 1280) >[ 6581.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3720b20] >[ 6581.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3720b20] width 1280 pitch 5120 (/4 1280) >[ 6581.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d651a0] >[ 6581.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d651a0] width 1280 pitch 5120 (/4 1280) >[ 6581.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d621f0] >[ 6581.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d621f0] width 1280 pitch 5120 (/4 1280) >[ 6700.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8bbc0] >[ 6700.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8bbc0] width 1280 pitch 5120 (/4 1280) >[ 6700.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x517cba0] >[ 6700.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x517cba0] width 1280 pitch 5120 (/4 1280) >[ 6710.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62640] >[ 6710.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62640] width 1280 pitch 5120 (/4 1280) >[ 6710.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8bbc0] >[ 6710.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8bbc0] width 1280 pitch 5120 (/4 1280) >[ 6864.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f8b90] >[ 6864.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f8b90] width 1280 pitch 5120 (/4 1280) >[ 6883.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8e90] >[ 6883.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8e90] width 1280 pitch 5120 (/4 1280) >[ 6892.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fd400] >[ 6892.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fd400] width 1280 pitch 5120 (/4 1280) >[ 6923.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5e80] >[ 6923.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5e80] width 1280 pitch 5120 (/4 1280) >[ 6923.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34cb5d0] >[ 6923.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34cb5d0] width 1280 pitch 5120 (/4 1280) >[ 6923.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5e80] >[ 6924.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5e80] width 1280 pitch 5120 (/4 1280) >[ 6924.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34cb5d0] >[ 6924.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34cb5d0] width 1280 pitch 5120 (/4 1280) >[ 6924.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34cb5d0] >[ 6924.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34cb5d0] width 1280 pitch 5120 (/4 1280) >[ 6924.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5e80] >[ 6924.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5e80] width 1280 pitch 5120 (/4 1280) >[ 6924.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34cb5d0] >[ 6924.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34cb5d0] width 1280 pitch 5120 (/4 1280) >[ 6924.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5e80] >[ 6925.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5e80] width 1280 pitch 5120 (/4 1280) >[ 6925.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5e80] >[ 6925.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5e80] width 1280 pitch 5120 (/4 1280) >[ 6925.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d14a0] >[ 6925.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d14a0] width 1280 pitch 5120 (/4 1280) >[ 6925.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5e80] >[ 6925.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5e80] width 1280 pitch 5120 (/4 1280) >[ 6969.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6969.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6969.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f8210] >[ 6969.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f8210] width 1280 pitch 5120 (/4 1280) >[ 6969.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6969.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6969.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5e80] >[ 6969.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5e80] width 1280 pitch 5120 (/4 1280) >[ 6969.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6970.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6970.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d5e80] >[ 6970.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d5e80] width 1280 pitch 5120 (/4 1280) >[ 6970.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6970.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6970.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d14a0] >[ 6970.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d14a0] width 1280 pitch 5120 (/4 1280) >[ 6970.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6970.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6970.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d14a0] >[ 6970.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d14a0] width 1280 pitch 5120 (/4 1280) >[ 6971.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6971.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6971.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d14a0] >[ 6971.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d14a0] width 1280 pitch 5120 (/4 1280) >[ 6971.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6972.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6972.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6972.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6973.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccfdf0] >[ 6973.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccfdf0] width 1280 pitch 5120 (/4 1280) >[ 6973.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6973.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 6973.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce85f0] >[ 6973.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce85f0] width 1280 pitch 5120 (/4 1280) >[ 7080.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7080.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7080.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7080.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7080.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7080.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7080.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7080.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7080.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7080.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7080.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7080.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7080.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7080.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7082.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb0d0] >[ 7082.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb0d0] width 1280 pitch 5120 (/4 1280) >[ 7082.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb0d0] >[ 7082.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb0d0] width 1280 pitch 5120 (/4 1280) >[ 7082.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7082.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7082.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb0d0] >[ 7082.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb0d0] width 1280 pitch 5120 (/4 1280) >[ 7082.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7082.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7082.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7082.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7082.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7082.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7082.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7082.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7082.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7082.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7082.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb0d0] >[ 7083.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb0d0] width 1280 pitch 5120 (/4 1280) >[ 7083.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7083.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7083.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb0d0] >[ 7083.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb0d0] width 1280 pitch 5120 (/4 1280) >[ 7083.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7083.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7083.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb0d0] >[ 7083.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb0d0] width 1280 pitch 5120 (/4 1280) >[ 7083.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7083.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7083.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7083.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7083.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7083.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7157.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7157.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7157.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb0d0] >[ 7157.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb0d0] width 1280 pitch 5120 (/4 1280) >[ 7157.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7157.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7157.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ccb0d0] >[ 7157.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ccb0d0] width 1280 pitch 5120 (/4 1280) >[ 7157.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7158.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7163.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7164.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7164.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7164.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7164.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7164.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7164.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7164.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7164.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7164.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7165.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7165.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7165.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7165.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7165.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7165.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7165.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520e120] >[ 7165.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520e120] width 1280 pitch 5120 (/4 1280) >[ 7165.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5214b20] >[ 7165.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5214b20] width 1280 pitch 5120 (/4 1280) >[ 7448.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52306f0] >[ 7448.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52306f0] width 1280 pitch 5120 (/4 1280) >[ 7448.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52306f0] >[ 7448.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52306f0] width 1280 pitch 5120 (/4 1280) >[ 7664.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb150] >[ 7664.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb150] width 1280 pitch 5120 (/4 1280) >[ 7664.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb150] >[ 7664.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb150] width 1280 pitch 5120 (/4 1280) >[ 7757.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5252070] >[ 7757.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5252070] width 1280 pitch 5120 (/4 1280) >[ 7757.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521cb20] >[ 7757.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521cb20] width 1280 pitch 5120 (/4 1280) >[ 7757.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52306f0] >[ 7757.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52306f0] width 1280 pitch 5120 (/4 1280) >[ 7757.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524da80] >[ 7757.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524da80] width 1280 pitch 5120 (/4 1280) >[ 7757.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52306f0] >[ 7757.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52306f0] width 1280 pitch 5120 (/4 1280) >[ 7758.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524da80] >[ 7758.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524da80] width 1280 pitch 5120 (/4 1280) >[ 7758.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5252070] >[ 7758.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5252070] width 1280 pitch 5120 (/4 1280) >[ 7759.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52306f0] >[ 7759.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52306f0] width 1280 pitch 5120 (/4 1280) >[ 7760.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f6a0] >[ 7760.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f6a0] width 1280 pitch 5120 (/4 1280) >[ 7760.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521cb20] >[ 7760.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521cb20] width 1280 pitch 5120 (/4 1280) >[ 7760.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528f6a0] >[ 7760.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528f6a0] width 1280 pitch 5120 (/4 1280) >[ 7760.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5252070] >[ 7760.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5252070] width 1280 pitch 5120 (/4 1280) >[ 7760.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521cb20] >[ 7760.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521cb20] width 1280 pitch 5120 (/4 1280) >[ 7774.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5250e30] >[ 7774.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5250e30] width 1280 pitch 5120 (/4 1280) >[ 7774.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524da80] >[ 7774.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524da80] width 1280 pitch 5120 (/4 1280) >[ 7775.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5250e30] >[ 7775.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5250e30] width 1280 pitch 5120 (/4 1280) >[ 7775.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524da80] >[ 7775.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524da80] width 1280 pitch 5120 (/4 1280) >[ 7775.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5250e30] >[ 7775.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5250e30] width 1280 pitch 5120 (/4 1280) >[ 7775.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524da80] >[ 7775.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524da80] width 1280 pitch 5120 (/4 1280) >[ 7776.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5250e30] >[ 7776.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5250e30] width 1280 pitch 5120 (/4 1280) >[ 7776.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524da80] >[ 7776.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524da80] width 1280 pitch 5120 (/4 1280) >[ 7776.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5250e30] >[ 7776.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5250e30] width 1280 pitch 5120 (/4 1280) >[ 7776.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524da80] >[ 7776.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524da80] width 1280 pitch 5120 (/4 1280) >[ 7777.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5250e30] >[ 7778.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5250e30] width 1280 pitch 5120 (/4 1280) >[ 7778.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x524da80] >[ 7778.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x524da80] width 1280 pitch 5120 (/4 1280) >[ 7778.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fd460] >[ 7778.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fd460] width 1280 pitch 5120 (/4 1280) >[ 7797.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5250e30] >[ 7797.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5250e30] width 1280 pitch 5120 (/4 1280) >[ 7829.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc98d0] >[ 7829.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc98d0] width 1280 pitch 5120 (/4 1280) >[ 7829.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5281100] >[ 7829.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5281100] width 1280 pitch 5120 (/4 1280) >[ 7966.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a8f70] >[ 7966.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a8f70] width 1280 pitch 5120 (/4 1280) >[ 7966.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5286f70] >[ 7967.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5286f70] width 1280 pitch 5120 (/4 1280) >[ 7967.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341bd60] >[ 7967.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341bd60] width 1280 pitch 5120 (/4 1280) >[ 8103.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5259f60] >[ 8103.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5259f60] width 1280 pitch 5120 (/4 1280) >[ 8104.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5216340] >[ 8104.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5216340] width 1280 pitch 5120 (/4 1280) >[ 8104.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5259f60] >[ 8104.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5259f60] width 1280 pitch 5120 (/4 1280) >[ 8104.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5216340] >[ 8104.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5216340] width 1280 pitch 5120 (/4 1280) >[ 8104.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5259f60] >[ 8104.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5259f60] width 1280 pitch 5120 (/4 1280) >[ 8104.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5216340] >[ 8105.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5216340] width 1280 pitch 5120 (/4 1280) >[ 8105.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5259f60] >[ 8105.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5259f60] width 1280 pitch 5120 (/4 1280) >[ 8105.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5216340] >[ 8105.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5216340] width 1280 pitch 5120 (/4 1280) >[ 8105.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5216340] >[ 8105.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5216340] width 1280 pitch 5120 (/4 1280) >[ 8105.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x527fa20] >[ 8106.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x527fa20] width 1280 pitch 5120 (/4 1280) >[ 8125.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5242a10] >[ 8125.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5242a10] width 1280 pitch 5120 (/4 1280) >[ 8126.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x525da80] >[ 8126.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x525da80] width 1280 pitch 5120 (/4 1280) >[ 8126.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a6550] >[ 8126.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a6550] width 1280 pitch 5120 (/4 1280) >[ 8182.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x529c790] >[ 8182.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x529c790] width 1280 pitch 5120 (/4 1280) >[ 8183.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a0910] >[ 8183.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a0910] width 1280 pitch 5120 (/4 1280) >[ 8185.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e8620] >[ 8185.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e8620] width 1280 pitch 5120 (/4 1280) >[ 8185.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e8620] >[ 8185.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e8620] width 1280 pitch 5120 (/4 1280) >[ 8321.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x529a300] >[ 8321.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x529a300] width 1280 pitch 5120 (/4 1280) >[ 8321.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5299010] >[ 8321.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5299010] width 1280 pitch 5120 (/4 1280) >[ 8322.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52956a0] >[ 8322.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52956a0] width 1280 pitch 5120 (/4 1280) >[ 8322.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521e520] >[ 8322.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521e520] width 1280 pitch 5120 (/4 1280) >[ 8323.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5299010] >[ 8323.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5299010] width 1280 pitch 5120 (/4 1280) >[ 8323.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5254530] >[ 8323.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5254530] width 1280 pitch 5120 (/4 1280) >[ 8323.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5299010] >[ 8323.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5299010] width 1280 pitch 5120 (/4 1280) >[ 8324.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x529a300] >[ 8324.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x529a300] width 1280 pitch 5120 (/4 1280) >[ 8324.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52a5850] >[ 8324.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52a5850] width 1280 pitch 5120 (/4 1280) >[ 8324.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x521e520] >[ 8324.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x521e520] width 1280 pitch 5120 (/4 1280) >[ 8331.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5281da0] >[ 8331.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5281da0] width 1280 pitch 5120 (/4 1280) >[ 8621.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5281da0] >[ 8621.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5281da0] width 1280 pitch 5120 (/4 1280) >[ 8621.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5281da0] >[ 8621.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5281da0] width 1280 pitch 5120 (/4 1280) >[ 8621.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5262fe0] >[ 8622.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5262fe0] width 1280 pitch 5120 (/4 1280) >[ 8622.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5281da0] >[ 8622.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5281da0] width 1280 pitch 5120 (/4 1280) >[ 8622.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5297c50] >[ 8622.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5297c50] width 1280 pitch 5120 (/4 1280) >[ 8622.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5262fe0] >[ 8623.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5262fe0] width 1280 pitch 5120 (/4 1280) >[ 8623.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5297c50] >[ 8623.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5297c50] width 1280 pitch 5120 (/4 1280) >[ 8623.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5262fe0] >[ 8623.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5262fe0] width 1280 pitch 5120 (/4 1280) >[ 8623.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5297c50] >[ 8623.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5297c50] width 1280 pitch 5120 (/4 1280) >[ 8624.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5262fe0] >[ 8624.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5262fe0] width 1280 pitch 5120 (/4 1280) >[ 8624.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5262fe0] >[ 8624.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5262fe0] width 1280 pitch 5120 (/4 1280) >[ 8624.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5264c70] >[ 8624.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5264c70] width 1280 pitch 5120 (/4 1280) >[ 9611.510] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 9611.545] (II) RADEON(0): Using hsync ranges from config file >[ 9611.545] (II) RADEON(0): Using vrefresh ranges from config file >[ 9611.545] (II) RADEON(0): Printing DDC gathered Modelines: >[ 9611.545] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 9611.545] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 9611.545] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 9611.545] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 9611.545] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 9701.386] (II) RADEON(0): RADEONSaveScreen(2) >[ 9701.397] (II) RADEON(0): RADEONSaveScreen(0) >[ 9790.160] (II) RADEON(0): RADEONSaveScreen(1) >[ 9981.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e200] >[ 9981.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e200] width 1280 pitch 5120 (/4 1280) >[ 9983.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6f830] >[ 9983.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6f830] width 1280 pitch 5120 (/4 1280) >[ 9983.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e200] >[ 9983.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e200] width 1280 pitch 5120 (/4 1280) >[ 10006.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c6d970] >[ 10006.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c6d970] width 1280 pitch 5120 (/4 1280) >[ 10007.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10007.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10008.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e200] >[ 10008.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e200] width 1280 pitch 5120 (/4 1280) >[ 10008.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10008.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10008.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e200] >[ 10008.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e200] width 1280 pitch 5120 (/4 1280) >[ 10008.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6f830] >[ 10009.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6f830] width 1280 pitch 5120 (/4 1280) >[ 10010.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c6d970] >[ 10010.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c6d970] width 1280 pitch 5120 (/4 1280) >[ 10010.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10010.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10010.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c5d2f0] >[ 10011.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c5d2f0] width 1280 pitch 5120 (/4 1280) >[ 10011.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10011.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10026.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52949e0] >[ 10026.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52949e0] width 1280 pitch 5120 (/4 1280) >[ 10026.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10026.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10027.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1880] >[ 10027.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1880] width 1280 pitch 5120 (/4 1280) >[ 10027.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10027.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10027.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1880] >[ 10027.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1880] width 1280 pitch 5120 (/4 1280) >[ 10027.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10027.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10028.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10028.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10028.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e200] >[ 10028.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e200] width 1280 pitch 5120 (/4 1280) >[ 10028.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10028.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10028.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e200] >[ 10028.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e200] width 1280 pitch 5120 (/4 1280) >[ 10028.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10028.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10029.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e200] >[ 10029.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e200] width 1280 pitch 5120 (/4 1280) >[ 10029.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10029.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10030.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e200] >[ 10030.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e200] width 1280 pitch 5120 (/4 1280) >[ 10030.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10030.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10030.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10030.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10030.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52949e0] >[ 10031.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52949e0] width 1280 pitch 5120 (/4 1280) >[ 10031.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10031.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10031.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52949e0] >[ 10031.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52949e0] width 1280 pitch 5120 (/4 1280) >[ 10031.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10031.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10031.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52949e0] >[ 10032.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52949e0] width 1280 pitch 5120 (/4 1280) >[ 10033.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10033.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10033.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10033.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10034.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1880] >[ 10034.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1880] width 1280 pitch 5120 (/4 1280) >[ 10034.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10034.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10035.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1880] >[ 10035.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1880] width 1280 pitch 5120 (/4 1280) >[ 10036.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1880] >[ 10036.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1880] width 1280 pitch 5120 (/4 1280) >[ 10037.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1880] >[ 10037.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1880] width 1280 pitch 5120 (/4 1280) >[ 10037.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10037.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10037.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1880] >[ 10037.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1880] width 1280 pitch 5120 (/4 1280) >[ 10037.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52641e0] >[ 10037.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52641e0] width 1280 pitch 5120 (/4 1280) >[ 10037.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c585e0] >[ 10038.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c585e0] width 1280 pitch 5120 (/4 1280) >[ 10054.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b16f0] >[ 10054.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b16f0] width 1280 pitch 5120 (/4 1280) >[ 10054.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x526e750] >[ 10054.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x526e750] width 1280 pitch 5120 (/4 1280) >[ 10095.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51edbd0] >[ 10095.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51edbd0] width 1280 pitch 5120 (/4 1280) >[ 10095.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51edbd0] >[ 10095.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51edbd0] width 1280 pitch 5120 (/4 1280) >[ 10259.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51eb7a0] >[ 10259.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51eb7a0] width 1280 pitch 5120 (/4 1280) >[ 10259.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51eb7a0] >[ 10259.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51eb7a0] width 1280 pitch 5120 (/4 1280) >[ 10259.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5269000] >[ 10259.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5269000] width 1280 pitch 5120 (/4 1280) >[ 10259.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5269000] >[ 10259.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5269000] width 1280 pitch 5120 (/4 1280) >[ 10491.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x534ef00] >[ 10491.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x534ef00] width 1280 pitch 5120 (/4 1280) >[ 10491.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x534d8d0] >[ 10491.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x534d8d0] width 1280 pitch 5120 (/4 1280) >[ 10838.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52e7b40] >[ 10838.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52e7b40] width 1280 pitch 5120 (/4 1280) >[ 10838.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52e81b0] >[ 10838.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52e81b0] width 1280 pitch 5120 (/4 1280) >[ 11008.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5315e80] >[ 11008.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5315e80] width 1280 pitch 5120 (/4 1280) >[ 11009.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5342740] >[ 11009.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5342740] width 1280 pitch 5120 (/4 1280) >[ 11009.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5315e80] >[ 11009.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5315e80] width 1280 pitch 5120 (/4 1280) >[ 11009.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5342740] >[ 11009.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5342740] width 1280 pitch 5120 (/4 1280) >[ 11009.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53108e0] >[ 11009.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53108e0] width 1280 pitch 5120 (/4 1280) >[ 11010.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5310810] >[ 11010.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5310810] width 1280 pitch 5120 (/4 1280) >[ 11010.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53255f0] >[ 11011.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53255f0] width 1280 pitch 5120 (/4 1280) >[ 11011.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c0090] >[ 11011.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c0090] width 1280 pitch 5120 (/4 1280) >[ 11011.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5310810] >[ 11011.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5310810] width 1280 pitch 5120 (/4 1280) >[ 11012.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53108e0] >[ 11012.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53108e0] width 1280 pitch 5120 (/4 1280) >[ 11012.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5310810] >[ 11012.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5310810] width 1280 pitch 5120 (/4 1280) >[ 11013.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53108e0] >[ 11013.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53108e0] width 1280 pitch 5120 (/4 1280) >[ 11014.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53255f0] >[ 11014.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53255f0] width 1280 pitch 5120 (/4 1280) >[ 11014.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5315e80] >[ 11014.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5315e80] width 1280 pitch 5120 (/4 1280) >[ 11015.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53108e0] >[ 11015.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53108e0] width 1280 pitch 5120 (/4 1280) >[ 11015.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5315e80] >[ 11015.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5315e80] width 1280 pitch 5120 (/4 1280) >[ 11015.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53108e0] >[ 11015.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53108e0] width 1280 pitch 5120 (/4 1280) >[ 11016.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5315e80] >[ 11016.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5315e80] width 1280 pitch 5120 (/4 1280) >[ 11016.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53108e0] >[ 11016.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53108e0] width 1280 pitch 5120 (/4 1280) >[ 11016.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5315e80] >[ 11016.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5315e80] width 1280 pitch 5120 (/4 1280) >[ 11017.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bf920] >[ 11017.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bf920] width 1280 pitch 5120 (/4 1280) >[ 11017.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x530c170] >[ 11017.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x530c170] width 1280 pitch 5120 (/4 1280) >[ 11017.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5324da0] >[ 11017.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5324da0] width 1280 pitch 5120 (/4 1280) >[ 11037.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11037.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11037.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 11037.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 11037.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11037.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11037.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 11038.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 11038.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53108e0] >[ 11038.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53108e0] width 1280 pitch 5120 (/4 1280) >[ 11038.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 11038.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 11038.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53108e0] >[ 11038.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53108e0] width 1280 pitch 5120 (/4 1280) >[ 11038.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ac40] >[ 11038.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ac40] width 1280 pitch 5120 (/4 1280) >[ 11039.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5315e80] >[ 11039.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5315e80] width 1280 pitch 5120 (/4 1280) >[ 11039.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x530c170] >[ 11039.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x530c170] width 1280 pitch 5120 (/4 1280) >[ 11108.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53201b0] >[ 11108.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53201b0] width 1280 pitch 5120 (/4 1280) >[ 11108.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 11108.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 11108.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53201b0] >[ 11108.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53201b0] width 1280 pitch 5120 (/4 1280) >[ 11108.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 11108.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 11108.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53201b0] >[ 11108.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53201b0] width 1280 pitch 5120 (/4 1280) >[ 11108.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 11109.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 11109.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53201b0] >[ 11109.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53201b0] width 1280 pitch 5120 (/4 1280) >[ 11109.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 11109.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 11109.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53201b0] >[ 11109.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53201b0] width 1280 pitch 5120 (/4 1280) >[ 11110.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc1220] >[ 11110.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc1220] width 1280 pitch 5120 (/4 1280) >[ 11110.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5291d50] >[ 11110.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5291d50] width 1280 pitch 5120 (/4 1280) >[ 11114.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5319cc0] >[ 11114.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5319cc0] width 1280 pitch 5120 (/4 1280) >[ 11114.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35057f0] >[ 11114.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35057f0] width 1280 pitch 5120 (/4 1280) >[ 11115.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5319cc0] >[ 11115.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5319cc0] width 1280 pitch 5120 (/4 1280) >[ 11115.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35057f0] >[ 11115.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35057f0] width 1280 pitch 5120 (/4 1280) >[ 11115.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5319cc0] >[ 11115.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5319cc0] width 1280 pitch 5120 (/4 1280) >[ 11115.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35057f0] >[ 11115.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35057f0] width 1280 pitch 5120 (/4 1280) >[ 11115.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5319cc0] >[ 11115.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5319cc0] width 1280 pitch 5120 (/4 1280) >[ 11115.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35057f0] >[ 11115.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35057f0] width 1280 pitch 5120 (/4 1280) >[ 11116.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5319cc0] >[ 11116.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5319cc0] width 1280 pitch 5120 (/4 1280) >[ 11118.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11118.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11118.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338d1c0] >[ 11119.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338d1c0] width 1280 pitch 5120 (/4 1280) >[ 11124.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11124.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11124.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11124.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11124.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11124.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11124.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9df50] >[ 11125.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9df50] width 1280 pitch 5120 (/4 1280) >[ 11125.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11125.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11125.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9df50] >[ 11125.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9df50] width 1280 pitch 5120 (/4 1280) >[ 11125.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11125.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11125.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9df50] >[ 11125.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9df50] width 1280 pitch 5120 (/4 1280) >[ 11125.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11125.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11125.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11126.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11126.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11126.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11126.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11126.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11126.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11126.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11126.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b370] >[ 11127.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b370] width 1280 pitch 5120 (/4 1280) >[ 11139.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11140.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11142.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11142.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11142.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1720] >[ 11142.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1720] width 1280 pitch 5120 (/4 1280) >[ 11142.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11142.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11143.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1720] >[ 11143.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1720] width 1280 pitch 5120 (/4 1280) >[ 11143.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11143.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11143.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1720] >[ 11143.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1720] width 1280 pitch 5120 (/4 1280) >[ 11143.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11143.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11143.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1720] >[ 11143.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1720] width 1280 pitch 5120 (/4 1280) >[ 11143.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11144.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11144.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1720] >[ 11144.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1720] width 1280 pitch 5120 (/4 1280) >[ 11144.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11144.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11144.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1720] >[ 11144.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1720] width 1280 pitch 5120 (/4 1280) >[ 11146.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11146.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11146.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52948b0] >[ 11146.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52948b0] width 1280 pitch 5120 (/4 1280) >[ 11146.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3712770] >[ 11146.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3712770] width 1280 pitch 5120 (/4 1280) >[ 11146.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52948b0] >[ 11146.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52948b0] width 1280 pitch 5120 (/4 1280) >[ 11407.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54eb180] >[ 11407.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54eb180] width 1280 pitch 5120 (/4 1280) >[ 11407.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8010] >[ 11407.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8010] width 1280 pitch 5120 (/4 1280) >[ 11408.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5265020] >[ 11408.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5265020] width 1280 pitch 5120 (/4 1280) >[ 11408.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8010] >[ 11408.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8010] width 1280 pitch 5120 (/4 1280) >[ 11408.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5265020] >[ 11409.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5265020] width 1280 pitch 5120 (/4 1280) >[ 11409.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8010] >[ 11409.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8010] width 1280 pitch 5120 (/4 1280) >[ 11409.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5265020] >[ 11409.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5265020] width 1280 pitch 5120 (/4 1280) >[ 11409.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8010] >[ 11409.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8010] width 1280 pitch 5120 (/4 1280) >[ 11409.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5265020] >[ 11409.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5265020] width 1280 pitch 5120 (/4 1280) >[ 11409.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8010] >[ 11410.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8010] width 1280 pitch 5120 (/4 1280) >[ 11410.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5265020] >[ 11410.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5265020] width 1280 pitch 5120 (/4 1280) >[ 11410.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557c290] >[ 11410.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557c290] width 1280 pitch 5120 (/4 1280) >[ 11410.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5265020] >[ 11410.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5265020] width 1280 pitch 5120 (/4 1280) >[ 11564.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557c290] >[ 11564.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557c290] width 1280 pitch 5120 (/4 1280) >[ 11564.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557c290] >[ 11564.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557c290] width 1280 pitch 5120 (/4 1280) >[ 11564.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54eb180] >[ 11564.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54eb180] width 1280 pitch 5120 (/4 1280) >[ 11565.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557c290] >[ 11565.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557c290] width 1280 pitch 5120 (/4 1280) >[ 11565.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54eb180] >[ 11565.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54eb180] width 1280 pitch 5120 (/4 1280) >[ 11565.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557c290] >[ 11565.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557c290] width 1280 pitch 5120 (/4 1280) >[ 11565.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557c290] >[ 11566.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557c290] width 1280 pitch 5120 (/4 1280) >[ 11566.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e9840] >[ 11566.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e9840] width 1280 pitch 5120 (/4 1280) >[ 11566.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5160] >[ 11566.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5160] width 1280 pitch 5120 (/4 1280) >[ 11566.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5160] >[ 11566.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5160] width 1280 pitch 5120 (/4 1280) >[ 11567.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338d060] >[ 11567.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338d060] width 1280 pitch 5120 (/4 1280) >[ 11567.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5160] >[ 11567.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5160] width 1280 pitch 5120 (/4 1280) >[ 11584.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f93d0] >[ 11584.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f93d0] width 1280 pitch 5120 (/4 1280) >[ 11584.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e9840] >[ 11584.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e9840] width 1280 pitch 5120 (/4 1280) >[ 11584.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55310f0] >[ 11584.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55310f0] width 1280 pitch 5120 (/4 1280) >[ 11584.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55310f0] >[ 11584.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55310f0] width 1280 pitch 5120 (/4 1280) >[ 12022.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55278f0] >[ 12022.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55278f0] width 1280 pitch 5120 (/4 1280) >[ 12022.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543870] >[ 12022.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543870] width 1280 pitch 5120 (/4 1280) >[ 12022.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543990] >[ 12022.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543990] width 1280 pitch 5120 (/4 1280) >[ 12022.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554aa70] >[ 12022.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554aa70] width 1280 pitch 5120 (/4 1280) >[ 12023.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543990] >[ 12023.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543990] width 1280 pitch 5120 (/4 1280) >[ 12023.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554aa70] >[ 12023.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554aa70] width 1280 pitch 5120 (/4 1280) >[ 12023.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543990] >[ 12023.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543990] width 1280 pitch 5120 (/4 1280) >[ 12024.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55278f0] >[ 12024.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55278f0] width 1280 pitch 5120 (/4 1280) >[ 12024.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5539590] >[ 12024.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5539590] width 1280 pitch 5120 (/4 1280) >[ 12024.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b000] >[ 12024.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b000] width 1280 pitch 5120 (/4 1280) >[ 12308.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5542fe0] >[ 12308.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5542fe0] width 1280 pitch 5120 (/4 1280) >[ 12308.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553e320] >[ 12308.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553e320] width 1280 pitch 5120 (/4 1280) >[ 12308.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55376d0] >[ 12308.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55376d0] width 1280 pitch 5120 (/4 1280) >[ 12308.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d250] >[ 12308.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d250] width 1280 pitch 5120 (/4 1280) >[ 12308.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55376d0] >[ 12308.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55376d0] width 1280 pitch 5120 (/4 1280) >[ 12308.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8fc0] >[ 12308.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8fc0] width 1280 pitch 5120 (/4 1280) >[ 12308.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d250] >[ 12308.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d250] width 1280 pitch 5120 (/4 1280) >[ 12308.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8fc0] >[ 12308.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8fc0] width 1280 pitch 5120 (/4 1280) >[ 12308.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d250] >[ 12308.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d250] width 1280 pitch 5120 (/4 1280) >[ 12308.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8fc0] >[ 12308.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8fc0] width 1280 pitch 5120 (/4 1280) >[ 12308.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d250] >[ 12308.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d250] width 1280 pitch 5120 (/4 1280) >[ 12309.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f21a0] >[ 12309.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f21a0] width 1280 pitch 5120 (/4 1280) >[ 12309.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d250] >[ 12309.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d250] width 1280 pitch 5120 (/4 1280) >[ 12310.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561e60] >[ 12310.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561e60] width 1280 pitch 5120 (/4 1280) >[ 12310.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f21a0] >[ 12310.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f21a0] width 1280 pitch 5120 (/4 1280) >[ 12310.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561e60] >[ 12310.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561e60] width 1280 pitch 5120 (/4 1280) >[ 12310.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543170] >[ 12310.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543170] width 1280 pitch 5120 (/4 1280) >[ 12310.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f21a0] >[ 12310.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f21a0] width 1280 pitch 5120 (/4 1280) >[ 12310.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5501250] >[ 12310.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5501250] width 1280 pitch 5120 (/4 1280) >[ 12310.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f21a0] >[ 12310.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f21a0] width 1280 pitch 5120 (/4 1280) >[ 12310.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5501250] >[ 12310.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5501250] width 1280 pitch 5120 (/4 1280) >[ 12310.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f21a0] >[ 12310.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f21a0] width 1280 pitch 5120 (/4 1280) >[ 12326.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e8010] >[ 12326.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e8010] width 1280 pitch 5120 (/4 1280) >[ 12326.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f21a0] >[ 12326.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f21a0] width 1280 pitch 5120 (/4 1280) >[ 12336.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd1720] >[ 12336.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd1720] width 1280 pitch 5120 (/4 1280) >[ 12336.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552e7b0] >[ 12336.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552e7b0] width 1280 pitch 5120 (/4 1280) >[ 12483.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55372f0] >[ 12483.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55372f0] width 1280 pitch 5120 (/4 1280) >[ 12490.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55278f0] >[ 12490.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55278f0] width 1280 pitch 5120 (/4 1280) >[ 12593.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382760] >[ 12593.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382760] width 1280 pitch 5120 (/4 1280) >[ 12593.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5535210] >[ 12593.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5535210] width 1280 pitch 5120 (/4 1280) >[ 12593.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5563cd0] >[ 12593.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5563cd0] width 1280 pitch 5120 (/4 1280) >[ 12593.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5535210] >[ 12593.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5535210] width 1280 pitch 5120 (/4 1280) >[ 12593.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b95c0] >[ 12593.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b95c0] width 1280 pitch 5120 (/4 1280) >[ 12614.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9b010] >[ 12614.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9b010] width 1280 pitch 5120 (/4 1280) >[ 12614.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536e200] >[ 12614.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536e200] width 1280 pitch 5120 (/4 1280) >[ 12614.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53847f0] >[ 12614.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53847f0] width 1280 pitch 5120 (/4 1280) >[ 12614.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536e200] >[ 12614.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536e200] width 1280 pitch 5120 (/4 1280) >[ 12614.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53847f0] >[ 12614.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53847f0] width 1280 pitch 5120 (/4 1280) >[ 12614.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5356b10] >[ 12614.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5356b10] width 1280 pitch 5120 (/4 1280) >[ 12614.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53847f0] >[ 12615.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53847f0] width 1280 pitch 5120 (/4 1280) >[ 12615.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5356b10] >[ 12615.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5356b10] width 1280 pitch 5120 (/4 1280) >[ 12615.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53847f0] >[ 12615.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53847f0] width 1280 pitch 5120 (/4 1280) >[ 12615.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5356b10] >[ 12615.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5356b10] width 1280 pitch 5120 (/4 1280) >[ 12672.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f9700] >[ 12672.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f9700] width 1280 pitch 5120 (/4 1280) >[ 12672.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4375d90] >[ 12672.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4375d90] width 1280 pitch 5120 (/4 1280) >[ 12672.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371df0] >[ 12672.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371df0] width 1280 pitch 5120 (/4 1280) >[ 12673.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4375d90] >[ 12673.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4375d90] width 1280 pitch 5120 (/4 1280) >[ 12673.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371df0] >[ 12673.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371df0] width 1280 pitch 5120 (/4 1280) >[ 12673.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4375d90] >[ 12673.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4375d90] width 1280 pitch 5120 (/4 1280) >[ 12674.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371df0] >[ 12674.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371df0] width 1280 pitch 5120 (/4 1280) >[ 12674.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4375d90] >[ 12674.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4375d90] width 1280 pitch 5120 (/4 1280) >[ 12675.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371df0] >[ 12675.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371df0] width 1280 pitch 5120 (/4 1280) >[ 12675.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4375d90] >[ 12675.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4375d90] width 1280 pitch 5120 (/4 1280) >[ 12675.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371760] >[ 12676.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371760] width 1280 pitch 5120 (/4 1280) >[ 12676.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371df0] >[ 12676.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371df0] width 1280 pitch 5120 (/4 1280) >[ 12677.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4375d90] >[ 12677.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4375d90] width 1280 pitch 5120 (/4 1280) >[ 12677.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371df0] >[ 12677.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371df0] width 1280 pitch 5120 (/4 1280) >[ 12685.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5201d60] >[ 12685.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5201d60] width 1280 pitch 5120 (/4 1280) >[ 12685.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dcc60] >[ 12685.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dcc60] width 1280 pitch 5120 (/4 1280) >[ 12685.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5201d60] >[ 12685.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5201d60] width 1280 pitch 5120 (/4 1280) >[ 12685.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dcc60] >[ 12686.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dcc60] width 1280 pitch 5120 (/4 1280) >[ 12686.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5201d60] >[ 12686.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5201d60] width 1280 pitch 5120 (/4 1280) >[ 12687.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dcc60] >[ 12687.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dcc60] width 1280 pitch 5120 (/4 1280) >[ 12687.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c760] >[ 12687.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c760] width 1280 pitch 5120 (/4 1280) >[ 12687.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dcc60] >[ 12687.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dcc60] width 1280 pitch 5120 (/4 1280) >[ 12688.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c760] >[ 12688.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c760] width 1280 pitch 5120 (/4 1280) >[ 12688.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dcc60] >[ 12688.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dcc60] width 1280 pitch 5120 (/4 1280) >[ 12688.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c760] >[ 12688.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c760] width 1280 pitch 5120 (/4 1280) >[ 12688.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dcc60] >[ 12688.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dcc60] width 1280 pitch 5120 (/4 1280) >[ 12688.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c760] >[ 12689.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c760] width 1280 pitch 5120 (/4 1280) >[ 12689.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371760] >[ 12689.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371760] width 1280 pitch 5120 (/4 1280) >[ 12689.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5371df0] >[ 12689.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5371df0] width 1280 pitch 5120 (/4 1280) >[ 12697.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c335e0] >[ 12697.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c335e0] width 1280 pitch 5120 (/4 1280) >[ 12697.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dcc60] >[ 12697.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dcc60] width 1280 pitch 5120 (/4 1280) >[ 12697.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4c40] >[ 12697.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4c40] width 1280 pitch 5120 (/4 1280) >[ 12697.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c4c40] >[ 12697.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c4c40] width 1280 pitch 5120 (/4 1280) >[ 12847.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1900] >[ 12847.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1900] width 1280 pitch 5120 (/4 1280) >[ 12848.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12848.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12848.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1e50] >[ 12848.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1e50] width 1280 pitch 5120 (/4 1280) >[ 12848.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1900] >[ 12848.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1900] width 1280 pitch 5120 (/4 1280) >[ 12848.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12849.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12849.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1900] >[ 12849.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1900] width 1280 pitch 5120 (/4 1280) >[ 12849.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12849.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12849.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1900] >[ 12849.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1900] width 1280 pitch 5120 (/4 1280) >[ 12849.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12849.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12850.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1900] >[ 12850.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1900] width 1280 pitch 5120 (/4 1280) >[ 12850.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12850.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12893.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12893.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12893.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1900] >[ 12894.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1900] width 1280 pitch 5120 (/4 1280) >[ 12894.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12894.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12894.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1900] >[ 12894.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1900] width 1280 pitch 5120 (/4 1280) >[ 12894.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12894.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12894.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12894.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12894.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5562a60] >[ 12894.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5562a60] width 1280 pitch 5120 (/4 1280) >[ 12894.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12894.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12894.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12894.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12894.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12894.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12894.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12894.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12894.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12895.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12898.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12898.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12899.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1e50] >[ 12899.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1e50] width 1280 pitch 5120 (/4 1280) >[ 12899.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12899.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12899.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1e50] >[ 12899.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1e50] width 1280 pitch 5120 (/4 1280) >[ 12900.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12900.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12900.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12900.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12900.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12900.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12900.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12901.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12901.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12901.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12901.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12901.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12901.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12901.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12901.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12902.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12902.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12902.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12904.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12904.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12904.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12904.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12905.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12905.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12905.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12905.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12906.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12906.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12906.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12906.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12907.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f22c0] >[ 12907.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f22c0] width 1280 pitch 5120 (/4 1280) >[ 12907.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1620] >[ 12907.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1620] width 1280 pitch 5120 (/4 1280) >[ 12907.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc6f0] >[ 12907.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc6f0] width 1280 pitch 5120 (/4 1280) >[ 12945.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1c40] >[ 12945.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1c40] width 1280 pitch 5120 (/4 1280) >[ 12945.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c5d0] >[ 12945.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c5d0] width 1280 pitch 5120 (/4 1280) >[ 12945.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c5d0] >[ 12945.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c5d0] width 1280 pitch 5120 (/4 1280) >[ 12946.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f7a20] >[ 12946.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f7a20] width 1280 pitch 5120 (/4 1280) >[ 12946.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c263f0] >[ 12946.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c263f0] width 1280 pitch 5120 (/4 1280) >[ 12947.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1c40] >[ 12947.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1c40] width 1280 pitch 5120 (/4 1280) >[ 12947.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c263f0] >[ 12947.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c263f0] width 1280 pitch 5120 (/4 1280) >[ 12947.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d070] >[ 12947.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d070] width 1280 pitch 5120 (/4 1280) >[ 12947.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c263f0] >[ 12947.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c263f0] width 1280 pitch 5120 (/4 1280) >[ 12947.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d070] >[ 12947.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d070] width 1280 pitch 5120 (/4 1280) >[ 12947.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f7a20] >[ 12948.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f7a20] width 1280 pitch 5120 (/4 1280) >[ 12948.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537dd50] >[ 12948.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537dd50] width 1280 pitch 5120 (/4 1280) >[ 12949.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f1c40] >[ 12949.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f1c40] width 1280 pitch 5120 (/4 1280) >[ 12949.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55b4c60] >[ 12949.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55b4c60] width 1280 pitch 5120 (/4 1280) >[ 12949.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d070] >[ 12949.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d070] width 1280 pitch 5120 (/4 1280) >[ 12950.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f7a20] >[ 12950.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f7a20] width 1280 pitch 5120 (/4 1280) >[ 12950.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f9700] >[ 12950.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f9700] width 1280 pitch 5120 (/4 1280) >[ 12950.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f9700] >[ 12951.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f9700] width 1280 pitch 5120 (/4 1280) >[ 12951.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d070] >[ 12951.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d070] width 1280 pitch 5120 (/4 1280) >[ 13012.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55aca10] >[ 13012.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55aca10] width 1280 pitch 5120 (/4 1280) >[ 13012.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e7c50] >[ 13012.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e7c50] width 1280 pitch 5120 (/4 1280) >[ 13012.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f7810] >[ 13012.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f7810] width 1280 pitch 5120 (/4 1280) >[ 13012.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e7c50] >[ 13012.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e7c50] width 1280 pitch 5120 (/4 1280) >[ 13012.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537eda0] >[ 13012.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537eda0] width 1280 pitch 5120 (/4 1280) >[ 13013.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55aca10] >[ 13013.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55aca10] width 1280 pitch 5120 (/4 1280) >[ 13013.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c4a0] >[ 13013.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c4a0] width 1280 pitch 5120 (/4 1280) >[ 13013.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55aca10] >[ 13014.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55aca10] width 1280 pitch 5120 (/4 1280) >[ 13014.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ef110] >[ 13014.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ef110] width 1280 pitch 5120 (/4 1280) >[ 13014.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537eda0] >[ 13014.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537eda0] width 1280 pitch 5120 (/4 1280) >[ 13014.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55c2e90] >[ 13014.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55c2e90] width 1280 pitch 5120 (/4 1280) >[ 13014.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d6b10] >[ 13014.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d6b10] width 1280 pitch 5120 (/4 1280) >[ 13014.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55aca10] >[ 13015.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55aca10] width 1280 pitch 5120 (/4 1280) >[ 13015.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c4a0] >[ 13015.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c4a0] width 1280 pitch 5120 (/4 1280) >[ 13015.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537eda0] >[ 13015.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537eda0] width 1280 pitch 5120 (/4 1280) >[ 13015.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d6b10] >[ 13015.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d6b10] width 1280 pitch 5120 (/4 1280) >[ 13016.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ef110] >[ 13016.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ef110] width 1280 pitch 5120 (/4 1280) >[ 13016.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d6b10] >[ 13016.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d6b10] width 1280 pitch 5120 (/4 1280) >[ 13016.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537eda0] >[ 13017.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537eda0] width 1280 pitch 5120 (/4 1280) >[ 13017.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e7c50] >[ 13017.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e7c50] width 1280 pitch 5120 (/4 1280) >[ 13017.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d6b10] >[ 13017.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d6b10] width 1280 pitch 5120 (/4 1280) >[ 13017.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536cf60] >[ 13017.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536cf60] width 1280 pitch 5120 (/4 1280) >[ 13018.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d6b10] >[ 13018.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d6b10] width 1280 pitch 5120 (/4 1280) >[ 13018.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e7c50] >[ 13018.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e7c50] width 1280 pitch 5120 (/4 1280) >[ 13018.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537eda0] >[ 13018.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537eda0] width 1280 pitch 5120 (/4 1280) >[ 13018.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x536cf60] >[ 13019.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x536cf60] width 1280 pitch 5120 (/4 1280) >[ 13019.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c4a0] >[ 13019.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c4a0] width 1280 pitch 5120 (/4 1280) >[ 13019.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537eda0] >[ 13019.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537eda0] width 1280 pitch 5120 (/4 1280) >[ 13019.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e7c50] >[ 13019.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e7c50] width 1280 pitch 5120 (/4 1280) >[ 13020.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d6b10] >[ 13020.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d6b10] width 1280 pitch 5120 (/4 1280) >[ 13020.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e7c50] >[ 13020.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e7c50] width 1280 pitch 5120 (/4 1280) >[ 13020.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537eda0] >[ 13021.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537eda0] width 1280 pitch 5120 (/4 1280) >[ 13021.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e7c50] >[ 13021.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e7c50] width 1280 pitch 5120 (/4 1280) >[ 13021.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555ec20] >[ 13021.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555ec20] width 1280 pitch 5120 (/4 1280) >[ 13021.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fd160] >[ 13021.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fd160] width 1280 pitch 5120 (/4 1280) >[ 13049.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d87a0] >[ 13049.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d87a0] width 1280 pitch 5120 (/4 1280) >[ 13049.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f4bb0] >[ 13049.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f4bb0] width 1280 pitch 5120 (/4 1280) >[ 13049.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d87a0] >[ 13049.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d87a0] width 1280 pitch 5120 (/4 1280) >[ 13049.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d87a0] >[ 13049.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d87a0] width 1280 pitch 5120 (/4 1280) >[ 13049.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52be130] >[ 13049.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52be130] width 1280 pitch 5120 (/4 1280) >[ 13049.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d87a0] >[ 13049.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d87a0] width 1280 pitch 5120 (/4 1280) >[ 13060.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a50b0] >[ 13060.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a50b0] width 1280 pitch 5120 (/4 1280) >[ 13079.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52b5ac0] >[ 13079.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52b5ac0] width 1280 pitch 5120 (/4 1280) >[ 13083.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a62b0] >[ 13083.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a62b0] width 1280 pitch 5120 (/4 1280) >[ 13119.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55dc250] >[ 13119.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55dc250] width 1280 pitch 5120 (/4 1280) >[ 13119.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a7430] >[ 13119.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a7430] width 1280 pitch 5120 (/4 1280) >[ 13223.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13223.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13223.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13224.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13224.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13224.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13224.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13224.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13224.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13224.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13224.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13225.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13225.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13225.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13225.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13225.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13225.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13226.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13227.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13227.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13227.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13227.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13228.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13228.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13228.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13228.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13228.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13228.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13229.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13229.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13229.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13229.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13229.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13229.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13230.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13230.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13230.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13230.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13231.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13231.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13233.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13233.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13233.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13234.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13234.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13234.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13234.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13234.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13236.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13236.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13236.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13236.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13240.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13240.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13240.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13240.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13240.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13240.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13241.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13241.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13245.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13245.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13245.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13246.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13248.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13248.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13248.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13248.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13248.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13248.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13250.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13250.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13251.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13251.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13251.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13251.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13251.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13252.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13252.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13252.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13252.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13252.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13252.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13252.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13252.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13252.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13253.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13253.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13253.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13253.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13253.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13254.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13254.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13254.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13254.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13254.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13254.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13254.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13255.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13255.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13255.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13255.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13255.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13255.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13255.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13255.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13255.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13256.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13256.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13256.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13256.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13256.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13256.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13256.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13256.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13257.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13258.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13258.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13258.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13258.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13259.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a8d60] >[ 13259.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a8d60] width 1280 pitch 5120 (/4 1280) >[ 13270.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 13270.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 13270.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13270.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13270.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53213f0] >[ 13270.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53213f0] width 1280 pitch 5120 (/4 1280) >[ 13270.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53213f0] >[ 13270.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53213f0] width 1280 pitch 5120 (/4 1280) >[ 13270.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13270.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13270.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53213f0] >[ 13270.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53213f0] width 1280 pitch 5120 (/4 1280) >[ 13270.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13271.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13271.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53213f0] >[ 13271.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53213f0] width 1280 pitch 5120 (/4 1280) >[ 13271.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13271.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13271.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53213f0] >[ 13271.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53213f0] width 1280 pitch 5120 (/4 1280) >[ 13271.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13271.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13272.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53213f0] >[ 13272.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53213f0] width 1280 pitch 5120 (/4 1280) >[ 13272.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13272.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13273.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53213f0] >[ 13273.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53213f0] width 1280 pitch 5120 (/4 1280) >[ 13273.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13273.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13273.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53213f0] >[ 13273.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53213f0] width 1280 pitch 5120 (/4 1280) >[ 13273.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13274.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13274.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13274.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13274.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13274.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13274.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13274.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13275.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13275.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13276.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13276.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13276.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13276.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13277.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13277.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13277.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13277.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13278.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13278.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13278.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13278.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13278.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13279.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13279.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13280.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13280.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54da660] >[ 13280.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54da660] width 1280 pitch 5120 (/4 1280) >[ 13282.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dcfe0] >[ 13282.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dcfe0] width 1280 pitch 5120 (/4 1280) >[ 13283.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e1c80] >[ 13283.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e1c80] width 1280 pitch 5120 (/4 1280) >[ 13292.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56023a0] >[ 13293.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56023a0] width 1280 pitch 5120 (/4 1280) >[ 13348.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5671750] >[ 13348.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5671750] width 1280 pitch 5120 (/4 1280) >[ 13357.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5323a90] >[ 13357.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5323a90] width 1280 pitch 5120 (/4 1280) >[ 13372.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56299b0] >[ 13372.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56299b0] width 1280 pitch 5120 (/4 1280) >[ 13441.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ea890] >[ 13441.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ea890] width 1280 pitch 5120 (/4 1280) >[ 13441.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5626ca0] >[ 13441.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5626ca0] width 1280 pitch 5120 (/4 1280) >[ 13441.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563db00] >[ 13441.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563db00] width 1280 pitch 5120 (/4 1280) >[ 13441.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ff550] >[ 13442.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ff550] width 1280 pitch 5120 (/4 1280) >[ 13442.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5626ca0] >[ 13442.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5626ca0] width 1280 pitch 5120 (/4 1280) >[ 13442.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ff550] >[ 13442.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ff550] width 1280 pitch 5120 (/4 1280) >[ 13443.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563db00] >[ 13443.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563db00] width 1280 pitch 5120 (/4 1280) >[ 13443.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5626ca0] >[ 13443.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5626ca0] width 1280 pitch 5120 (/4 1280) >[ 13443.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563db00] >[ 13443.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563db00] width 1280 pitch 5120 (/4 1280) >[ 13443.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5626ca0] >[ 13444.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5626ca0] width 1280 pitch 5120 (/4 1280) >[ 13444.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563db00] >[ 13444.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563db00] width 1280 pitch 5120 (/4 1280) >[ 13444.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5626ca0] >[ 13445.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5626ca0] width 1280 pitch 5120 (/4 1280) >[ 13445.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563db00] >[ 13445.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563db00] width 1280 pitch 5120 (/4 1280) >[ 13445.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563db00] >[ 13445.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563db00] width 1280 pitch 5120 (/4 1280) >[ 13560.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a51d0] >[ 13560.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a51d0] width 1280 pitch 5120 (/4 1280) >[ 13563.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935300] >[ 13563.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935300] width 1280 pitch 5120 (/4 1280) >[ 13563.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692a770] >[ 13563.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692a770] width 1280 pitch 5120 (/4 1280) >[ 13563.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935300] >[ 13563.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935300] width 1280 pitch 5120 (/4 1280) >[ 13563.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692a770] >[ 13563.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692a770] width 1280 pitch 5120 (/4 1280) >[ 13563.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935300] >[ 13563.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935300] width 1280 pitch 5120 (/4 1280) >[ 13588.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfd250] >[ 13588.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfd250] width 1280 pitch 5120 (/4 1280) >[ 13588.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13588.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13588.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfd250] >[ 13588.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfd250] width 1280 pitch 5120 (/4 1280) >[ 13588.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13588.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13588.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfd250] >[ 13588.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfd250] width 1280 pitch 5120 (/4 1280) >[ 13588.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69004e0] >[ 13588.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69004e0] width 1280 pitch 5120 (/4 1280) >[ 13588.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfd250] >[ 13588.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfd250] width 1280 pitch 5120 (/4 1280) >[ 13611.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13611.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13612.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13612.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13613.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13613.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13613.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13613.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13613.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13613.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13613.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13613.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13614.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13614.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13614.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13614.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13614.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13615.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13615.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13615.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13615.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13616.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13616.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13616.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13616.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13616.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13616.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13617.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13617.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13617.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13617.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13617.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13617.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13618.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13618.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13618.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13619.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13619.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13619.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13619.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13619.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13619.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13619.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13620.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13620.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6935c30] >[ 13620.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6935c30] width 1280 pitch 5120 (/4 1280) >[ 13621.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635d60] >[ 13621.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635d60] width 1280 pitch 5120 (/4 1280) >[ 13621.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635d60] >[ 13621.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635d60] width 1280 pitch 5120 (/4 1280) >[ 13707.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13707.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13707.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635d60] >[ 13708.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635d60] width 1280 pitch 5120 (/4 1280) >[ 13708.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13708.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13708.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635d60] >[ 13708.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635d60] width 1280 pitch 5120 (/4 1280) >[ 13708.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13708.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13708.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13708.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13708.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56255d0] >[ 13708.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56255d0] width 1280 pitch 5120 (/4 1280) >[ 13708.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13708.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13708.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13708.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13708.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13708.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13708.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13708.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13708.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13708.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13708.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13708.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13709.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13709.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13709.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13709.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13709.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13709.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13709.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13709.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13709.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13709.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13709.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13709.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13709.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13709.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13709.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13709.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13709.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13709.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13709.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13709.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13714.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6900830] >[ 13715.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6900830] width 1280 pitch 5120 (/4 1280) >[ 13715.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13715.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13715.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13715.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13715.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13715.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13715.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13715.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13715.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfe160] >[ 13715.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfe160] width 1280 pitch 5120 (/4 1280) >[ 13715.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13715.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13716.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfe160] >[ 13716.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfe160] width 1280 pitch 5120 (/4 1280) >[ 13716.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13716.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13716.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfe160] >[ 13716.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfe160] width 1280 pitch 5120 (/4 1280) >[ 13716.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13716.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13716.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfe160] >[ 13716.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfe160] width 1280 pitch 5120 (/4 1280) >[ 13716.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13716.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13716.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfe160] >[ 13716.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfe160] width 1280 pitch 5120 (/4 1280) >[ 13716.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13716.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13716.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfe160] >[ 13716.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfe160] width 1280 pitch 5120 (/4 1280) >[ 13716.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13716.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13740.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ffa20] >[ 13740.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ffa20] width 1280 pitch 5120 (/4 1280) >[ 13740.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e7b90] >[ 13740.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e7b90] width 1280 pitch 5120 (/4 1280) >[ 13740.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13740.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13740.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e7b90] >[ 13740.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e7b90] width 1280 pitch 5120 (/4 1280) >[ 13740.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2c740] >[ 13740.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2c740] width 1280 pitch 5120 (/4 1280) >[ 13740.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfe100] >[ 13740.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfe100] width 1280 pitch 5120 (/4 1280) >[ 13740.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13740.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13740.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bfe100] >[ 13740.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bfe100] width 1280 pitch 5120 (/4 1280) >[ 13740.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2d1e0] >[ 13741.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2d1e0] width 1280 pitch 5120 (/4 1280) >[ 13741.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f7b0] >[ 13741.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f7b0] width 1280 pitch 5120 (/4 1280) >[ 13741.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2d1e0] >[ 13741.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2d1e0] width 1280 pitch 5120 (/4 1280) >[ 13743.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2d1e0] >[ 13743.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2d1e0] width 1280 pitch 5120 (/4 1280) >[ 13744.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561d20] >[ 13744.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561d20] width 1280 pitch 5120 (/4 1280) >[ 13744.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2d1e0] >[ 13744.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2d1e0] width 1280 pitch 5120 (/4 1280) >[ 13744.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6936030] >[ 13744.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6936030] width 1280 pitch 5120 (/4 1280) >[ 13744.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff720] >[ 13744.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff720] width 1280 pitch 5120 (/4 1280) >[ 13744.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6936030] >[ 13745.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6936030] width 1280 pitch 5120 (/4 1280) >[ 13746.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561ac0] >[ 13746.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561ac0] width 1280 pitch 5120 (/4 1280) >[ 13746.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff360] >[ 13747.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff360] width 1280 pitch 5120 (/4 1280) >[ 13747.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6936030] >[ 13747.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6936030] width 1280 pitch 5120 (/4 1280) >[ 13747.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5675e70] >[ 13747.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5675e70] width 1280 pitch 5120 (/4 1280) >[ 13747.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff650] >[ 13748.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff650] width 1280 pitch 5120 (/4 1280) >[ 13748.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff6b0] >[ 13748.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff6b0] width 1280 pitch 5120 (/4 1280) >[ 13749.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff650] >[ 13749.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff650] width 1280 pitch 5120 (/4 1280) >[ 13749.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2d1a0] >[ 13749.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2d1a0] width 1280 pitch 5120 (/4 1280) >[ 13749.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff650] >[ 13750.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff650] width 1280 pitch 5120 (/4 1280) >[ 13750.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561a80] >[ 13750.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561a80] width 1280 pitch 5120 (/4 1280) >[ 13750.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a2d1a0] >[ 13751.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a2d1a0] width 1280 pitch 5120 (/4 1280) >[ 13751.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6936030] >[ 13751.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6936030] width 1280 pitch 5120 (/4 1280) >[ 13752.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff6d0] >[ 13752.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff6d0] width 1280 pitch 5120 (/4 1280) >[ 13752.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff730] >[ 13752.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff730] width 1280 pitch 5120 (/4 1280) >[ 13752.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff6d0] >[ 13752.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff6d0] width 1280 pitch 5120 (/4 1280) >[ 13753.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6936030] >[ 13753.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6936030] width 1280 pitch 5120 (/4 1280) >[ 13753.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5635c90] >[ 13753.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5635c90] width 1280 pitch 5120 (/4 1280) >[ 13753.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e7e00] >[ 13753.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e7e00] width 1280 pitch 5120 (/4 1280) >[ 13754.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561d20] >[ 13755.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561d20] width 1280 pitch 5120 (/4 1280) >[ 13755.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54de440] >[ 13755.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54de440] width 1280 pitch 5120 (/4 1280) >[ 13755.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e7e00] >[ 13755.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e7e00] width 1280 pitch 5120 (/4 1280) >[ 13755.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54de440] >[ 13756.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54de440] width 1280 pitch 5120 (/4 1280) >[ 13756.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e7e00] >[ 13756.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e7e00] width 1280 pitch 5120 (/4 1280) >[ 13756.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690d130] >[ 13756.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690d130] width 1280 pitch 5120 (/4 1280) >[ 13757.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690d130] >[ 13757.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690d130] width 1280 pitch 5120 (/4 1280) >[ 13757.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54de440] >[ 13758.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54de440] width 1280 pitch 5120 (/4 1280) >[ 13759.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561d20] >[ 13759.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561d20] width 1280 pitch 5120 (/4 1280) >[ 13760.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e7e00] >[ 13760.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e7e00] width 1280 pitch 5120 (/4 1280) >[ 13760.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690d130] >[ 13760.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690d130] width 1280 pitch 5120 (/4 1280) >[ 13760.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e7e00] >[ 13761.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e7e00] width 1280 pitch 5120 (/4 1280) >[ 13761.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690d130] >[ 13761.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690d130] width 1280 pitch 5120 (/4 1280) >[ 13763.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e7e00] >[ 13763.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e7e00] width 1280 pitch 5120 (/4 1280) >[ 13763.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690d130] >[ 13763.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690d130] width 1280 pitch 5120 (/4 1280) >[ 13764.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54de440] >[ 13764.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54de440] width 1280 pitch 5120 (/4 1280) >[ 13764.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69295f0] >[ 13764.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69295f0] width 1280 pitch 5120 (/4 1280) >[ 13972.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13972.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13972.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 13972.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 13974.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13974.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13975.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13975.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13975.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6912930] >[ 13975.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6912930] width 1280 pitch 5120 (/4 1280) >[ 13976.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13976.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13976.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13976.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13976.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13976.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13977.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 13977.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 13978.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13978.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13978.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 13978.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 13978.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13978.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13979.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13979.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13979.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 13979.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 13979.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13979.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13980.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 13980.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 13980.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13980.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 13981.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 13982.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 13982.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 13982.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 14000.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690fd50] >[ 14000.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690fd50] width 1280 pitch 5120 (/4 1280) >[ 14000.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a2c0] >[ 14000.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a2c0] width 1280 pitch 5120 (/4 1280) >[ 14001.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 14001.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 14001.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a2c0] >[ 14001.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a2c0] width 1280 pitch 5120 (/4 1280) >[ 14001.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 14001.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 14002.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a2c0] >[ 14002.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a2c0] width 1280 pitch 5120 (/4 1280) >[ 14002.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 14002.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 14002.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a2c0] >[ 14002.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a2c0] width 1280 pitch 5120 (/4 1280) >[ 14003.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 14003.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 14004.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 14004.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 14004.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 14004.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 14005.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 14005.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 14005.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930120] >[ 14005.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930120] width 1280 pitch 5120 (/4 1280) >[ 14006.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cb0e0] >[ 14006.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cb0e0] width 1280 pitch 5120 (/4 1280) >[ 14006.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fe40] >[ 14006.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fe40] width 1280 pitch 5120 (/4 1280) >[ 14309.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692e5d0] >[ 14309.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692e5d0] width 1280 pitch 5120 (/4 1280) >[ 14367.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b4180] >[ 14367.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b4180] width 1280 pitch 5120 (/4 1280) >[ 14367.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x79f2210] >[ 14367.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x79f2210] width 1280 pitch 5120 (/4 1280) >[ 14367.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1f540] >[ 14367.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1f540] width 1280 pitch 5120 (/4 1280) >[ 14367.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55fc330] >[ 14367.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55fc330] width 1280 pitch 5120 (/4 1280) >[ 14367.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b4180] >[ 14367.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b4180] width 1280 pitch 5120 (/4 1280) >[ 14431.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c00f70] >[ 14431.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c00f70] width 1280 pitch 5120 (/4 1280) >[ 14431.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d27c0] >[ 14431.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d27c0] width 1280 pitch 5120 (/4 1280) >[ 14431.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c01120] >[ 14431.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c01120] width 1280 pitch 5120 (/4 1280) >[ 14431.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e1b70] >[ 14432.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e1b70] width 1280 pitch 5120 (/4 1280) >[ 14432.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c01120] >[ 14432.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c01120] width 1280 pitch 5120 (/4 1280) >[ 14432.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c00f70] >[ 14432.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c00f70] width 1280 pitch 5120 (/4 1280) >[ 14432.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fd510] >[ 14432.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fd510] width 1280 pitch 5120 (/4 1280) >[ 14432.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x79f2210] >[ 14432.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x79f2210] width 1280 pitch 5120 (/4 1280) >[ 14436.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c01120] >[ 14436.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c01120] width 1280 pitch 5120 (/4 1280) >[ 14436.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55e2690] >[ 14436.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55e2690] width 1280 pitch 5120 (/4 1280) >[ 14522.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f33d0] >[ 14522.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f33d0] width 1280 pitch 5120 (/4 1280) >[ 14522.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929000] >[ 14522.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929000] width 1280 pitch 5120 (/4 1280) >[ 14522.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 14522.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 14522.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929000] >[ 14522.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929000] width 1280 pitch 5120 (/4 1280) >[ 14522.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692c7d0] >[ 14522.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692c7d0] width 1280 pitch 5120 (/4 1280) >[ 14522.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f33d0] >[ 14522.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f33d0] width 1280 pitch 5120 (/4 1280) >[ 14523.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929000] >[ 14523.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929000] width 1280 pitch 5120 (/4 1280) >[ 14523.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x79f2210] >[ 14523.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x79f2210] width 1280 pitch 5120 (/4 1280) >[ 14523.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929000] >[ 14523.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929000] width 1280 pitch 5120 (/4 1280) >[ 14523.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x79f2210] >[ 14523.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x79f2210] width 1280 pitch 5120 (/4 1280) >[ 14523.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929000] >[ 14523.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929000] width 1280 pitch 5120 (/4 1280) >[ 14523.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x79f2210] >[ 14523.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x79f2210] width 1280 pitch 5120 (/4 1280) >[ 14523.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929000] >[ 14523.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929000] width 1280 pitch 5120 (/4 1280) >[ 14572.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 14573.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 14573.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a29ed0] >[ 14573.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a29ed0] width 1280 pitch 5120 (/4 1280) >[ 14573.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 14573.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 14573.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a29ed0] >[ 14574.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a29ed0] width 1280 pitch 5120 (/4 1280) >[ 14574.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 14574.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 14574.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 14574.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 14575.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a29ed0] >[ 14575.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a29ed0] width 1280 pitch 5120 (/4 1280) >[ 14575.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e77a0] >[ 14575.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e77a0] width 1280 pitch 5120 (/4 1280) >[ 14640.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706fa0] >[ 14640.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706fa0] width 1280 pitch 5120 (/4 1280) >[ 14640.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0a4e0] >[ 14640.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0a4e0] width 1280 pitch 5120 (/4 1280) >[ 14641.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706fa0] >[ 14641.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706fa0] width 1280 pitch 5120 (/4 1280) >[ 14641.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0a4e0] >[ 14641.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0a4e0] width 1280 pitch 5120 (/4 1280) >[ 14641.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706fa0] >[ 14642.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706fa0] width 1280 pitch 5120 (/4 1280) >[ 14642.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706fa0] >[ 14642.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706fa0] width 1280 pitch 5120 (/4 1280) >[ 14642.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706fa0] >[ 14642.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706fa0] width 1280 pitch 5120 (/4 1280) >[ 14643.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0a4e0] >[ 14643.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0a4e0] width 1280 pitch 5120 (/4 1280) >[ 14643.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x670ff90] >[ 14643.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x670ff90] width 1280 pitch 5120 (/4 1280) >[ 14644.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0a4e0] >[ 14644.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0a4e0] width 1280 pitch 5120 (/4 1280) >[ 14644.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0a4e0] >[ 14644.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0a4e0] width 1280 pitch 5120 (/4 1280) >[ 14644.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706fa0] >[ 14645.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706fa0] width 1280 pitch 5120 (/4 1280) >[ 14645.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706ca0] >[ 14645.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706ca0] width 1280 pitch 5120 (/4 1280) >[ 14646.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706fa0] >[ 14646.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706fa0] width 1280 pitch 5120 (/4 1280) >[ 14646.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706ca0] >[ 14646.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706ca0] width 1280 pitch 5120 (/4 1280) >[ 14647.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34dafe0] >[ 14647.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34dafe0] width 1280 pitch 5120 (/4 1280) >[ 14729.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e5af0] >[ 14729.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e5af0] width 1280 pitch 5120 (/4 1280) >[ 14729.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929390] >[ 14729.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929390] width 1280 pitch 5120 (/4 1280) >[ 14729.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e5a10] >[ 14729.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e5a10] width 1280 pitch 5120 (/4 1280) >[ 14729.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e5af0] >[ 14729.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e5af0] width 1280 pitch 5120 (/4 1280) >[ 14729.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a07090] >[ 14729.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a07090] width 1280 pitch 5120 (/4 1280) >[ 14729.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e5a10] >[ 14729.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e5a10] width 1280 pitch 5120 (/4 1280) >[ 14729.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929390] >[ 14729.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929390] width 1280 pitch 5120 (/4 1280) >[ 14729.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929540] >[ 14729.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929540] width 1280 pitch 5120 (/4 1280) >[ 14729.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a54d0] >[ 14729.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a54d0] width 1280 pitch 5120 (/4 1280) >[ 14729.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69294e0] >[ 14730.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69294e0] width 1280 pitch 5120 (/4 1280) >[ 14730.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a54d0] >[ 14730.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a54d0] width 1280 pitch 5120 (/4 1280) >[ 14730.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69294e0] >[ 14730.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69294e0] width 1280 pitch 5120 (/4 1280) >[ 14730.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a54d0] >[ 14730.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a54d0] width 1280 pitch 5120 (/4 1280) >[ 14730.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69294e0] >[ 14730.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69294e0] width 1280 pitch 5120 (/4 1280) >[ 14730.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a54d0] >[ 14730.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a54d0] width 1280 pitch 5120 (/4 1280) >[ 14730.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69294e0] >[ 14730.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69294e0] width 1280 pitch 5120 (/4 1280) >[ 14730.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a54d0] >[ 14730.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a54d0] width 1280 pitch 5120 (/4 1280) >[ 15074.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e5950] >[ 15074.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e5950] width 1280 pitch 5120 (/4 1280) >[ 15074.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e58b0] >[ 15074.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e58b0] width 1280 pitch 5120 (/4 1280) >[ 15077.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6902240] >[ 15077.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6902240] width 1280 pitch 5120 (/4 1280) >[ 15077.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6714730] >[ 15077.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6714730] width 1280 pitch 5120 (/4 1280) >[ 15077.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a08fd0] >[ 15077.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a08fd0] width 1280 pitch 5120 (/4 1280) >[ 15077.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e5ab0] >[ 15077.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e5ab0] width 1280 pitch 5120 (/4 1280) >[ 15077.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a08fd0] >[ 15077.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a08fd0] width 1280 pitch 5120 (/4 1280) >[ 15077.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e5ab0] >[ 15077.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e5ab0] width 1280 pitch 5120 (/4 1280) >[ 15084.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690e180] >[ 15084.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690e180] width 1280 pitch 5120 (/4 1280) >[ 15084.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6714bb0] >[ 15084.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6714bb0] width 1280 pitch 5120 (/4 1280) >[ 15084.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e8e0] >[ 15084.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e8e0] width 1280 pitch 5120 (/4 1280) >[ 15084.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0b5a0] >[ 15084.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0b5a0] width 1280 pitch 5120 (/4 1280) >[ 15084.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e8e0] >[ 15084.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e8e0] width 1280 pitch 5120 (/4 1280) >[ 15084.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0b5a0] >[ 15084.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0b5a0] width 1280 pitch 5120 (/4 1280) >[ 15084.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e8e0] >[ 15084.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e8e0] width 1280 pitch 5120 (/4 1280) >[ 15092.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929390] >[ 15092.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929390] width 1280 pitch 5120 (/4 1280) >[ 15092.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6902240] >[ 15092.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6902240] width 1280 pitch 5120 (/4 1280) >[ 15092.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706cd0] >[ 15092.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706cd0] width 1280 pitch 5120 (/4 1280) >[ 15092.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c01fa0] >[ 15093.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c01fa0] width 1280 pitch 5120 (/4 1280) >[ 15093.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c01f40] >[ 15093.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c01f40] width 1280 pitch 5120 (/4 1280) >[ 15093.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c01fa0] >[ 15093.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c01fa0] width 1280 pitch 5120 (/4 1280) >[ 15093.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c01f40] >[ 15094.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c01f40] width 1280 pitch 5120 (/4 1280) >[ 15094.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c01fa0] >[ 15094.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c01fa0] width 1280 pitch 5120 (/4 1280) >[ 15094.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a07010] >[ 15095.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a07010] width 1280 pitch 5120 (/4 1280) >[ 15095.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0ae30] >[ 15095.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0ae30] width 1280 pitch 5120 (/4 1280) >[ 15099.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0c5f0] >[ 15099.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0c5f0] width 1280 pitch 5120 (/4 1280) >[ 15321.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6778530] >[ 15321.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6778530] width 1280 pitch 5120 (/4 1280) >[ 15321.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a21290] >[ 15321.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a21290] width 1280 pitch 5120 (/4 1280) >[ 15332.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e670] >[ 15332.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e670] width 1280 pitch 5120 (/4 1280) >[ 15333.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e6b0] >[ 15333.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e6b0] width 1280 pitch 5120 (/4 1280) >[ 15333.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e610] >[ 15333.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e610] width 1280 pitch 5120 (/4 1280) >[ 15333.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e6b0] >[ 15334.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e6b0] width 1280 pitch 5120 (/4 1280) >[ 15334.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e610] >[ 15335.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e610] width 1280 pitch 5120 (/4 1280) >[ 15335.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e6b0] >[ 15335.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e6b0] width 1280 pitch 5120 (/4 1280) >[ 15335.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67429e0] >[ 15335.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67429e0] width 1280 pitch 5120 (/4 1280) >[ 15336.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929270] >[ 15336.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929270] width 1280 pitch 5120 (/4 1280) >[ 15336.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e6b0] >[ 15336.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e6b0] width 1280 pitch 5120 (/4 1280) >[ 15336.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929270] >[ 15336.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929270] width 1280 pitch 5120 (/4 1280) >[ 15336.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e6b0] >[ 15337.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e6b0] width 1280 pitch 5120 (/4 1280) >[ 15338.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6929270] >[ 15338.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6929270] width 1280 pitch 5120 (/4 1280) >[ 15338.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5600460] >[ 15338.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5600460] width 1280 pitch 5120 (/4 1280) >[ 15338.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566cae0] >[ 15338.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566cae0] width 1280 pitch 5120 (/4 1280) >[ 15344.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f98f0] >[ 15344.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f98f0] width 1280 pitch 5120 (/4 1280) >[ 15345.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537a800] >[ 15345.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537a800] width 1280 pitch 5120 (/4 1280) >[ 15345.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6778110] >[ 15345.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6778110] width 1280 pitch 5120 (/4 1280) >[ 15345.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362b20] >[ 15345.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362b20] width 1280 pitch 5120 (/4 1280) >[ 15431.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5356d10] >[ 15431.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5356d10] width 1280 pitch 5120 (/4 1280) >[ 15431.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5362b20] >[ 15431.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5362b20] width 1280 pitch 5120 (/4 1280) >[ 15537.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5356d10] >[ 15537.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5356d10] width 1280 pitch 5120 (/4 1280) >[ 15537.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543db0] >[ 15537.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543db0] width 1280 pitch 5120 (/4 1280) >[ 15537.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f950] >[ 15537.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f950] width 1280 pitch 5120 (/4 1280) >[ 15537.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543db0] >[ 15537.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543db0] width 1280 pitch 5120 (/4 1280) >[ 15537.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f950] >[ 15537.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f950] width 1280 pitch 5120 (/4 1280) >[ 15561.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x79efbd0] >[ 15561.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x79efbd0] width 1280 pitch 5120 (/4 1280) >[ 15561.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6707320] >[ 15561.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6707320] width 1280 pitch 5120 (/4 1280) >[ 15561.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6707320] >[ 15561.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6707320] width 1280 pitch 5120 (/4 1280) >[ 15561.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e2d00] >[ 15562.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e2d00] width 1280 pitch 5120 (/4 1280) >[ 15562.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6707320] >[ 15562.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6707320] width 1280 pitch 5120 (/4 1280) >[ 15562.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6707320] >[ 15562.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6707320] width 1280 pitch 5120 (/4 1280) >[ 15563.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6707320] >[ 15563.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6707320] width 1280 pitch 5120 (/4 1280) >[ 15563.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f9600] >[ 15563.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f9600] width 1280 pitch 5120 (/4 1280) >[ 15563.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f9600] >[ 15563.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f9600] width 1280 pitch 5120 (/4 1280) >[ 15563.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f9600] >[ 15563.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f9600] width 1280 pitch 5120 (/4 1280) >[ 15565.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0ae30] >[ 15565.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0ae30] width 1280 pitch 5120 (/4 1280) >[ 15569.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d6d80] >[ 15569.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d6d80] width 1280 pitch 5120 (/4 1280) >[ 15688.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f090] >[ 15688.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f090] width 1280 pitch 5120 (/4 1280) >[ 15688.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 15688.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 15689.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55530d0] >[ 15689.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55530d0] width 1280 pitch 5120 (/4 1280) >[ 15689.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d7980] >[ 15689.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d7980] width 1280 pitch 5120 (/4 1280) >[ 15691.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 15691.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 15691.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d7980] >[ 15692.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d7980] width 1280 pitch 5120 (/4 1280) >[ 15693.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55daee0] >[ 15693.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55daee0] width 1280 pitch 5120 (/4 1280) >[ 15693.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 15694.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 15696.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f090] >[ 15696.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f090] width 1280 pitch 5120 (/4 1280) >[ 15696.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 15696.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 15697.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f090] >[ 15697.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f090] width 1280 pitch 5120 (/4 1280) >[ 15697.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c69280] >[ 15697.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c69280] width 1280 pitch 5120 (/4 1280) >[ 15697.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 15697.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 15705.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf010] >[ 15705.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf010] width 1280 pitch 5120 (/4 1280) >[ 15705.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf010] >[ 15705.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf010] width 1280 pitch 5120 (/4 1280) >[ 15706.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cf010] >[ 15706.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cf010] width 1280 pitch 5120 (/4 1280) >[ 15706.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a19240] >[ 15706.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a19240] width 1280 pitch 5120 (/4 1280) >[ 15706.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55fc160] >[ 15707.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55fc160] width 1280 pitch 5120 (/4 1280) >[ 15707.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a19240] >[ 15707.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a19240] width 1280 pitch 5120 (/4 1280) >[ 15707.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406a30] >[ 15707.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406a30] width 1280 pitch 5120 (/4 1280) >[ 15708.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55fc410] >[ 15708.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55fc410] width 1280 pitch 5120 (/4 1280) >[ 15708.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c69280] >[ 15708.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c69280] width 1280 pitch 5120 (/4 1280) >[ 15708.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406a30] >[ 15709.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406a30] width 1280 pitch 5120 (/4 1280) >[ 15709.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c69280] >[ 15709.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c69280] width 1280 pitch 5120 (/4 1280) >[ 15709.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406a30] >[ 15709.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406a30] width 1280 pitch 5120 (/4 1280) >[ 15709.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c69280] >[ 15709.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c69280] width 1280 pitch 5120 (/4 1280) >[ 15710.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55fc410] >[ 15710.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55fc410] width 1280 pitch 5120 (/4 1280) >[ 15710.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406a30] >[ 15710.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406a30] width 1280 pitch 5120 (/4 1280) >[ 15710.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffe40] >[ 15711.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffe40] width 1280 pitch 5120 (/4 1280) >[ 15711.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406a30] >[ 15711.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406a30] width 1280 pitch 5120 (/4 1280) >[ 15711.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffe40] >[ 15711.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffe40] width 1280 pitch 5120 (/4 1280) >[ 15712.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6711930] >[ 15712.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6711930] width 1280 pitch 5120 (/4 1280) >[ 16050.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16050.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16050.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16050.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16050.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16050.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16050.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16050.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16051.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16051.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16051.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16051.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16051.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16051.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16051.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16052.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16052.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16052.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16052.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16052.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16053.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16053.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16053.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16053.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16053.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16053.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16054.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16054.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16054.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16054.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16054.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16054.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16055.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16055.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16055.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16055.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16058.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16058.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16058.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16058.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16058.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16058.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16058.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16059.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16059.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16059.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16059.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16059.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16060.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16060.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16060.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16060.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16061.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16061.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16061.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16061.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16061.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16062.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16062.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0af40] >[ 16062.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0af40] width 1280 pitch 5120 (/4 1280) >[ 16062.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16062.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16063.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5634860] >[ 16063.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5634860] width 1280 pitch 5120 (/4 1280) >[ 16159.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554bda0] >[ 16159.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554bda0] width 1280 pitch 5120 (/4 1280) >[ 16159.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x537a800] >[ 16159.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x537a800] width 1280 pitch 5120 (/4 1280) >[ 16159.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554bda0] >[ 16159.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554bda0] width 1280 pitch 5120 (/4 1280) >[ 16159.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16159.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16159.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554bda0] >[ 16159.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554bda0] width 1280 pitch 5120 (/4 1280) >[ 16159.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16159.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16179.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16179.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16179.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16179.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16179.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16179.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16179.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16179.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16179.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16179.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16179.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16179.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16179.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16179.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16179.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16179.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16181.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16181.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16181.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5642830] >[ 16181.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5642830] width 1280 pitch 5120 (/4 1280) >[ 16181.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f0f0] >[ 16181.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f0f0] width 1280 pitch 5120 (/4 1280) >[ 16181.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16182.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16182.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16182.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16182.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16182.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16184.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554bda0] >[ 16184.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554bda0] width 1280 pitch 5120 (/4 1280) >[ 16186.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d74f0] >[ 16186.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d74f0] width 1280 pitch 5120 (/4 1280) >[ 16186.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554bda0] >[ 16186.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554bda0] width 1280 pitch 5120 (/4 1280) >[ 16186.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffb70] >[ 16186.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffb70] width 1280 pitch 5120 (/4 1280) >[ 16197.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f900] >[ 16197.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f900] width 1280 pitch 5120 (/4 1280) >[ 16197.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0b250] >[ 16197.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0b250] width 1280 pitch 5120 (/4 1280) >[ 16214.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a09b30] >[ 16214.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a09b30] width 1280 pitch 5120 (/4 1280) >[ 16215.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6777cc0] >[ 16215.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6777cc0] width 1280 pitch 5120 (/4 1280) >[ 16215.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f900] >[ 16215.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f900] width 1280 pitch 5120 (/4 1280) >[ 16215.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f7e0] >[ 16215.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f7e0] width 1280 pitch 5120 (/4 1280) >[ 16216.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53234c0] >[ 16216.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53234c0] width 1280 pitch 5120 (/4 1280) >[ 16216.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f900] >[ 16216.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f900] width 1280 pitch 5120 (/4 1280) >[ 16216.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f7e0] >[ 16217.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f7e0] width 1280 pitch 5120 (/4 1280) >[ 16217.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560a9c0] >[ 16217.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560a9c0] width 1280 pitch 5120 (/4 1280) >[ 16217.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566f7e0] >[ 16218.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566f7e0] width 1280 pitch 5120 (/4 1280) >[ 16218.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a09b30] >[ 16218.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a09b30] width 1280 pitch 5120 (/4 1280) >[ 16218.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53234c0] >[ 16218.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53234c0] width 1280 pitch 5120 (/4 1280) >[ 16219.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34db6d0] >[ 16219.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34db6d0] width 1280 pitch 5120 (/4 1280) >[ 16219.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f900] >[ 16219.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f900] width 1280 pitch 5120 (/4 1280) >[ 16246.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f900] >[ 16246.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f900] width 1280 pitch 5120 (/4 1280) >[ 16246.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16246.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16249.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f900] >[ 16249.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f900] width 1280 pitch 5120 (/4 1280) >[ 16249.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16249.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16250.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f0f0] >[ 16250.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f0f0] width 1280 pitch 5120 (/4 1280) >[ 16251.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5555230] >[ 16251.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5555230] width 1280 pitch 5120 (/4 1280) >[ 16251.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f0f0] >[ 16251.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f0f0] width 1280 pitch 5120 (/4 1280) >[ 16251.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16251.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16252.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f0f0] >[ 16252.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f0f0] width 1280 pitch 5120 (/4 1280) >[ 16252.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16252.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16253.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1dcf0] >[ 16253.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1dcf0] width 1280 pitch 5120 (/4 1280) >[ 16253.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffa80] >[ 16253.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffa80] width 1280 pitch 5120 (/4 1280) >[ 16254.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffa80] >[ 16254.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffa80] width 1280 pitch 5120 (/4 1280) >[ 16258.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16258.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16258.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16258.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16258.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffa80] >[ 16258.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffa80] width 1280 pitch 5120 (/4 1280) >[ 16259.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16259.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16259.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffa80] >[ 16259.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffa80] width 1280 pitch 5120 (/4 1280) >[ 16259.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16259.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16259.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54deaa0] >[ 16259.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54deaa0] width 1280 pitch 5120 (/4 1280) >[ 16259.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722600] >[ 16260.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722600] width 1280 pitch 5120 (/4 1280) >[ 16260.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16260.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16260.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffa80] >[ 16261.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffa80] width 1280 pitch 5120 (/4 1280) >[ 16261.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16261.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16261.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54deaa0] >[ 16261.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54deaa0] width 1280 pitch 5120 (/4 1280) >[ 16262.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffa80] >[ 16263.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffa80] width 1280 pitch 5120 (/4 1280) >[ 16263.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54deaa0] >[ 16263.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54deaa0] width 1280 pitch 5120 (/4 1280) >[ 16264.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffe40] >[ 16264.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffe40] width 1280 pitch 5120 (/4 1280) >[ 16286.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16286.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16287.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffe40] >[ 16287.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffe40] width 1280 pitch 5120 (/4 1280) >[ 16287.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16287.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16287.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f220] >[ 16287.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f220] width 1280 pitch 5120 (/4 1280) >[ 16287.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16288.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16288.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f220] >[ 16288.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f220] width 1280 pitch 5120 (/4 1280) >[ 16289.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54deaa0] >[ 16289.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54deaa0] width 1280 pitch 5120 (/4 1280) >[ 16289.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f220] >[ 16289.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f220] width 1280 pitch 5120 (/4 1280) >[ 16291.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffe40] >[ 16291.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffe40] width 1280 pitch 5120 (/4 1280) >[ 16292.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563f220] >[ 16293.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563f220] width 1280 pitch 5120 (/4 1280) >[ 16293.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16293.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16293.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffe40] >[ 16293.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffe40] width 1280 pitch 5120 (/4 1280) >[ 16294.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54deaa0] >[ 16294.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54deaa0] width 1280 pitch 5120 (/4 1280) >[ 16294.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ffe40] >[ 16294.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ffe40] width 1280 pitch 5120 (/4 1280) >[ 16294.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555e0c0] >[ 16294.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555e0c0] width 1280 pitch 5120 (/4 1280) >[ 16295.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54deaa0] >[ 16295.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54deaa0] width 1280 pitch 5120 (/4 1280) >[ 16295.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0ad50] >[ 16295.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0ad50] width 1280 pitch 5120 (/4 1280) >[ 16295.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54deaa0] >[ 16296.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54deaa0] width 1280 pitch 5120 (/4 1280) >[ 16558.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fc460] >[ 16558.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fc460] width 1280 pitch 5120 (/4 1280) >[ 16558.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fc890] >[ 16558.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fc890] width 1280 pitch 5120 (/4 1280) >[ 16558.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fb4b0] >[ 16558.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fb4b0] width 1280 pitch 5120 (/4 1280) >[ 16558.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fc890] >[ 16558.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fc890] width 1280 pitch 5120 (/4 1280) >[ 16559.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fc190] >[ 16559.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fc190] width 1280 pitch 5120 (/4 1280) >[ 16569.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fc890] >[ 16569.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fc890] width 1280 pitch 5120 (/4 1280) >[ 16570.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563bb50] >[ 16570.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563bb50] width 1280 pitch 5120 (/4 1280) >[ 16570.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fc890] >[ 16570.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fc890] width 1280 pitch 5120 (/4 1280) >[ 16570.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563bb50] >[ 16570.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563bb50] width 1280 pitch 5120 (/4 1280) >[ 16572.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563bb50] >[ 16572.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563bb50] width 1280 pitch 5120 (/4 1280) >[ 16572.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a09e30] >[ 16572.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a09e30] width 1280 pitch 5120 (/4 1280) >[ 16572.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563bb50] >[ 16572.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563bb50] width 1280 pitch 5120 (/4 1280) >[ 16572.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a09e30] >[ 16573.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a09e30] width 1280 pitch 5120 (/4 1280) >[ 16573.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563bb50] >[ 16573.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563bb50] width 1280 pitch 5120 (/4 1280) >[ 16573.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a09e30] >[ 16573.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a09e30] width 1280 pitch 5120 (/4 1280) >[ 16574.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563bb50] >[ 16574.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563bb50] width 1280 pitch 5120 (/4 1280) >[ 16574.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a09e30] >[ 16574.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a09e30] width 1280 pitch 5120 (/4 1280) >[ 16589.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677c730] >[ 16589.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677c730] width 1280 pitch 5120 (/4 1280) >[ 16589.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a540] >[ 16590.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a540] width 1280 pitch 5120 (/4 1280) >[ 16590.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5639e80] >[ 16590.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5639e80] width 1280 pitch 5120 (/4 1280) >[ 16590.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6732ef0] >[ 16590.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6732ef0] width 1280 pitch 5120 (/4 1280) >[ 16590.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673bfd0] >[ 16590.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673bfd0] width 1280 pitch 5120 (/4 1280) >[ 16590.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a4e0] >[ 16590.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a4e0] width 1280 pitch 5120 (/4 1280) >[ 16590.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a4e0] >[ 16590.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a4e0] width 1280 pitch 5120 (/4 1280) >[ 16590.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a4e0] >[ 16591.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a4e0] width 1280 pitch 5120 (/4 1280) >[ 16591.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55d9d90] >[ 16591.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55d9d90] width 1280 pitch 5120 (/4 1280) >[ 16591.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5639de0] >[ 16591.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5639de0] width 1280 pitch 5120 (/4 1280) >[ 16591.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5639de0] >[ 16591.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5639de0] width 1280 pitch 5120 (/4 1280) >[ 16591.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55d9d90] >[ 16591.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55d9d90] width 1280 pitch 5120 (/4 1280) >[ 16591.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55d9d90] >[ 16591.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55d9d90] width 1280 pitch 5120 (/4 1280) >[ 16591.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67762c0] >[ 16591.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67762c0] width 1280 pitch 5120 (/4 1280) >[ 16591.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a4e0] >[ 16591.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a4e0] width 1280 pitch 5120 (/4 1280) >[ 16591.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67762c0] >[ 16592.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67762c0] width 1280 pitch 5120 (/4 1280) >[ 16592.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c090] >[ 16592.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c090] width 1280 pitch 5120 (/4 1280) >[ 16592.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6737040] >[ 16592.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6737040] width 1280 pitch 5120 (/4 1280) >[ 16658.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 16658.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 16662.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677e8f0] >[ 16662.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677e8f0] width 1280 pitch 5120 (/4 1280) >[ 16662.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bc10] >[ 16662.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bc10] width 1280 pitch 5120 (/4 1280) >[ 16768.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738380] >[ 16768.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738380] width 1280 pitch 5120 (/4 1280) >[ 16768.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fec0] >[ 16768.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fec0] width 1280 pitch 5120 (/4 1280) >[ 16768.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738380] >[ 16768.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738380] width 1280 pitch 5120 (/4 1280) >[ 16768.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fec0] >[ 16768.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fec0] width 1280 pitch 5120 (/4 1280) >[ 16768.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738380] >[ 16768.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738380] width 1280 pitch 5120 (/4 1280) >[ 16864.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 16864.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 16864.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 16864.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 16864.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 16864.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 16864.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 16864.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 16864.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 16864.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 16864.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 16864.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 16864.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 16864.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 16864.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 16864.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 16864.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 16864.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 16864.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 16865.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 16865.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6784e70] >[ 16865.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6784e70] width 1280 pitch 5120 (/4 1280) >[ 16865.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 16865.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 16865.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6784e70] >[ 16865.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6784e70] width 1280 pitch 5120 (/4 1280) >[ 16881.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6777980] >[ 16881.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6777980] width 1280 pitch 5120 (/4 1280) >[ 16881.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb100] >[ 16881.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb100] width 1280 pitch 5120 (/4 1280) >[ 16890.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 16890.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 16891.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678e040] >[ 16891.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678e040] width 1280 pitch 5120 (/4 1280) >[ 16892.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 16892.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 16892.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7d00] >[ 16892.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7d00] width 1280 pitch 5120 (/4 1280) >[ 16892.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678e040] >[ 16892.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678e040] width 1280 pitch 5120 (/4 1280) >[ 16892.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7d00] >[ 16893.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7d00] width 1280 pitch 5120 (/4 1280) >[ 16893.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678e040] >[ 16893.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678e040] width 1280 pitch 5120 (/4 1280) >[ 16893.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7d00] >[ 16893.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7d00] width 1280 pitch 5120 (/4 1280) >[ 16894.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678e040] >[ 16894.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678e040] width 1280 pitch 5120 (/4 1280) >[ 16894.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7d00] >[ 16895.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7d00] width 1280 pitch 5120 (/4 1280) >[ 16895.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678e040] >[ 16895.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678e040] width 1280 pitch 5120 (/4 1280) >[ 16895.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7d00] >[ 16895.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7d00] width 1280 pitch 5120 (/4 1280) >[ 16895.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678e040] >[ 16896.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678e040] width 1280 pitch 5120 (/4 1280) >[ 16896.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7d00] >[ 16896.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7d00] width 1280 pitch 5120 (/4 1280) >[ 16896.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678e040] >[ 16896.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678e040] width 1280 pitch 5120 (/4 1280) >[ 16896.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7d00] >[ 16896.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7d00] width 1280 pitch 5120 (/4 1280) >[ 17115.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56708b0] >[ 17115.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56708b0] width 1280 pitch 5120 (/4 1280) >[ 17116.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6772650] >[ 17116.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6772650] width 1280 pitch 5120 (/4 1280) >[ 17116.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17116.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17116.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6772650] >[ 17116.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6772650] width 1280 pitch 5120 (/4 1280) >[ 17116.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17116.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17118.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c02050] >[ 17118.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c02050] width 1280 pitch 5120 (/4 1280) >[ 17118.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17118.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17119.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c02050] >[ 17119.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c02050] width 1280 pitch 5120 (/4 1280) >[ 17119.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17119.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17120.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17120.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17120.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706ec0] >[ 17120.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706ec0] width 1280 pitch 5120 (/4 1280) >[ 17120.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17121.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17121.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706ec0] >[ 17121.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706ec0] width 1280 pitch 5120 (/4 1280) >[ 17121.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17121.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17123.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56708b0] >[ 17123.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56708b0] width 1280 pitch 5120 (/4 1280) >[ 17123.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6772650] >[ 17123.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6772650] width 1280 pitch 5120 (/4 1280) >[ 17123.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56708b0] >[ 17123.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56708b0] width 1280 pitch 5120 (/4 1280) >[ 17123.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d43a0] >[ 17124.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d43a0] width 1280 pitch 5120 (/4 1280) >[ 17124.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56708b0] >[ 17124.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56708b0] width 1280 pitch 5120 (/4 1280) >[ 17124.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d43a0] >[ 17124.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d43a0] width 1280 pitch 5120 (/4 1280) >[ 17124.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56708b0] >[ 17125.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56708b0] width 1280 pitch 5120 (/4 1280) >[ 17125.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d43a0] >[ 17125.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d43a0] width 1280 pitch 5120 (/4 1280) >[ 17125.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56708b0] >[ 17126.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56708b0] width 1280 pitch 5120 (/4 1280) >[ 17126.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17126.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17126.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706ec0] >[ 17127.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706ec0] width 1280 pitch 5120 (/4 1280) >[ 17127.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17127.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17127.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706ec0] >[ 17127.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706ec0] width 1280 pitch 5120 (/4 1280) >[ 17127.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17127.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17128.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6706ec0] >[ 17128.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6706ec0] width 1280 pitch 5120 (/4 1280) >[ 17129.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6908cd0] >[ 17129.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6908cd0] width 1280 pitch 5120 (/4 1280) >[ 17129.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6772650] >[ 17129.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6772650] width 1280 pitch 5120 (/4 1280) >[ 17129.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6908cd0] >[ 17130.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6908cd0] width 1280 pitch 5120 (/4 1280) >[ 17130.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673aa00] >[ 17130.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673aa00] width 1280 pitch 5120 (/4 1280) >[ 17130.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738b50] >[ 17130.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738b50] width 1280 pitch 5120 (/4 1280) >[ 17131.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673aa00] >[ 17131.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673aa00] width 1280 pitch 5120 (/4 1280) >[ 17131.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738b50] >[ 17132.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738b50] width 1280 pitch 5120 (/4 1280) >[ 17132.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673aa00] >[ 17132.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673aa00] width 1280 pitch 5120 (/4 1280) >[ 17132.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1bd10] >[ 17132.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1bd10] width 1280 pitch 5120 (/4 1280) >[ 17132.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673aa00] >[ 17133.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673aa00] width 1280 pitch 5120 (/4 1280) >[ 17135.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6772650] >[ 17135.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6772650] width 1280 pitch 5120 (/4 1280) >[ 17135.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6908cd0] >[ 17136.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6908cd0] width 1280 pitch 5120 (/4 1280) >[ 17137.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6772650] >[ 17137.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6772650] width 1280 pitch 5120 (/4 1280) >[ 17137.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a480] >[ 17137.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a480] width 1280 pitch 5120 (/4 1280) >[ 17268.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56086e0] >[ 17268.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56086e0] width 1280 pitch 5120 (/4 1280) >[ 17268.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b3d10] >[ 17268.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b3d10] width 1280 pitch 5120 (/4 1280) >[ 17268.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ba9b0] >[ 17268.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ba9b0] width 1280 pitch 5120 (/4 1280) >[ 17268.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608450] >[ 17268.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608450] width 1280 pitch 5120 (/4 1280) >[ 17268.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d9d30] >[ 17269.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d9d30] width 1280 pitch 5120 (/4 1280) >[ 17269.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608450] >[ 17269.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608450] width 1280 pitch 5120 (/4 1280) >[ 17270.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ba9b0] >[ 17270.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ba9b0] width 1280 pitch 5120 (/4 1280) >[ 17270.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3723ee0] >[ 17270.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3723ee0] width 1280 pitch 5120 (/4 1280) >[ 17270.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fc9b0] >[ 17271.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fc9b0] width 1280 pitch 5120 (/4 1280) >[ 17272.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fc9b0] >[ 17272.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fc9b0] width 1280 pitch 5120 (/4 1280) >[ 17272.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6460] >[ 17272.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6460] width 1280 pitch 5120 (/4 1280) >[ 17277.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6964da0] >[ 17277.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6964da0] width 1280 pitch 5120 (/4 1280) >[ 17277.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f430] >[ 17277.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f430] width 1280 pitch 5120 (/4 1280) >[ 17286.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17286.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17287.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17287.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17287.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17287.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17287.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17287.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17287.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17287.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17287.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17287.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17288.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17288.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17291.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17291.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17291.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17291.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17291.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17291.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17291.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17291.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17291.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17291.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17291.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17291.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17293.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17293.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17293.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17293.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17293.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17293.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17293.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17293.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17293.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17293.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17297.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6460] >[ 17297.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6460] width 1280 pitch 5120 (/4 1280) >[ 17297.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17297.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17297.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6460] >[ 17297.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6460] width 1280 pitch 5120 (/4 1280) >[ 17297.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17297.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17297.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x71a6460] >[ 17297.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x71a6460] width 1280 pitch 5120 (/4 1280) >[ 17372.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17373.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17373.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17373.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17373.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dac0] >[ 17373.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dac0] width 1280 pitch 5120 (/4 1280) >[ 17373.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561dcc0] >[ 17373.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561dcc0] width 1280 pitch 5120 (/4 1280) >[ 17373.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561e8c0] >[ 17373.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561e8c0] width 1280 pitch 5120 (/4 1280) >[ 17376.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f8b0] >[ 17376.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f8b0] width 1280 pitch 5120 (/4 1280) >[ 17376.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bc050] >[ 17376.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bc050] width 1280 pitch 5120 (/4 1280) >[ 17376.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cb850] >[ 17376.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cb850] width 1280 pitch 5120 (/4 1280) >[ 17376.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678fee0] >[ 17376.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678fee0] width 1280 pitch 5120 (/4 1280) >[ 17377.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8c60] >[ 17377.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8c60] width 1280 pitch 5120 (/4 1280) >[ 17377.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561e8c0] >[ 17377.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561e8c0] width 1280 pitch 5120 (/4 1280) >[ 17377.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678fee0] >[ 17377.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678fee0] width 1280 pitch 5120 (/4 1280) >[ 17377.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561e8c0] >[ 17377.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561e8c0] width 1280 pitch 5120 (/4 1280) >[ 17377.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678fee0] >[ 17377.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678fee0] width 1280 pitch 5120 (/4 1280) >[ 17377.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561e8c0] >[ 17377.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561e8c0] width 1280 pitch 5120 (/4 1280) >[ 17423.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b9460] >[ 17423.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b9460] width 1280 pitch 5120 (/4 1280) >[ 17423.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17423.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17423.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b9460] >[ 17423.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b9460] width 1280 pitch 5120 (/4 1280) >[ 17423.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17423.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17423.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b9460] >[ 17423.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b9460] width 1280 pitch 5120 (/4 1280) >[ 17423.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17423.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17423.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b9460] >[ 17423.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b9460] width 1280 pitch 5120 (/4 1280) >[ 17424.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d9b90] >[ 17424.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d9b90] width 1280 pitch 5120 (/4 1280) >[ 17424.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17424.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17425.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17425.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17425.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8a50] >[ 17425.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8a50] width 1280 pitch 5120 (/4 1280) >[ 17425.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17425.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17425.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8a50] >[ 17425.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8a50] width 1280 pitch 5120 (/4 1280) >[ 17425.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17425.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17426.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17426.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17426.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8a50] >[ 17426.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8a50] width 1280 pitch 5120 (/4 1280) >[ 17426.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17426.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17426.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f8a50] >[ 17426.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f8a50] width 1280 pitch 5120 (/4 1280) >[ 17426.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17426.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17461.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cb800] >[ 17461.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cb800] width 1280 pitch 5120 (/4 1280) >[ 17461.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17461.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17462.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cb800] >[ 17462.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cb800] width 1280 pitch 5120 (/4 1280) >[ 17462.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ba8b0] >[ 17462.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ba8b0] width 1280 pitch 5120 (/4 1280) >[ 17462.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17462.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17462.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ba8b0] >[ 17463.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ba8b0] width 1280 pitch 5120 (/4 1280) >[ 17463.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17463.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17463.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ba8b0] >[ 17463.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ba8b0] width 1280 pitch 5120 (/4 1280) >[ 17463.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17463.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17463.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ba8b0] >[ 17464.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ba8b0] width 1280 pitch 5120 (/4 1280) >[ 17464.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17464.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17464.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55ba8b0] >[ 17464.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55ba8b0] width 1280 pitch 5120 (/4 1280) >[ 17465.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cb800] >[ 17465.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cb800] width 1280 pitch 5120 (/4 1280) >[ 17466.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a370] >[ 17466.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a370] width 1280 pitch 5120 (/4 1280) >[ 17502.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34db540] >[ 17502.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34db540] width 1280 pitch 5120 (/4 1280) >[ 17502.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c1850] >[ 17502.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c1850] width 1280 pitch 5120 (/4 1280) >[ 17502.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 17502.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 17502.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34db540] >[ 17502.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34db540] width 1280 pitch 5120 (/4 1280) >[ 17502.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c9a70] >[ 17502.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c9a70] width 1280 pitch 5120 (/4 1280) >[ 17502.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34db540] >[ 17502.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34db540] width 1280 pitch 5120 (/4 1280) >[ 17502.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c9a70] >[ 17502.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c9a70] width 1280 pitch 5120 (/4 1280) >[ 17502.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34db540] >[ 17502.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34db540] width 1280 pitch 5120 (/4 1280) >[ 17503.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67108b0] >[ 17503.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67108b0] width 1280 pitch 5120 (/4 1280) >[ 17523.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6704ac0] >[ 17523.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6704ac0] width 1280 pitch 5120 (/4 1280) >[ 17526.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c1850] >[ 17526.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c1850] width 1280 pitch 5120 (/4 1280) >[ 17542.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561be40] >[ 17542.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561be40] width 1280 pitch 5120 (/4 1280) >[ 17542.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c1850] >[ 17542.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c1850] width 1280 pitch 5120 (/4 1280) >[ 17542.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d0420] >[ 17542.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d0420] width 1280 pitch 5120 (/4 1280) >[ 17542.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c1850] >[ 17542.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c1850] width 1280 pitch 5120 (/4 1280) >[ 17548.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608cc0] >[ 17548.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608cc0] width 1280 pitch 5120 (/4 1280) >[ 17548.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb1840] >[ 17548.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb1840] width 1280 pitch 5120 (/4 1280) >[ 17548.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608cc0] >[ 17548.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608cc0] width 1280 pitch 5120 (/4 1280) >[ 17548.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb1840] >[ 17548.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb1840] width 1280 pitch 5120 (/4 1280) >[ 17548.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5608cc0] >[ 17548.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5608cc0] width 1280 pitch 5120 (/4 1280) >[ 17550.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fe300] >[ 17550.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fe300] width 1280 pitch 5120 (/4 1280) >[ 17570.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56426c0] >[ 17570.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56426c0] width 1280 pitch 5120 (/4 1280) >[ 17963.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17963.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17968.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5540] >[ 17968.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5540] width 1280 pitch 5120 (/4 1280) >[ 17969.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 17970.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 17970.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e5440] >[ 17970.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e5440] width 1280 pitch 5120 (/4 1280) >[ 17970.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561be40] >[ 17970.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561be40] width 1280 pitch 5120 (/4 1280) >[ 17970.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e5440] >[ 17970.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e5440] width 1280 pitch 5120 (/4 1280) >[ 17971.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561be40] >[ 17971.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561be40] width 1280 pitch 5120 (/4 1280) >[ 17971.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e5440] >[ 17971.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e5440] width 1280 pitch 5120 (/4 1280) >[ 17971.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561be40] >[ 17972.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561be40] width 1280 pitch 5120 (/4 1280) >[ 17973.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 17973.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 17973.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d4e30] >[ 17973.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d4e30] width 1280 pitch 5120 (/4 1280) >[ 17976.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b9b80] >[ 17976.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b9b80] width 1280 pitch 5120 (/4 1280) >[ 17977.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d4e30] >[ 17977.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d4e30] width 1280 pitch 5120 (/4 1280) >[ 17977.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b9b80] >[ 17977.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b9b80] width 1280 pitch 5120 (/4 1280) >[ 17977.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d4e30] >[ 17977.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d4e30] width 1280 pitch 5120 (/4 1280) >[ 17977.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b9b80] >[ 17977.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b9b80] width 1280 pitch 5120 (/4 1280) >[ 17978.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d4e30] >[ 17978.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d4e30] width 1280 pitch 5120 (/4 1280) >[ 17978.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55553f0] >[ 17978.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55553f0] width 1280 pitch 5120 (/4 1280) >[ 17978.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d4e30] >[ 17979.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d4e30] width 1280 pitch 5120 (/4 1280) >[ 17979.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55553f0] >[ 17979.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55553f0] width 1280 pitch 5120 (/4 1280) >[ 17979.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d4e30] >[ 17979.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d4e30] width 1280 pitch 5120 (/4 1280) >[ 17979.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55553f0] >[ 17980.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55553f0] width 1280 pitch 5120 (/4 1280) >[ 17980.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55f5980] >[ 17980.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55f5980] width 1280 pitch 5120 (/4 1280) >[ 17991.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f5d50] >[ 17991.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f5d50] width 1280 pitch 5120 (/4 1280) >[ 17991.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51f5d50] >[ 17991.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51f5d50] width 1280 pitch 5120 (/4 1280) >[ 17992.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bb7b0] >[ 17992.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bb7b0] width 1280 pitch 5120 (/4 1280) >[ 17992.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692fa70] >[ 17992.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692fa70] width 1280 pitch 5120 (/4 1280) >[ 17993.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 17993.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 17993.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55bb7b0] >[ 17993.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55bb7b0] width 1280 pitch 5120 (/4 1280) >[ 17994.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5621480] >[ 17994.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5621480] width 1280 pitch 5120 (/4 1280) >[ 17994.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 17994.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 17994.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5621480] >[ 17994.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5621480] width 1280 pitch 5120 (/4 1280) >[ 17994.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 17995.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 17995.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5621480] >[ 17995.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5621480] width 1280 pitch 5120 (/4 1280) >[ 17995.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fb80] >[ 17995.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fb80] width 1280 pitch 5120 (/4 1280) >[ 17996.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5623490] >[ 17996.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5623490] width 1280 pitch 5120 (/4 1280) >[ 17997.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563edd0] >[ 17997.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563edd0] width 1280 pitch 5120 (/4 1280) >[ 17997.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ab2c0] >[ 17997.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ab2c0] width 1280 pitch 5120 (/4 1280) >[ 18208.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6734c00] >[ 18208.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6734c00] width 1280 pitch 5120 (/4 1280) >[ 18208.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d38f0] >[ 18208.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d38f0] width 1280 pitch 5120 (/4 1280) >[ 18390.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695cbd0] >[ 18390.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695cbd0] width 1280 pitch 5120 (/4 1280) >[ 18390.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695b2f0] >[ 18390.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695b2f0] width 1280 pitch 5120 (/4 1280) >[ 18402.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6957080] >[ 18402.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6957080] width 1280 pitch 5120 (/4 1280) >[ 18402.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fe900] >[ 18403.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fe900] width 1280 pitch 5120 (/4 1280) >[ 18543.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67131c0] >[ 18543.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67131c0] width 1280 pitch 5120 (/4 1280) >[ 18543.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67131c0] >[ 18543.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67131c0] width 1280 pitch 5120 (/4 1280) >[ 18736.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6796df0] >[ 18737.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6796df0] width 1280 pitch 5120 (/4 1280) >[ 18737.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695f5f0] >[ 18737.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695f5f0] width 1280 pitch 5120 (/4 1280) >[ 18739.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695f5f0] >[ 18739.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695f5f0] width 1280 pitch 5120 (/4 1280) >[ 18740.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6959650] >[ 18740.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6959650] width 1280 pitch 5120 (/4 1280) >[ 18740.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x671caa0] >[ 18740.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x671caa0] width 1280 pitch 5120 (/4 1280) >[ 18740.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6959650] >[ 18740.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6959650] width 1280 pitch 5120 (/4 1280) >[ 18740.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x671caa0] >[ 18741.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x671caa0] width 1280 pitch 5120 (/4 1280) >[ 18741.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6959650] >[ 18741.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6959650] width 1280 pitch 5120 (/4 1280) >[ 18741.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x671caa0] >[ 18741.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x671caa0] width 1280 pitch 5120 (/4 1280) >[ 18741.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6959650] >[ 18742.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6959650] width 1280 pitch 5120 (/4 1280) >[ 18742.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x671caa0] >[ 18742.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x671caa0] width 1280 pitch 5120 (/4 1280) >[ 18742.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6959650] >[ 18742.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6959650] width 1280 pitch 5120 (/4 1280) >[ 18743.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55a8dd0] >[ 18743.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55a8dd0] width 1280 pitch 5120 (/4 1280) >[ 18757.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6796df0] >[ 18757.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6796df0] width 1280 pitch 5120 (/4 1280) >[ 18757.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6828f10] >[ 18757.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6828f10] width 1280 pitch 5120 (/4 1280) >[ 18757.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a370] >[ 18757.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a370] width 1280 pitch 5120 (/4 1280) >[ 18757.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5540] >[ 18757.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5540] width 1280 pitch 5120 (/4 1280) >[ 18765.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695dc70] >[ 18765.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695dc70] width 1280 pitch 5120 (/4 1280) >[ 18765.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68508c0] >[ 18765.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68508c0] width 1280 pitch 5120 (/4 1280) >[ 18765.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68509f0] >[ 18765.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68509f0] width 1280 pitch 5120 (/4 1280) >[ 18767.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68508c0] >[ 18767.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68508c0] width 1280 pitch 5120 (/4 1280) >[ 18786.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68769f0] >[ 18786.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68769f0] width 1280 pitch 5120 (/4 1280) >[ 18830.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925810] >[ 18830.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925810] width 1280 pitch 5120 (/4 1280) >[ 18834.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 18834.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 18834.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 18834.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 18834.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 18834.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 18834.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 18834.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 18834.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 18834.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 18834.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 18834.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 18839.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 18839.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 18839.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 18839.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 18839.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 18839.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 18839.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 18839.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 18839.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 18839.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 18843.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925810] >[ 18843.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925810] width 1280 pitch 5120 (/4 1280) >[ 18843.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 18843.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 18843.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925810] >[ 18843.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925810] width 1280 pitch 5120 (/4 1280) >[ 18843.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 18843.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 18843.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925810] >[ 18843.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925810] width 1280 pitch 5120 (/4 1280) >[ 19365.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ef910] >[ 19365.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ef910] width 1280 pitch 5120 (/4 1280) >[ 19366.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 19366.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 19366.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ef910] >[ 19366.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ef910] width 1280 pitch 5120 (/4 1280) >[ 19366.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 19367.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 19367.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68509f0] >[ 19367.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68509f0] width 1280 pitch 5120 (/4 1280) >[ 19367.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925810] >[ 19368.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925810] width 1280 pitch 5120 (/4 1280) >[ 19368.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68509f0] >[ 19368.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68509f0] width 1280 pitch 5120 (/4 1280) >[ 19368.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925810] >[ 19368.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925810] width 1280 pitch 5120 (/4 1280) >[ 19368.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68509f0] >[ 19369.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68509f0] width 1280 pitch 5120 (/4 1280) >[ 19369.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925810] >[ 19369.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925810] width 1280 pitch 5120 (/4 1280) >[ 19369.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68509f0] >[ 19369.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68509f0] width 1280 pitch 5120 (/4 1280) >[ 19369.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925810] >[ 19370.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925810] width 1280 pitch 5120 (/4 1280) >[ 19370.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 19371.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 19371.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ef910] >[ 19371.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ef910] width 1280 pitch 5120 (/4 1280) >[ 19372.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6872d40] >[ 19372.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6872d40] width 1280 pitch 5120 (/4 1280) >[ 19372.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880b80] >[ 19372.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880b80] width 1280 pitch 5120 (/4 1280) >[ 19444.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5564cd0] >[ 19444.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5564cd0] width 1280 pitch 5120 (/4 1280) >[ 19447.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5542440] >[ 19447.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5542440] width 1280 pitch 5120 (/4 1280) >[ 19472.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6827f90] >[ 19472.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6827f90] width 1280 pitch 5120 (/4 1280) >[ 19472.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6828250] >[ 19472.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6828250] width 1280 pitch 5120 (/4 1280) >[ 19474.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555a160] >[ 19474.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555a160] width 1280 pitch 5120 (/4 1280) >[ 19476.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555a160] >[ 19476.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555a160] width 1280 pitch 5120 (/4 1280) >[ 19490.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e9df0] >[ 19490.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e9df0] width 1280 pitch 5120 (/4 1280) >[ 19490.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687db40] >[ 19490.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687db40] width 1280 pitch 5120 (/4 1280) >[ 19490.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e9df0] >[ 19491.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e9df0] width 1280 pitch 5120 (/4 1280) >[ 19491.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687db40] >[ 19491.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687db40] width 1280 pitch 5120 (/4 1280) >[ 19491.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e9df0] >[ 19491.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e9df0] width 1280 pitch 5120 (/4 1280) >[ 19491.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687db40] >[ 19491.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687db40] width 1280 pitch 5120 (/4 1280) >[ 19499.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5564cd0] >[ 19499.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5564cd0] width 1280 pitch 5120 (/4 1280) >[ 19500.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5542440] >[ 19500.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5542440] width 1280 pitch 5120 (/4 1280) >[ 19571.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5264e00] >[ 19571.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5264e00] width 1280 pitch 5120 (/4 1280) >[ 19572.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68f1a40] >[ 19572.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68f1a40] width 1280 pitch 5120 (/4 1280) >[ 19572.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x551c860] >[ 19572.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x551c860] width 1280 pitch 5120 (/4 1280) >[ 19575.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561be40] >[ 19575.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561be40] width 1280 pitch 5120 (/4 1280) >[ 19576.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b00c0] >[ 19576.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b00c0] width 1280 pitch 5120 (/4 1280) >[ 19576.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561be40] >[ 19576.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561be40] width 1280 pitch 5120 (/4 1280) >[ 19576.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b00c0] >[ 19576.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b00c0] width 1280 pitch 5120 (/4 1280) >[ 19576.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561be40] >[ 19576.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561be40] width 1280 pitch 5120 (/4 1280) >[ 19576.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b00c0] >[ 19576.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b00c0] width 1280 pitch 5120 (/4 1280) >[ 19576.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561be40] >[ 19577.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561be40] width 1280 pitch 5120 (/4 1280) >[ 19577.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b00c0] >[ 19577.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b00c0] width 1280 pitch 5120 (/4 1280) >[ 19577.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68f1a40] >[ 19577.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68f1a40] width 1280 pitch 5120 (/4 1280) >[ 19578.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67186c0] >[ 19578.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67186c0] width 1280 pitch 5120 (/4 1280) >[ 19578.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382520] >[ 19578.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382520] width 1280 pitch 5120 (/4 1280) >[ 19585.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x561d520] >[ 19585.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x561d520] width 1280 pitch 5120 (/4 1280) >[ 19587.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382520] >[ 19587.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382520] width 1280 pitch 5120 (/4 1280) >[ 19587.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ccfc0] >[ 19587.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ccfc0] width 1280 pitch 5120 (/4 1280) >[ 19587.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382520] >[ 19587.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382520] width 1280 pitch 5120 (/4 1280) >[ 19587.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ccfc0] >[ 19588.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ccfc0] width 1280 pitch 5120 (/4 1280) >[ 19588.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382520] >[ 19588.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382520] width 1280 pitch 5120 (/4 1280) >[ 19588.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ccfc0] >[ 19588.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ccfc0] width 1280 pitch 5120 (/4 1280) >[ 19588.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382520] >[ 19589.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382520] width 1280 pitch 5120 (/4 1280) >[ 19591.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55730c0] >[ 19591.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55730c0] width 1280 pitch 5120 (/4 1280) >[ 19591.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a370] >[ 19591.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a370] width 1280 pitch 5120 (/4 1280) >[ 19697.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382700] >[ 19697.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382700] width 1280 pitch 5120 (/4 1280) >[ 19697.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68f1a40] >[ 19697.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68f1a40] width 1280 pitch 5120 (/4 1280) >[ 19796.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5cc0] >[ 19796.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5cc0] width 1280 pitch 5120 (/4 1280) >[ 19796.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5313df0] >[ 19796.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5313df0] width 1280 pitch 5120 (/4 1280) >[ 19807.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5382700] >[ 19807.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5382700] width 1280 pitch 5120 (/4 1280) >[ 19807.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55db2e0] >[ 19807.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55db2e0] width 1280 pitch 5120 (/4 1280) >[ 19876.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d57d0] >[ 19876.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d57d0] width 1280 pitch 5120 (/4 1280) >[ 19877.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7660] >[ 19877.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7660] width 1280 pitch 5120 (/4 1280) >[ 19877.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 19877.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 19877.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7660] >[ 19877.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7660] width 1280 pitch 5120 (/4 1280) >[ 19878.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c36c0] >[ 19878.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c36c0] width 1280 pitch 5120 (/4 1280) >[ 19878.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7660] >[ 19879.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7660] width 1280 pitch 5120 (/4 1280) >[ 19879.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679d280] >[ 19879.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679d280] width 1280 pitch 5120 (/4 1280) >[ 19879.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dc5a0] >[ 19880.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dc5a0] width 1280 pitch 5120 (/4 1280) >[ 19883.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dc5a0] >[ 19883.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dc5a0] width 1280 pitch 5120 (/4 1280) >[ 19883.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543f20] >[ 19884.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543f20] width 1280 pitch 5120 (/4 1280) >[ 19885.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a09a0] >[ 19885.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a09a0] width 1280 pitch 5120 (/4 1280) >[ 19885.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543f20] >[ 19885.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543f20] width 1280 pitch 5120 (/4 1280) >[ 19885.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dc5a0] >[ 19885.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dc5a0] width 1280 pitch 5120 (/4 1280) >[ 19885.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690f390] >[ 19885.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690f390] width 1280 pitch 5120 (/4 1280) >[ 19885.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6799510] >[ 19886.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6799510] width 1280 pitch 5120 (/4 1280) >[ 19886.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53817b0] >[ 19886.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53817b0] width 1280 pitch 5120 (/4 1280) >[ 19886.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a09a0] >[ 19886.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a09a0] width 1280 pitch 5120 (/4 1280) >[ 19886.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a09a0] >[ 19886.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a09a0] width 1280 pitch 5120 (/4 1280) >[ 19886.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a09a0] >[ 19886.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a09a0] width 1280 pitch 5120 (/4 1280) >[ 19886.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5381b50] >[ 19886.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5381b50] width 1280 pitch 5120 (/4 1280) >[ 19886.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a09a0] >[ 19886.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a09a0] width 1280 pitch 5120 (/4 1280) >[ 19886.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5381b50] >[ 19886.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5381b50] width 1280 pitch 5120 (/4 1280) >[ 19886.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a09a0] >[ 19886.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a09a0] width 1280 pitch 5120 (/4 1280) >[ 20374.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bf0a0] >[ 20374.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bf0a0] width 1280 pitch 5120 (/4 1280) >[ 20374.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561c80] >[ 20374.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561c80] width 1280 pitch 5120 (/4 1280) >[ 20375.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bf0a0] >[ 20375.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bf0a0] width 1280 pitch 5120 (/4 1280) >[ 20375.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bef00] >[ 20375.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bef00] width 1280 pitch 5120 (/4 1280) >[ 20376.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bef00] >[ 20376.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bef00] width 1280 pitch 5120 (/4 1280) >[ 20376.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bf0a0] >[ 20376.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bf0a0] width 1280 pitch 5120 (/4 1280) >[ 20377.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561c80] >[ 20377.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561c80] width 1280 pitch 5120 (/4 1280) >[ 20377.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5621d30] >[ 20377.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5621d30] width 1280 pitch 5120 (/4 1280) >[ 20411.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e8730] >[ 20411.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e8730] width 1280 pitch 5120 (/4 1280) >[ 20411.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758070] >[ 20411.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758070] width 1280 pitch 5120 (/4 1280) >[ 20411.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e8730] >[ 20411.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e8730] width 1280 pitch 5120 (/4 1280) >[ 20411.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758070] >[ 20411.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758070] width 1280 pitch 5120 (/4 1280) >[ 20411.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e8730] >[ 20411.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e8730] width 1280 pitch 5120 (/4 1280) >[ 20411.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758070] >[ 20411.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758070] width 1280 pitch 5120 (/4 1280) >[ 20411.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e8730] >[ 20411.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e8730] width 1280 pitch 5120 (/4 1280) >[ 20411.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758070] >[ 20411.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758070] width 1280 pitch 5120 (/4 1280) >[ 20411.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e5480] >[ 20411.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e5480] width 1280 pitch 5120 (/4 1280) >[ 20415.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68426d0] >[ 20415.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68426d0] width 1280 pitch 5120 (/4 1280) >[ 20415.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6843d10] >[ 20415.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6843d10] width 1280 pitch 5120 (/4 1280) >[ 20415.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68451c0] >[ 20415.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68451c0] width 1280 pitch 5120 (/4 1280) >[ 20415.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6843d10] >[ 20415.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6843d10] width 1280 pitch 5120 (/4 1280) >[ 20415.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6844f10] >[ 20415.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6844f10] width 1280 pitch 5120 (/4 1280) >[ 20415.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845f60] >[ 20415.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845f60] width 1280 pitch 5120 (/4 1280) >[ 20428.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x683ea10] >[ 20428.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x683ea10] width 1280 pitch 5120 (/4 1280) >[ 20428.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5600130] >[ 20428.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5600130] width 1280 pitch 5120 (/4 1280) >[ 20428.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e8730] >[ 20428.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e8730] width 1280 pitch 5120 (/4 1280) >[ 20432.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554f880] >[ 20432.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554f880] width 1280 pitch 5120 (/4 1280) >[ 20432.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e4d0] >[ 20432.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e4d0] width 1280 pitch 5120 (/4 1280) >[ 20432.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561c80] >[ 20432.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561c80] width 1280 pitch 5120 (/4 1280) >[ 20432.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554f880] >[ 20432.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554f880] width 1280 pitch 5120 (/4 1280) >[ 20432.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52bee20] >[ 20432.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52bee20] width 1280 pitch 5120 (/4 1280) >[ 20432.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e4d0] >[ 20432.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e4d0] width 1280 pitch 5120 (/4 1280) >[ 20432.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x683f9d0] >[ 20432.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x683f9d0] width 1280 pitch 5120 (/4 1280) >[ 20432.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561c80] >[ 20432.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561c80] width 1280 pitch 5120 (/4 1280) >[ 20432.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758070] >[ 20433.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758070] width 1280 pitch 5120 (/4 1280) >[ 20433.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5600130] >[ 20433.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5600130] width 1280 pitch 5120 (/4 1280) >[ 20433.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561c80] >[ 20433.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561c80] width 1280 pitch 5120 (/4 1280) >[ 20433.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758070] >[ 20433.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758070] width 1280 pitch 5120 (/4 1280) >[ 20434.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d8cb0] >[ 20434.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d8cb0] width 1280 pitch 5120 (/4 1280) >[ 20452.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845e40] >[ 20452.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845e40] width 1280 pitch 5120 (/4 1280) >[ 20452.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6896e90] >[ 20452.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6896e90] width 1280 pitch 5120 (/4 1280) >[ 20452.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e8730] >[ 20452.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e8730] width 1280 pitch 5120 (/4 1280) >[ 20452.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6896e90] >[ 20452.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6896e90] width 1280 pitch 5120 (/4 1280) >[ 20457.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31010] >[ 20457.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31010] width 1280 pitch 5120 (/4 1280) >[ 20532.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66b0130] >[ 20532.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66b0130] width 1280 pitch 5120 (/4 1280) >[ 20533.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20533.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20533.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20534.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20534.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20534.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20534.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5323780] >[ 20535.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5323780] width 1280 pitch 5120 (/4 1280) >[ 20535.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20535.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20535.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5323780] >[ 20535.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5323780] width 1280 pitch 5120 (/4 1280) >[ 20536.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20536.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20536.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5323780] >[ 20536.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5323780] width 1280 pitch 5120 (/4 1280) >[ 20536.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20537.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20537.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5323780] >[ 20537.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5323780] width 1280 pitch 5120 (/4 1280) >[ 20537.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20537.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20537.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c5990] >[ 20538.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c5990] width 1280 pitch 5120 (/4 1280) >[ 20538.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20539.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20539.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c5990] >[ 20539.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c5990] width 1280 pitch 5120 (/4 1280) >[ 20547.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20547.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20547.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66b0130] >[ 20547.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66b0130] width 1280 pitch 5120 (/4 1280) >[ 20563.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20563.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20563.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20563.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20564.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1b8a0] >[ 20564.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1b8a0] width 1280 pitch 5120 (/4 1280) >[ 20574.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bc8f0] >[ 20574.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bc8f0] width 1280 pitch 5120 (/4 1280) >[ 20579.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bc7f0] >[ 20579.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bc7f0] width 1280 pitch 5120 (/4 1280) >[ 20579.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bf5970] >[ 20579.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bf5970] width 1280 pitch 5120 (/4 1280) >[ 20580.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1b8a0] >[ 20580.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1b8a0] width 1280 pitch 5120 (/4 1280) >[ 20580.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20580.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20580.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1b8a0] >[ 20580.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1b8a0] width 1280 pitch 5120 (/4 1280) >[ 20608.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5379da0] >[ 20608.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5379da0] width 1280 pitch 5120 (/4 1280) >[ 20608.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c850] >[ 20608.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c850] width 1280 pitch 5120 (/4 1280) >[ 20608.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66b0130] >[ 20608.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66b0130] width 1280 pitch 5120 (/4 1280) >[ 20608.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280a980] >[ 20609.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280a980] width 1280 pitch 5120 (/4 1280) >[ 20609.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20609.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20609.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280a980] >[ 20609.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280a980] width 1280 pitch 5120 (/4 1280) >[ 20914.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5379da0] >[ 20914.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5379da0] width 1280 pitch 5120 (/4 1280) >[ 20914.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e5740] >[ 20914.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e5740] width 1280 pitch 5120 (/4 1280) >[ 20915.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6896700] >[ 20915.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6896700] width 1280 pitch 5120 (/4 1280) >[ 20915.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20916.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20916.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20916.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20916.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20916.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20916.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20917.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20917.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20917.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20917.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20918.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20918.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20918.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20918.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280a980] >[ 20919.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280a980] width 1280 pitch 5120 (/4 1280) >[ 20919.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x541b960] >[ 20919.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x541b960] width 1280 pitch 5120 (/4 1280) >[ 20919.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280a980] >[ 20919.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280a980] width 1280 pitch 5120 (/4 1280) >[ 20919.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x541b960] >[ 20920.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x541b960] width 1280 pitch 5120 (/4 1280) >[ 20920.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280a980] >[ 20920.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280a980] width 1280 pitch 5120 (/4 1280) >[ 20920.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x541b960] >[ 20920.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x541b960] width 1280 pitch 5120 (/4 1280) >[ 20921.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x280a980] >[ 20921.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x280a980] width 1280 pitch 5120 (/4 1280) >[ 20921.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20921.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20922.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66b0130] >[ 20922.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66b0130] width 1280 pitch 5120 (/4 1280) >[ 20922.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20923.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20923.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66b0130] >[ 20923.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66b0130] width 1280 pitch 5120 (/4 1280) >[ 20924.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20924.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20924.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66b0130] >[ 20924.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66b0130] width 1280 pitch 5120 (/4 1280) >[ 20924.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c850] >[ 20924.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c850] width 1280 pitch 5120 (/4 1280) >[ 20925.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66b0130] >[ 20925.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66b0130] width 1280 pitch 5120 (/4 1280) >[ 20927.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6896700] >[ 20927.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6896700] width 1280 pitch 5120 (/4 1280) >[ 20928.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5379da0] >[ 20929.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5379da0] width 1280 pitch 5120 (/4 1280) >[ 20929.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6896700] >[ 20929.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6896700] width 1280 pitch 5120 (/4 1280) >[ 20929.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5379da0] >[ 20929.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5379da0] width 1280 pitch 5120 (/4 1280) >[ 20929.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6896700] >[ 20930.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6896700] width 1280 pitch 5120 (/4 1280) >[ 20930.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5418b80] >[ 20930.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5418b80] width 1280 pitch 5120 (/4 1280) >[ 20930.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20931.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20931.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20931.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20931.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20931.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20931.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20932.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20932.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20932.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20932.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20933.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20933.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20933.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20934.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20934.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20934.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20934.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20934.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20935.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20935.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20935.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20935.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20935.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20936.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c850] >[ 20936.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c850] width 1280 pitch 5120 (/4 1280) >[ 20936.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c014c0] >[ 20937.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c014c0] width 1280 pitch 5120 (/4 1280) >[ 20937.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1b8a0] >[ 20937.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1b8a0] width 1280 pitch 5120 (/4 1280) >[ 20937.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c014c0] >[ 20937.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c014c0] width 1280 pitch 5120 (/4 1280) >[ 20937.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1b8a0] >[ 20938.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1b8a0] width 1280 pitch 5120 (/4 1280) >[ 20939.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c014c0] >[ 20939.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c014c0] width 1280 pitch 5120 (/4 1280) >[ 20939.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0a240] >[ 20939.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0a240] width 1280 pitch 5120 (/4 1280) >[ 20943.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20943.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20943.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5379da0] >[ 20943.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5379da0] width 1280 pitch 5120 (/4 1280) >[ 20943.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20943.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20944.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5379da0] >[ 20944.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5379da0] width 1280 pitch 5120 (/4 1280) >[ 20944.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20944.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20945.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5379da0] >[ 20945.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5379da0] width 1280 pitch 5120 (/4 1280) >[ 20945.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20945.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20945.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20945.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20945.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20946.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20946.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20946.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20946.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20946.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20946.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20946.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20947.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20947.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20947.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20947.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20947.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20947.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20948.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20948.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20948.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20948.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20948.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20948.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20949.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20949.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20949.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20949.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20949.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20949.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20950.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a8d0] >[ 20950.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a8d0] width 1280 pitch 5120 (/4 1280) >[ 20950.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20951.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20952.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18d90] >[ 20952.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18d90] width 1280 pitch 5120 (/4 1280) >[ 20952.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c014c0] >[ 20952.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c014c0] width 1280 pitch 5120 (/4 1280) >[ 20952.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18d90] >[ 20953.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18d90] width 1280 pitch 5120 (/4 1280) >[ 20953.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7c014c0] >[ 20953.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7c014c0] width 1280 pitch 5120 (/4 1280) >[ 20954.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c850] >[ 20954.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c850] width 1280 pitch 5120 (/4 1280) >[ 20954.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5216c80] >[ 20955.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5216c80] width 1280 pitch 5120 (/4 1280) >[ 20955.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c850] >[ 20955.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c850] width 1280 pitch 5120 (/4 1280) >[ 20955.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5216c80] >[ 20955.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5216c80] width 1280 pitch 5120 (/4 1280) >[ 20955.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c850] >[ 20955.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c850] width 1280 pitch 5120 (/4 1280) >[ 20955.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5216c80] >[ 20956.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5216c80] width 1280 pitch 5120 (/4 1280) >[ 20956.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0a240] >[ 20956.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0a240] width 1280 pitch 5120 (/4 1280) >[ 20956.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e8730] >[ 20957.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e8730] width 1280 pitch 5120 (/4 1280) >[ 20957.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67849b0] >[ 20957.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67849b0] width 1280 pitch 5120 (/4 1280) >[ 20957.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5561c80] >[ 20957.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5561c80] width 1280 pitch 5120 (/4 1280) >[ 20957.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e4d0] >[ 20958.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e4d0] width 1280 pitch 5120 (/4 1280) >[ 20958.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758070] >[ 20958.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758070] width 1280 pitch 5120 (/4 1280) >[ 20958.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682ad90] >[ 20959.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682ad90] width 1280 pitch 5120 (/4 1280) >[ 20959.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3758070] >[ 20959.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3758070] width 1280 pitch 5120 (/4 1280) >[ 20959.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d1980] >[ 20959.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d1980] width 1280 pitch 5120 (/4 1280) >[ 20965.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b84d0] >[ 20965.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b84d0] width 1280 pitch 5120 (/4 1280) >[ 20966.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6f830] >[ 20966.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6f830] width 1280 pitch 5120 (/4 1280) >[ 20966.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c32140] >[ 20966.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c32140] width 1280 pitch 5120 (/4 1280) >[ 20966.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5628a40] >[ 20966.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5628a40] width 1280 pitch 5120 (/4 1280) >[ 20966.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c32140] >[ 20966.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c32140] width 1280 pitch 5120 (/4 1280) >[ 20966.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54cb730] >[ 20966.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54cb730] width 1280 pitch 5120 (/4 1280) >[ 20968.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d3f90] >[ 20968.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d3f90] width 1280 pitch 5120 (/4 1280) >[ 20968.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20968.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20968.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d3f90] >[ 20968.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d3f90] width 1280 pitch 5120 (/4 1280) >[ 20968.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ff810] >[ 20969.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ff810] width 1280 pitch 5120 (/4 1280) >[ 20969.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d3f90] >[ 20969.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d3f90] width 1280 pitch 5120 (/4 1280) >[ 20969.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 20969.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 20970.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20970.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20970.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 20970.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 20970.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20970.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20970.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 20971.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 20971.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7beeb30] >[ 20971.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7beeb30] width 1280 pitch 5120 (/4 1280) >[ 20971.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a18bc0] >[ 20971.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a18bc0] width 1280 pitch 5120 (/4 1280) >[ 20972.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6791f40] >[ 20972.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6791f40] width 1280 pitch 5120 (/4 1280) >[ 20976.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5369660] >[ 20976.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5369660] width 1280 pitch 5120 (/4 1280) >[ 20977.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5600130] >[ 20977.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5600130] width 1280 pitch 5120 (/4 1280) >[ 20977.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5369660] >[ 20978.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5369660] width 1280 pitch 5120 (/4 1280) >[ 20978.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5600130] >[ 20978.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5600130] width 1280 pitch 5120 (/4 1280) >[ 21401.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69296b0] >[ 21401.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69296b0] width 1280 pitch 5120 (/4 1280) >[ 21401.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692a340] >[ 21401.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692a340] width 1280 pitch 5120 (/4 1280) >[ 21434.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54182c0] >[ 21434.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54182c0] width 1280 pitch 5120 (/4 1280) >[ 21434.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d1d90] >[ 21434.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d1d90] width 1280 pitch 5120 (/4 1280) >[ 21435.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cbcb0] >[ 21435.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cbcb0] width 1280 pitch 5120 (/4 1280) >[ 21435.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c5950] >[ 21435.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c5950] width 1280 pitch 5120 (/4 1280) >[ 21435.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cbcb0] >[ 21435.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cbcb0] width 1280 pitch 5120 (/4 1280) >[ 21435.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c5950] >[ 21435.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c5950] width 1280 pitch 5120 (/4 1280) >[ 21435.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cbcb0] >[ 21435.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cbcb0] width 1280 pitch 5120 (/4 1280) >[ 21673.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66bc4e0] >[ 21673.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66bc4e0] width 1280 pitch 5120 (/4 1280) >[ 21674.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b8030] >[ 21674.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b8030] width 1280 pitch 5120 (/4 1280) >[ 21674.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6892db0] >[ 21674.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6892db0] width 1280 pitch 5120 (/4 1280) >[ 21678.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b8030] >[ 21678.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b8030] width 1280 pitch 5120 (/4 1280) >[ 21678.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6892db0] >[ 21678.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6892db0] width 1280 pitch 5120 (/4 1280) >[ 21678.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b8030] >[ 21678.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b8030] width 1280 pitch 5120 (/4 1280) >[ 21678.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6892db0] >[ 21678.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6892db0] width 1280 pitch 5120 (/4 1280) >[ 21678.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51b8030] >[ 21678.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51b8030] width 1280 pitch 5120 (/4 1280) >[ 21679.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c5950] >[ 21679.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c5950] width 1280 pitch 5120 (/4 1280) >[ 21679.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6892db0] >[ 21679.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6892db0] width 1280 pitch 5120 (/4 1280) >[ 21679.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c5950] >[ 21679.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c5950] width 1280 pitch 5120 (/4 1280) >[ 21679.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6892db0] >[ 21679.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6892db0] width 1280 pitch 5120 (/4 1280) >[ 21679.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c5950] >[ 21679.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c5950] width 1280 pitch 5120 (/4 1280) >[ 21679.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6892db0] >[ 21679.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6892db0] width 1280 pitch 5120 (/4 1280) >[ 22231.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5426460] >[ 22231.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5426460] width 1280 pitch 5120 (/4 1280) >[ 22231.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a203d0] >[ 22231.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a203d0] width 1280 pitch 5120 (/4 1280) >[ 22234.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cb880] >[ 22234.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cb880] width 1280 pitch 5120 (/4 1280) >[ 22235.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22235.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22236.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22236.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22236.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22236.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22236.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22236.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22237.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22237.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22237.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22237.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22238.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22238.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22245.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22245.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22503.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22503.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22503.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5606f20] >[ 22503.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5606f20] width 1280 pitch 5120 (/4 1280) >[ 22503.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cb880] >[ 22503.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cb880] width 1280 pitch 5120 (/4 1280) >[ 22503.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22503.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22503.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22503.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22503.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5606f20] >[ 22503.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5606f20] width 1280 pitch 5120 (/4 1280) >[ 22504.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22504.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22504.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22504.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22504.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22504.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22504.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6847ae0] >[ 22504.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6847ae0] width 1280 pitch 5120 (/4 1280) >[ 22504.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22504.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22504.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5606f20] >[ 22504.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5606f20] width 1280 pitch 5120 (/4 1280) >[ 22504.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cb880] >[ 22504.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cb880] width 1280 pitch 5120 (/4 1280) >[ 22504.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22504.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22504.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cb880] >[ 22504.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cb880] width 1280 pitch 5120 (/4 1280) >[ 22504.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22504.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22504.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cb880] >[ 22504.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cb880] width 1280 pitch 5120 (/4 1280) >[ 22506.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22506.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22506.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6847ae0] >[ 22506.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6847ae0] width 1280 pitch 5120 (/4 1280) >[ 22506.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cb880] >[ 22506.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cb880] width 1280 pitch 5120 (/4 1280) >[ 22506.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6847ae0] >[ 22506.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6847ae0] width 1280 pitch 5120 (/4 1280) >[ 22506.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cb880] >[ 22506.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cb880] width 1280 pitch 5120 (/4 1280) >[ 22518.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cb880] >[ 22518.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cb880] width 1280 pitch 5120 (/4 1280) >[ 22518.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22518.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22519.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6847ae0] >[ 22519.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6847ae0] width 1280 pitch 5120 (/4 1280) >[ 22519.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22519.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22519.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22519.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22519.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22519.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22520.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22520.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22520.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22520.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22520.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22520.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22520.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22520.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22520.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22520.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22520.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679a5e0] >[ 22520.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679a5e0] width 1280 pitch 5120 (/4 1280) >[ 22520.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22520.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22520.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22520.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 22520.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538a0a0] >[ 22520.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538a0a0] width 1280 pitch 5120 (/4 1280) >[ 22520.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ba90] >[ 22520.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ba90] width 1280 pitch 5120 (/4 1280) >[ 23021.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23021.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23021.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb2b0] >[ 23021.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb2b0] width 1280 pitch 5120 (/4 1280) >[ 23021.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23022.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23022.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb2b0] >[ 23022.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb2b0] width 1280 pitch 5120 (/4 1280) >[ 23022.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23022.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23022.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb2b0] >[ 23022.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb2b0] width 1280 pitch 5120 (/4 1280) >[ 23023.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23023.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23023.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb2b0] >[ 23023.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb2b0] width 1280 pitch 5120 (/4 1280) >[ 23023.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23023.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23025.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb2b0] >[ 23025.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb2b0] width 1280 pitch 5120 (/4 1280) >[ 23026.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb480] >[ 23026.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb480] width 1280 pitch 5120 (/4 1280) >[ 23026.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb2b0] >[ 23026.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb2b0] width 1280 pitch 5120 (/4 1280) >[ 23026.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb480] >[ 23026.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb480] width 1280 pitch 5120 (/4 1280) >[ 23027.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb2b0] >[ 23027.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb2b0] width 1280 pitch 5120 (/4 1280) >[ 23027.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23027.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23027.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb480] >[ 23028.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb480] width 1280 pitch 5120 (/4 1280) >[ 23028.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23028.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23028.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb480] >[ 23029.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb480] width 1280 pitch 5120 (/4 1280) >[ 23029.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23029.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23029.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb480] >[ 23029.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb480] width 1280 pitch 5120 (/4 1280) >[ 23029.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23029.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23031.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eb480] >[ 23031.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eb480] width 1280 pitch 5120 (/4 1280) >[ 23031.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556f3e0] >[ 23031.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556f3e0] width 1280 pitch 5120 (/4 1280) >[ 23652.878] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 23652.902] (II) RADEON(0): Using hsync ranges from config file >[ 23652.903] (II) RADEON(0): Using vrefresh ranges from config file >[ 23652.903] (II) RADEON(0): Printing DDC gathered Modelines: >[ 23652.903] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 23652.903] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 23652.903] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 23652.903] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 23652.903] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 23741.395] (II) RADEON(0): RADEONSaveScreen(2) >[ 23741.406] (II) RADEON(0): RADEONSaveScreen(0) >[ 24290.190] (II) RADEON(0): RADEONSaveScreen(1) >[ 24321.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6726320] >[ 24321.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6726320] width 1280 pitch 5120 (/4 1280) >[ 24327.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd730] >[ 24327.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd730] width 1280 pitch 5120 (/4 1280) >[ 24328.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x293f300] >[ 24328.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x293f300] width 1280 pitch 5120 (/4 1280) >[ 24328.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24328.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24328.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x293f300] >[ 24328.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x293f300] width 1280 pitch 5120 (/4 1280) >[ 24328.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24328.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24328.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x293f300] >[ 24329.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x293f300] width 1280 pitch 5120 (/4 1280) >[ 24329.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd93c0] >[ 24329.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd93c0] width 1280 pitch 5120 (/4 1280) >[ 24329.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd93c0] >[ 24330.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd93c0] width 1280 pitch 5120 (/4 1280) >[ 24337.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556fc50] >[ 24337.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556fc50] width 1280 pitch 5120 (/4 1280) >[ 24338.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bf7b60] >[ 24338.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bf7b60] width 1280 pitch 5120 (/4 1280) >[ 24339.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24339.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24339.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24339.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24339.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1e800] >[ 24340.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1e800] width 1280 pitch 5120 (/4 1280) >[ 24340.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab440] >[ 24340.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab440] width 1280 pitch 5120 (/4 1280) >[ 24340.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab440] >[ 24340.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab440] width 1280 pitch 5120 (/4 1280) >[ 24341.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53cbc10] >[ 24341.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53cbc10] width 1280 pitch 5120 (/4 1280) >[ 24341.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24341.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24341.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab440] >[ 24341.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab440] width 1280 pitch 5120 (/4 1280) >[ 24341.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556fc50] >[ 24342.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556fc50] width 1280 pitch 5120 (/4 1280) >[ 24342.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd93c0] >[ 24342.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd93c0] width 1280 pitch 5120 (/4 1280) >[ 24342.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47024b0] >[ 24342.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47024b0] width 1280 pitch 5120 (/4 1280) >[ 24342.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24342.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24343.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47024b0] >[ 24343.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47024b0] width 1280 pitch 5120 (/4 1280) >[ 24343.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24343.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24343.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47024b0] >[ 24344.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47024b0] width 1280 pitch 5120 (/4 1280) >[ 24344.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24344.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24344.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab440] >[ 24345.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab440] width 1280 pitch 5120 (/4 1280) >[ 24345.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd93c0] >[ 24346.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd93c0] width 1280 pitch 5120 (/4 1280) >[ 24346.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556fc50] >[ 24346.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556fc50] width 1280 pitch 5120 (/4 1280) >[ 24346.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c367b0] >[ 24346.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c367b0] width 1280 pitch 5120 (/4 1280) >[ 24346.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24347.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24347.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c367b0] >[ 24347.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c367b0] width 1280 pitch 5120 (/4 1280) >[ 24347.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab440] >[ 24347.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab440] width 1280 pitch 5120 (/4 1280) >[ 24348.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556fc50] >[ 24348.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556fc50] width 1280 pitch 5120 (/4 1280) >[ 24348.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd93c0] >[ 24348.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd93c0] width 1280 pitch 5120 (/4 1280) >[ 24348.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54169a0] >[ 24348.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54169a0] width 1280 pitch 5120 (/4 1280) >[ 24349.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24349.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24349.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54169a0] >[ 24349.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54169a0] width 1280 pitch 5120 (/4 1280) >[ 24349.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24350.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24350.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54169a0] >[ 24350.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54169a0] width 1280 pitch 5120 (/4 1280) >[ 24351.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab440] >[ 24351.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab440] width 1280 pitch 5120 (/4 1280) >[ 24351.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd93c0] >[ 24351.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd93c0] width 1280 pitch 5120 (/4 1280) >[ 24351.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556fc50] >[ 24351.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556fc50] width 1280 pitch 5120 (/4 1280) >[ 24352.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ca70] >[ 24352.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ca70] width 1280 pitch 5120 (/4 1280) >[ 24352.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24352.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24353.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ca70] >[ 24353.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ca70] width 1280 pitch 5120 (/4 1280) >[ 24353.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24353.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24353.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab440] >[ 24353.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab440] width 1280 pitch 5120 (/4 1280) >[ 24354.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556fc50] >[ 24354.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556fc50] width 1280 pitch 5120 (/4 1280) >[ 24354.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd93c0] >[ 24354.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd93c0] width 1280 pitch 5120 (/4 1280) >[ 24354.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47024b0] >[ 24355.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47024b0] width 1280 pitch 5120 (/4 1280) >[ 24355.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24355.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24356.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47024b0] >[ 24356.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47024b0] width 1280 pitch 5120 (/4 1280) >[ 24356.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24356.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24356.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ec8e0] >[ 24357.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ec8e0] width 1280 pitch 5120 (/4 1280) >[ 24361.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6898bd0] >[ 24361.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6898bd0] width 1280 pitch 5120 (/4 1280) >[ 24362.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6894ed0] >[ 24362.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6894ed0] width 1280 pitch 5120 (/4 1280) >[ 24362.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24362.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24362.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 24363.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 24363.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24363.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24363.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 24363.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 24363.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5613bb0] >[ 24363.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5613bb0] width 1280 pitch 5120 (/4 1280) >[ 24364.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24365.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24365.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5421d00] >[ 24365.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5421d00] width 1280 pitch 5120 (/4 1280) >[ 24365.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6847cc0] >[ 24365.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6847cc0] width 1280 pitch 5120 (/4 1280) >[ 24365.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6793080] >[ 24365.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6793080] width 1280 pitch 5120 (/4 1280) >[ 24365.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c533b0] >[ 24365.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c533b0] width 1280 pitch 5120 (/4 1280) >[ 24365.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 24365.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 24365.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 24365.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 24365.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 24365.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 24369.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 24369.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 24369.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 24369.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 24369.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 24369.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 24369.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 24370.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 24370.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 24370.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 24370.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 24370.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 24370.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 24370.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 24372.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6793080] >[ 24372.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6793080] width 1280 pitch 5120 (/4 1280) >[ 24372.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 24372.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 24406.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d73a0] >[ 24406.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d73a0] width 1280 pitch 5120 (/4 1280) >[ 24406.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557c3c0] >[ 24406.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557c3c0] width 1280 pitch 5120 (/4 1280) >[ 24406.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d73a0] >[ 24406.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d73a0] width 1280 pitch 5120 (/4 1280) >[ 24406.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557c3c0] >[ 24406.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557c3c0] width 1280 pitch 5120 (/4 1280) >[ 25375.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d330] >[ 25375.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d330] width 1280 pitch 5120 (/4 1280) >[ 25375.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fe40] >[ 25375.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fe40] width 1280 pitch 5120 (/4 1280) >[ 25375.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ab30] >[ 25375.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ab30] width 1280 pitch 5120 (/4 1280) >[ 25375.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fe40] >[ 25375.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fe40] width 1280 pitch 5120 (/4 1280) >[ 25375.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fb1a0] >[ 25375.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fb1a0] width 1280 pitch 5120 (/4 1280) >[ 25375.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6898890] >[ 25375.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6898890] width 1280 pitch 5120 (/4 1280) >[ 25375.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ab30] >[ 25375.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ab30] width 1280 pitch 5120 (/4 1280) >[ 25375.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6898890] >[ 25375.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6898890] width 1280 pitch 5120 (/4 1280) >[ 25375.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fb1a0] >[ 25375.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fb1a0] width 1280 pitch 5120 (/4 1280) >[ 25375.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6898890] >[ 25376.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6898890] width 1280 pitch 5120 (/4 1280) >[ 25376.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66fb1a0] >[ 25376.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66fb1a0] width 1280 pitch 5120 (/4 1280) >[ 25377.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d620] >[ 25377.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d620] width 1280 pitch 5120 (/4 1280) >[ 25377.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66eed50] >[ 25377.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66eed50] width 1280 pitch 5120 (/4 1280) >[ 25378.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e35e0] >[ 25378.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e35e0] width 1280 pitch 5120 (/4 1280) >[ 25378.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d620] >[ 25378.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d620] width 1280 pitch 5120 (/4 1280) >[ 25378.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563b350] >[ 25378.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563b350] width 1280 pitch 5120 (/4 1280) >[ 25378.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d620] >[ 25378.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d620] width 1280 pitch 5120 (/4 1280) >[ 25378.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563b350] >[ 25378.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563b350] width 1280 pitch 5120 (/4 1280) >[ 25378.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563b350] >[ 25378.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563b350] width 1280 pitch 5120 (/4 1280) >[ 25378.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d620] >[ 25378.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d620] width 1280 pitch 5120 (/4 1280) >[ 25378.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563b350] >[ 25378.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563b350] width 1280 pitch 5120 (/4 1280) >[ 25378.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d620] >[ 25378.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d620] width 1280 pitch 5120 (/4 1280) >[ 25417.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ebdc0] >[ 25417.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ebdc0] width 1280 pitch 5120 (/4 1280) >[ 25417.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563b350] >[ 25417.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563b350] width 1280 pitch 5120 (/4 1280) >[ 25417.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ebdc0] >[ 25417.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ebdc0] width 1280 pitch 5120 (/4 1280) >[ 25417.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563b350] >[ 25417.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563b350] width 1280 pitch 5120 (/4 1280) >[ 25417.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6937070] >[ 25417.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6937070] width 1280 pitch 5120 (/4 1280) >[ 25417.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ebdc0] >[ 25417.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ebdc0] width 1280 pitch 5120 (/4 1280) >[ 25417.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6937070] >[ 25418.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6937070] width 1280 pitch 5120 (/4 1280) >[ 25418.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ebdc0] >[ 25418.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ebdc0] width 1280 pitch 5120 (/4 1280) >[ 25418.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563b350] >[ 25418.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563b350] width 1280 pitch 5120 (/4 1280) >[ 25418.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ef870] >[ 25418.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ef870] width 1280 pitch 5120 (/4 1280) >[ 25418.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563b350] >[ 25418.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563b350] width 1280 pitch 5120 (/4 1280) >[ 25429.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x680cbb0] >[ 25429.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x680cbb0] width 1280 pitch 5120 (/4 1280) >[ 25429.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c372a0] >[ 25430.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c372a0] width 1280 pitch 5120 (/4 1280) >[ 25430.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x680cbb0] >[ 25430.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x680cbb0] width 1280 pitch 5120 (/4 1280) >[ 25430.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c372a0] >[ 25430.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c372a0] width 1280 pitch 5120 (/4 1280) >[ 25430.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x680cbb0] >[ 25430.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x680cbb0] width 1280 pitch 5120 (/4 1280) >[ 25431.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672fe40] >[ 25431.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672fe40] width 1280 pitch 5120 (/4 1280) >[ 25431.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68355a0] >[ 25431.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68355a0] width 1280 pitch 5120 (/4 1280) >[ 25432.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c9a10] >[ 25432.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c9a10] width 1280 pitch 5120 (/4 1280) >[ 25432.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53679e0] >[ 25432.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53679e0] width 1280 pitch 5120 (/4 1280) >[ 25432.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c9a10] >[ 25432.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c9a10] width 1280 pitch 5120 (/4 1280) >[ 25432.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53679e0] >[ 25432.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53679e0] width 1280 pitch 5120 (/4 1280) >[ 25433.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c9a10] >[ 25433.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c9a10] width 1280 pitch 5120 (/4 1280) >[ 25433.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53679e0] >[ 25433.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53679e0] width 1280 pitch 5120 (/4 1280) >[ 25434.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ec2c0] >[ 25434.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ec2c0] width 1280 pitch 5120 (/4 1280) >[ 25434.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6792980] >[ 25434.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6792980] width 1280 pitch 5120 (/4 1280) >[ 25508.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66beb00] >[ 25508.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66beb00] width 1280 pitch 5120 (/4 1280) >[ 25509.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53618a0] >[ 25509.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53618a0] width 1280 pitch 5120 (/4 1280) >[ 25509.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66beb00] >[ 25509.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66beb00] width 1280 pitch 5120 (/4 1280) >[ 25509.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53618a0] >[ 25509.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53618a0] width 1280 pitch 5120 (/4 1280) >[ 25509.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66beb00] >[ 25510.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66beb00] width 1280 pitch 5120 (/4 1280) >[ 25510.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53618a0] >[ 25510.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53618a0] width 1280 pitch 5120 (/4 1280) >[ 25510.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66beb00] >[ 25510.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66beb00] width 1280 pitch 5120 (/4 1280) >[ 25510.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53618a0] >[ 25510.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53618a0] width 1280 pitch 5120 (/4 1280) >[ 25510.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66beb00] >[ 25510.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66beb00] width 1280 pitch 5120 (/4 1280) >[ 25510.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53618a0] >[ 25511.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53618a0] width 1280 pitch 5120 (/4 1280) >[ 25511.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66beb00] >[ 25511.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66beb00] width 1280 pitch 5120 (/4 1280) >[ 25511.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53618a0] >[ 25511.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53618a0] width 1280 pitch 5120 (/4 1280) >[ 25511.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ef870] >[ 25511.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ef870] width 1280 pitch 5120 (/4 1280) >[ 25515.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a3050] >[ 25515.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a3050] width 1280 pitch 5120 (/4 1280) >[ 25515.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53679e0] >[ 25515.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53679e0] width 1280 pitch 5120 (/4 1280) >[ 25516.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ec2c0] >[ 25516.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ec2c0] width 1280 pitch 5120 (/4 1280) >[ 25516.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53679e0] >[ 25516.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53679e0] width 1280 pitch 5120 (/4 1280) >[ 25517.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ec2c0] >[ 25517.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ec2c0] width 1280 pitch 5120 (/4 1280) >[ 25517.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53679e0] >[ 25517.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53679e0] width 1280 pitch 5120 (/4 1280) >[ 25517.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ec2c0] >[ 25517.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ec2c0] width 1280 pitch 5120 (/4 1280) >[ 25517.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4709600] >[ 25518.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4709600] width 1280 pitch 5120 (/4 1280) >[ 25518.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ec2c0] >[ 25518.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ec2c0] width 1280 pitch 5120 (/4 1280) >[ 25518.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4709600] >[ 25519.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4709600] width 1280 pitch 5120 (/4 1280) >[ 25519.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ec2c0] >[ 25519.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ec2c0] width 1280 pitch 5120 (/4 1280) >[ 25519.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4709600] >[ 25519.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4709600] width 1280 pitch 5120 (/4 1280) >[ 25519.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ec2c0] >[ 25519.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ec2c0] width 1280 pitch 5120 (/4 1280) >[ 25519.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4709600] >[ 25519.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4709600] width 1280 pitch 5120 (/4 1280) >[ 25521.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53679e0] >[ 25521.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53679e0] width 1280 pitch 5120 (/4 1280) >[ 25521.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ca140] >[ 25521.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ca140] width 1280 pitch 5120 (/4 1280) >[ 25749.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53c9a10] >[ 25749.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53c9a10] width 1280 pitch 5120 (/4 1280) >[ 25749.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e2a40] >[ 25749.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e2a40] width 1280 pitch 5120 (/4 1280) >[ 25749.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51877f0] >[ 25749.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51877f0] width 1280 pitch 5120 (/4 1280) >[ 25749.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e2a40] >[ 25749.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e2a40] width 1280 pitch 5120 (/4 1280) >[ 25781.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 25781.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 25788.265] [mi] EQ overflowing. Additional events will be discarded until existing events are processed. >[ 25788.274] >[ 25788.274] Backtrace: >[ 25788.620] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326] >[ 25788.621] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x55155b] >[ 25788.621] 2: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22] >[ 25788.630] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7fa3823b8000+0x60e4) [0x7fa3823be0e4] >[ 25788.630] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817] >[ 25788.630] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00] >[ 25788.630] 6: /lib64/libpthread.so.0 (0x3da0a00000+0xefe0) [0x3da0a0efe0] >[ 25788.630] 7: /lib64/libc.so.6 (0x3da0600000+0x8e03b) [0x3da068e03b] >[ 25788.631] 8: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7fa382816000+0xa553b) [0x7fa3828bb53b] >[ 25788.631] 9: /usr/lib64/xorg/modules/libexa.so (0x7fa381de2000+0x5a7b) [0x7fa381de7a7b] >[ 25788.631] 10: /usr/lib64/xorg/modules/libexa.so (0x7fa381de2000+0x7f30) [0x7fa381de9f30] >[ 25788.631] 11: /usr/lib64/xorg/modules/libexa.so (0x7fa381de2000+0x11ed8) [0x7fa381df3ed8] >[ 25788.631] 12: /usr/lib64/xorg/modules/libexa.so (0x7fa381de2000+0xe828) [0x7fa381df0828] >[ 25788.631] 13: /usr/bin/Xorg (0x400000+0x102019) [0x502019] >[ 25788.631] 14: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74] >[ 25788.631] 15: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a] >[ 25788.631] 16: /usr/bin/Xorg (0x400000+0x23475) [0x423475] >[ 25788.631] 17: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3da0621735] >[ 25788.631] 18: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d] >[ 25788.631] >[ 25788.631] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack. >[ 25788.631] [mi] mieq is *NOT* the cause. It is a victim. >[ 25788.698] [mi] Increasing EQ size to 512 to prevent dropped events. >[ 25788.700] [mi] EQ processing has resumed after 49 dropped events. >[ 25788.700] [mi] This may be caused my a misbehaving driver monopolizing the server's resources. >[ 25795.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb18c0] >[ 25795.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb18c0] width 1280 pitch 5120 (/4 1280) >[ 25795.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f900] >[ 25795.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f900] width 1280 pitch 5120 (/4 1280) >[ 25795.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 25796.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 25796.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692f900] >[ 25796.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692f900] width 1280 pitch 5120 (/4 1280) >[ 25797.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5421d00] >[ 25797.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5421d00] width 1280 pitch 5120 (/4 1280) >[ 25797.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d73a0] >[ 25797.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d73a0] width 1280 pitch 5120 (/4 1280) >[ 25797.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5674b10] >[ 25797.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5674b10] width 1280 pitch 5120 (/4 1280) >[ 25802.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e29e0] >[ 25802.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e29e0] width 1280 pitch 5120 (/4 1280) >[ 25803.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 25803.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26140.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 26140.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 26140.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 26140.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26140.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 26140.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 26141.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 26141.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26141.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 26141.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 26141.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c6d0] >[ 26141.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c6d0] width 1280 pitch 5120 (/4 1280) >[ 26141.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67966e0] >[ 26141.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67966e0] width 1280 pitch 5120 (/4 1280) >[ 26141.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x556c6d0] >[ 26142.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x556c6d0] width 1280 pitch 5120 (/4 1280) >[ 26142.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7be5f50] >[ 26142.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7be5f50] width 1280 pitch 5120 (/4 1280) >[ 26142.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26142.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26142.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7be5f50] >[ 26142.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7be5f50] width 1280 pitch 5120 (/4 1280) >[ 26147.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26147.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26147.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66ef870] >[ 26148.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66ef870] width 1280 pitch 5120 (/4 1280) >[ 26148.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26148.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26148.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 26148.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 26148.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26148.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26149.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 26149.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 26149.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26149.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26149.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 26149.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 26149.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26149.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26149.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 26149.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 26149.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26149.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26150.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 26150.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 26150.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 26150.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 26150.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 26151.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 26151.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 26151.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 26152.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26152.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26152.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26153.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26153.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26153.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26153.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26153.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26153.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26153.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26153.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 26153.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 26153.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 26154.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26154.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 26154.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 26154.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 26154.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26154.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 26155.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 26155.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 26155.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26155.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 26155.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 26155.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 26155.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26155.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 26155.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 26155.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 26156.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26156.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406710] >[ 26156.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406710] width 1280 pitch 5120 (/4 1280) >[ 26156.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ddec0] >[ 26156.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ddec0] width 1280 pitch 5120 (/4 1280) >[ 26157.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786aa0] >[ 26157.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786aa0] width 1280 pitch 5120 (/4 1280) >[ 26157.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf56d0] >[ 26157.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf56d0] width 1280 pitch 5120 (/4 1280) >[ 26161.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c56950] >[ 26162.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c56950] width 1280 pitch 5120 (/4 1280) >[ 26162.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53590] >[ 26162.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53590] width 1280 pitch 5120 (/4 1280) >[ 26190.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf56d0] >[ 26190.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf56d0] width 1280 pitch 5120 (/4 1280) >[ 26190.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67966e0] >[ 26190.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67966e0] width 1280 pitch 5120 (/4 1280) >[ 26191.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 26191.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 26191.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67966e0] >[ 26191.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67966e0] width 1280 pitch 5120 (/4 1280) >[ 26193.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 26206.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 26207.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26207.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26207.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26207.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26207.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26207.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26208.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26208.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26208.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26208.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26208.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26208.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26208.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26208.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26208.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26208.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26208.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26208.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26208.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26208.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26208.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26209.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26210.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3479cc0] >[ 26210.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3479cc0] width 1280 pitch 5120 (/4 1280) >[ 26210.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3466d80] >[ 26210.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3466d80] width 1280 pitch 5120 (/4 1280) >[ 26211.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 26211.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 26211.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 26211.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 26211.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26211.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26211.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 26211.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 26212.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26212.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26212.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 26212.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 26212.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d13fa0] >[ 26212.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d13fa0] width 1280 pitch 5120 (/4 1280) >[ 26212.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26212.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26213.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26213.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26213.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26213.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26213.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26213.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26213.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26213.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26213.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26213.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26214.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26214.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26214.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26214.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26214.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26214.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26214.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26214.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26214.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26214.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26214.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26214.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26214.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26215.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26215.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26215.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26215.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26215.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26216.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26216.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26216.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26216.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26216.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26217.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26217.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26217.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26217.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26217.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26217.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26217.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26217.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26217.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26217.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26218.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26218.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26218.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26218.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26218.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26218.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26219.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26219.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26219.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26219.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26219.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26219.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26219.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26219.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26219.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26219.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26220.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26220.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26220.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26227.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26227.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26236.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26236.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26243.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51c8080] >[ 26243.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51c8080] width 1280 pitch 5120 (/4 1280) >[ 26244.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26244.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26244.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51c8080] >[ 26244.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51c8080] width 1280 pitch 5120 (/4 1280) >[ 26244.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26244.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26244.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb18c0] >[ 26244.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb18c0] width 1280 pitch 5120 (/4 1280) >[ 26245.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67966e0] >[ 26245.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67966e0] width 1280 pitch 5120 (/4 1280) >[ 26245.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a100] >[ 26245.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a100] width 1280 pitch 5120 (/4 1280) >[ 26246.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26246.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26246.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26246.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26246.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26246.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26246.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26246.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26246.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26246.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26246.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26246.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26247.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26247.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26247.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26247.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26247.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26247.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26247.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26247.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26247.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26247.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26247.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26247.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26248.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26248.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26248.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26248.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26248.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26248.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26248.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26248.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26248.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26249.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26249.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26249.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26251.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 26251.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 26251.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4737f10] >[ 26251.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4737f10] width 1280 pitch 5120 (/4 1280) >[ 26251.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51ea3b0] >[ 26251.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51ea3b0] width 1280 pitch 5120 (/4 1280) >[ 26252.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26252.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26252.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26252.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26253.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26253.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26253.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26253.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26253.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26253.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26254.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26254.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26254.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26254.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26254.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26254.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26254.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26254.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26254.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26254.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26254.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26254.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26256.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26256.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26256.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26256.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26256.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26256.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26257.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26257.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26257.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26257.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26257.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26257.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26258.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 26258.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 26258.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 26258.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 26260.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 26260.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 26260.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3446400] >[ 26260.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3446400] width 1280 pitch 5120 (/4 1280) >[ 26260.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 26260.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 26260.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3446400] >[ 26260.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3446400] width 1280 pitch 5120 (/4 1280) >[ 26260.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 26260.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 26260.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3446400] >[ 26260.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3446400] width 1280 pitch 5120 (/4 1280) >[ 26260.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 26260.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 26260.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3446400] >[ 26260.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3446400] width 1280 pitch 5120 (/4 1280) >[ 26260.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 26260.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 26260.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3446400] >[ 26260.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3446400] width 1280 pitch 5120 (/4 1280) >[ 26260.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 26261.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 26261.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3446400] >[ 26261.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3446400] width 1280 pitch 5120 (/4 1280) >[ 26261.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3446df0] >[ 26261.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3446df0] width 1280 pitch 5120 (/4 1280) >[ 26261.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26261.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26261.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26261.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26262.973] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 26262.973] (II) RADEON(0): Using hsync ranges from config file >[ 26262.973] (II) RADEON(0): Using vrefresh ranges from config file >[ 26262.973] (II) RADEON(0): Printing DDC gathered Modelines: >[ 26262.974] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 26262.974] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 26262.974] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 26262.974] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 26262.974] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 26275.231] (II) AIGLX: Suspending AIGLX clients for VT switch >[ 26275.307] (II) RADEON(0): RADEONLeaveVT_KMS >[ 26275.403] (II) RADEON(0): Ok, leaving now... >[ 26284.871] (II) AIGLX: Resuming AIGLX clients after VT switch >[ 26284.871] (II) RADEON(0): RADEONEnterVT_KMS >[ 26285.188] (II) RADEON(0): EDID vendor "ENC", prod id 6199 >[ 26285.188] (II) RADEON(0): Using hsync ranges from config file >[ 26285.188] (II) RADEON(0): Using vrefresh ranges from config file >[ 26285.188] (II) RADEON(0): Printing DDC gathered Modelines: >[ 26285.188] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 26285.188] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 26285.188] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 26285.188] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 26285.188] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 26285.207] (II) RADEON(0): RADEONSaveScreen(2) >[ 26292.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67966e0] >[ 26292.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67966e0] width 1280 pitch 5120 (/4 1280) >[ 26321.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26321.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26321.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26321.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26321.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26322.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26322.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26322.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26322.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26322.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26326.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26326.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26326.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26326.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26326.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26326.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26326.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26326.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26326.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26326.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26327.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26327.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26327.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26327.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26327.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26327.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26327.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26327.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26327.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26327.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26327.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 26327.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 26340.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 26340.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 26340.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26340.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26340.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26340.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26340.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d13fa0] >[ 26340.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d13fa0] width 1280 pitch 5120 (/4 1280) >[ 26340.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 26340.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 26340.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 26340.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 26340.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 26340.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 26340.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26341.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26341.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67aca60] >[ 26341.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67aca60] width 1280 pitch 5120 (/4 1280) >[ 26341.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 26341.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 26341.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5613bb0] >[ 26341.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5613bb0] width 1280 pitch 5120 (/4 1280) >[ 26341.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ca140] >[ 26341.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ca140] width 1280 pitch 5120 (/4 1280) >[ 26341.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7be5f50] >[ 26341.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7be5f50] width 1280 pitch 5120 (/4 1280) >[ 26341.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26341.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26341.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7be5f50] >[ 26341.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7be5f50] width 1280 pitch 5120 (/4 1280) >[ 26341.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 26341.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 26343.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d160] >[ 26343.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d160] width 1280 pitch 5120 (/4 1280) >[ 26343.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6782950] >[ 26343.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6782950] width 1280 pitch 5120 (/4 1280) >[ 26343.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3447250] >[ 26343.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3447250] width 1280 pitch 5120 (/4 1280) >[ 26343.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6782950] >[ 26343.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6782950] width 1280 pitch 5120 (/4 1280) >[ 26343.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf56d0] >[ 26343.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf56d0] width 1280 pitch 5120 (/4 1280) >[ 26344.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26344.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26344.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6723010] >[ 26344.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6723010] width 1280 pitch 5120 (/4 1280) >[ 26344.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26344.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26345.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6723010] >[ 26345.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6723010] width 1280 pitch 5120 (/4 1280) >[ 26345.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 26345.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 26346.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560d2a0] >[ 26346.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560d2a0] width 1280 pitch 5120 (/4 1280) >[ 26346.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ca140] >[ 26346.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ca140] width 1280 pitch 5120 (/4 1280) >[ 26348.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 26348.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 26348.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947f0] >[ 26348.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947f0] width 1280 pitch 5120 (/4 1280) >[ 26348.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51ea3b0] >[ 26348.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51ea3b0] width 1280 pitch 5120 (/4 1280) >[ 26348.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ebce0] >[ 26348.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ebce0] width 1280 pitch 5120 (/4 1280) >[ 26349.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e78d0] >[ 26349.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e78d0] width 1280 pitch 5120 (/4 1280) >[ 26349.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736db0] >[ 26349.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736db0] width 1280 pitch 5120 (/4 1280) >[ 26349.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x291db10] >[ 26349.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x291db10] width 1280 pitch 5120 (/4 1280) >[ 26350.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e78d0] >[ 26350.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e78d0] width 1280 pitch 5120 (/4 1280) >[ 26350.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51ea3b0] >[ 26350.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51ea3b0] width 1280 pitch 5120 (/4 1280) >[ 26350.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68e78d0] >[ 26350.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68e78d0] width 1280 pitch 5120 (/4 1280) >[ 26350.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51ea3b0] >[ 26350.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51ea3b0] width 1280 pitch 5120 (/4 1280) >[ 26350.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3486540] >[ 26350.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3486540] width 1280 pitch 5120 (/4 1280) >[ 26350.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932d40] >[ 26350.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932d40] width 1280 pitch 5120 (/4 1280) >[ 26379.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3458960] >[ 26379.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3458960] width 1280 pitch 5120 (/4 1280) >[ 26384.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ff070] >[ 26384.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ff070] width 1280 pitch 5120 (/4 1280) >[ 26399.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c770] >[ 26399.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c770] width 1280 pitch 5120 (/4 1280) >[ 26419.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678f200] >[ 26419.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678f200] width 1280 pitch 5120 (/4 1280) >[ 26419.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6793800] >[ 26419.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6793800] width 1280 pitch 5120 (/4 1280) >[ 26419.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3458900] >[ 26419.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3458900] width 1280 pitch 5120 (/4 1280) >[ 26419.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c9c0] >[ 26419.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c9c0] width 1280 pitch 5120 (/4 1280) >[ 26433.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932620] >[ 26433.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932620] width 1280 pitch 5120 (/4 1280) >[ 26437.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ccf80] >[ 26437.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ccf80] width 1280 pitch 5120 (/4 1280) >[ 26439.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51daac0] >[ 26439.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51daac0] width 1280 pitch 5120 (/4 1280) >[ 26835.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51e7b20] >[ 26835.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51e7b20] width 1280 pitch 5120 (/4 1280) >[ 26835.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6899270] >[ 26835.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6899270] width 1280 pitch 5120 (/4 1280) >[ 26835.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51e7b20] >[ 26835.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51e7b20] width 1280 pitch 5120 (/4 1280) >[ 26835.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51e7b20] >[ 26835.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51e7b20] width 1280 pitch 5120 (/4 1280) >[ 26835.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x436ae70] >[ 26835.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x436ae70] width 1280 pitch 5120 (/4 1280) >[ 26837.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690a250] >[ 26837.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690a250] width 1280 pitch 5120 (/4 1280) >[ 26837.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6899270] >[ 26837.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6899270] width 1280 pitch 5120 (/4 1280) >[ 26837.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690a250] >[ 26837.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690a250] width 1280 pitch 5120 (/4 1280) >[ 26837.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6793800] >[ 26837.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6793800] width 1280 pitch 5120 (/4 1280) >[ 26837.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690a250] >[ 26837.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690a250] width 1280 pitch 5120 (/4 1280) >[ 26838.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690a250] >[ 26838.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690a250] width 1280 pitch 5120 (/4 1280) >[ 26839.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6899270] >[ 26839.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6899270] width 1280 pitch 5120 (/4 1280) >[ 26853.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66dc1e0] >[ 26853.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66dc1e0] width 1280 pitch 5120 (/4 1280) >[ 26853.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66dc370] >[ 26853.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66dc370] width 1280 pitch 5120 (/4 1280) >[ 26853.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6792f80] >[ 26853.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6792f80] width 1280 pitch 5120 (/4 1280) >[ 26853.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687a480] >[ 26853.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687a480] width 1280 pitch 5120 (/4 1280) >[ 26853.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56751f0] >[ 26853.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56751f0] width 1280 pitch 5120 (/4 1280) >[ 26853.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687a480] >[ 26854.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687a480] width 1280 pitch 5120 (/4 1280) >[ 26855.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6793800] >[ 26855.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6793800] width 1280 pitch 5120 (/4 1280) >[ 26855.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690a250] >[ 26855.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690a250] width 1280 pitch 5120 (/4 1280) >[ 26855.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6899270] >[ 26855.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6899270] width 1280 pitch 5120 (/4 1280) >[ 26855.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6793800] >[ 26855.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6793800] width 1280 pitch 5120 (/4 1280) >[ 26855.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6899270] >[ 26855.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6899270] width 1280 pitch 5120 (/4 1280) >[ 26855.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6793800] >[ 26855.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6793800] width 1280 pitch 5120 (/4 1280) >[ 26855.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6899270] >[ 26855.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6899270] width 1280 pitch 5120 (/4 1280) >[ 26855.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6793800] >[ 26855.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6793800] width 1280 pitch 5120 (/4 1280) >[ 26872.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5177ca0] >[ 26872.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5177ca0] width 1280 pitch 5120 (/4 1280) >[ 26872.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a03670] >[ 26872.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a03670] width 1280 pitch 5120 (/4 1280) >[ 26872.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5458590] >[ 26872.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5458590] width 1280 pitch 5120 (/4 1280) >[ 26892.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d9000] >[ 26892.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d9000] width 1280 pitch 5120 (/4 1280) >[ 26896.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fe370] >[ 26896.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fe370] width 1280 pitch 5120 (/4 1280) >[ 26896.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393e20] >[ 26896.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393e20] width 1280 pitch 5120 (/4 1280) >[ 26896.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6792f80] >[ 26896.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6792f80] width 1280 pitch 5120 (/4 1280) >[ 26897.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51e3cf0] >[ 26897.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51e3cf0] width 1280 pitch 5120 (/4 1280) >[ 26904.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672e60] >[ 26904.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672e60] width 1280 pitch 5120 (/4 1280) >[ 26904.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672e60] >[ 26904.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672e60] width 1280 pitch 5120 (/4 1280) >[ 26904.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x560cfa0] >[ 26904.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x560cfa0] width 1280 pitch 5120 (/4 1280) >[ 26904.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5672e60] >[ 26904.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5672e60] width 1280 pitch 5120 (/4 1280) >[ 26913.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66f9bb0] >[ 26913.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66f9bb0] width 1280 pitch 5120 (/4 1280) >[ 26914.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5453950] >[ 26914.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5453950] width 1280 pitch 5120 (/4 1280) >[ 26917.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5454220] >[ 26917.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5454220] width 1280 pitch 5120 (/4 1280) >[ 26921.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ff700] >[ 26921.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ff700] width 1280 pitch 5120 (/4 1280) >[ 26921.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5458b40] >[ 26921.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5458b40] width 1280 pitch 5120 (/4 1280) >[ 26921.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ff700] >[ 26921.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ff700] width 1280 pitch 5120 (/4 1280) >[ 26921.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5458b40] >[ 26921.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5458b40] width 1280 pitch 5120 (/4 1280) >[ 26921.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34586a0] >[ 26921.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34586a0] width 1280 pitch 5120 (/4 1280) >[ 26921.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520c810] >[ 26921.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520c810] width 1280 pitch 5120 (/4 1280) >[ 26922.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c56e0] >[ 26922.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c56e0] width 1280 pitch 5120 (/4 1280) >[ 26922.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4733940] >[ 26922.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4733940] width 1280 pitch 5120 (/4 1280) >[ 26922.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4733940] >[ 26922.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4733940] width 1280 pitch 5120 (/4 1280) >[ 26922.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947f0] >[ 26922.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947f0] width 1280 pitch 5120 (/4 1280) >[ 26922.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4733940] >[ 26922.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4733940] width 1280 pitch 5120 (/4 1280) >[ 26922.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947f0] >[ 26922.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947f0] width 1280 pitch 5120 (/4 1280) >[ 26922.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4733940] >[ 26922.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4733940] width 1280 pitch 5120 (/4 1280) >[ 26922.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947f0] >[ 26923.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947f0] width 1280 pitch 5120 (/4 1280) >[ 27000.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ff260] >[ 27000.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ff260] width 1280 pitch 5120 (/4 1280) >[ 27002.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x350c320] >[ 27003.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x350c320] width 1280 pitch 5120 (/4 1280) >[ 27008.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d21820] >[ 27009.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d21820] width 1280 pitch 5120 (/4 1280) >[ 27076.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5454180] >[ 27076.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5454180] width 1280 pitch 5120 (/4 1280) >[ 27077.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5504610] >[ 27077.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5504610] width 1280 pitch 5120 (/4 1280) >[ 27077.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x566ed60] >[ 27077.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x566ed60] width 1280 pitch 5120 (/4 1280) >[ 27077.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5504610] >[ 27077.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5504610] width 1280 pitch 5120 (/4 1280) >[ 27077.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e8a60] >[ 27077.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e8a60] width 1280 pitch 5120 (/4 1280) >[ 27077.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ff4f0] >[ 27077.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ff4f0] width 1280 pitch 5120 (/4 1280) >[ 27077.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x680b8a0] >[ 27077.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x680b8a0] width 1280 pitch 5120 (/4 1280) >[ 27078.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68177a0] >[ 27078.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68177a0] width 1280 pitch 5120 (/4 1280) >[ 27078.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3458600] >[ 27078.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3458600] width 1280 pitch 5120 (/4 1280) >[ 27078.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5504610] >[ 27078.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5504610] width 1280 pitch 5120 (/4 1280) >[ 27079.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5453cf0] >[ 27079.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5453cf0] width 1280 pitch 5120 (/4 1280) >[ 27079.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a28fd0] >[ 27079.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a28fd0] width 1280 pitch 5120 (/4 1280) >[ 27079.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68177a0] >[ 27079.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68177a0] width 1280 pitch 5120 (/4 1280) >[ 27079.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5504610] >[ 27079.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5504610] width 1280 pitch 5120 (/4 1280) >[ 27079.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5570340] >[ 27079.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5570340] width 1280 pitch 5120 (/4 1280) >[ 27079.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a28fd0] >[ 27080.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a28fd0] width 1280 pitch 5120 (/4 1280) >[ 27080.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a28fd0] >[ 27080.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a28fd0] width 1280 pitch 5120 (/4 1280) >[ 27080.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5504610] >[ 27080.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5504610] width 1280 pitch 5120 (/4 1280) >[ 27080.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a28fd0] >[ 27080.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a28fd0] width 1280 pitch 5120 (/4 1280) >[ 27080.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748f10] >[ 27081.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748f10] width 1280 pitch 5120 (/4 1280) >[ 27081.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5570340] >[ 27081.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5570340] width 1280 pitch 5120 (/4 1280) >[ 27099.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ed070] >[ 27099.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ed070] width 1280 pitch 5120 (/4 1280) >[ 27101.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687a070] >[ 27101.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687a070] width 1280 pitch 5120 (/4 1280) >[ 27101.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4d3f0] >[ 27101.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4d3f0] width 1280 pitch 5120 (/4 1280) >[ 27119.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3438580] >[ 27119.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3438580] width 1280 pitch 5120 (/4 1280) >[ 27342.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27342.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27342.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27342.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27343.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27343.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27343.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27343.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27343.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27343.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27343.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27343.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27344.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27344.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27344.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27344.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27344.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27344.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27344.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27344.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27345.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27345.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27345.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27345.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27345.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27345.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27346.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27346.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27346.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27346.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27346.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27346.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27346.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27346.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27346.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27347.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27347.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27347.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27347.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27347.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27348.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27348.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27348.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27348.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27348.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27348.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27348.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27348.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27348.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27349.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27349.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27349.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27349.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27350.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27350.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27350.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27350.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27350.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27350.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27350.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27353.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27353.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27353.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27353.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27353.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27353.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27353.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27353.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27358.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27358.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27359.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27359.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27359.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27359.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27359.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27359.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27359.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27359.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27360.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27360.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27360.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27360.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27360.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27360.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27360.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27360.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27360.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27360.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27366.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27366.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27367.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27367.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27371.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27371.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27389.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e490] >[ 27389.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e490] width 1280 pitch 5120 (/4 1280) >[ 27391.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3432730] >[ 27391.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3432730] width 1280 pitch 5120 (/4 1280) >[ 27391.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34326d0] >[ 27391.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34326d0] width 1280 pitch 5120 (/4 1280) >[ 27391.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3432850] >[ 27391.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3432850] width 1280 pitch 5120 (/4 1280) >[ 27394.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34329e0] >[ 27395.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34329e0] width 1280 pitch 5120 (/4 1280) >[ 27395.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f9980] >[ 27395.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f9980] width 1280 pitch 5120 (/4 1280) >[ 27395.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f9980] >[ 27395.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f9980] width 1280 pitch 5120 (/4 1280) >[ 27395.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34329e0] >[ 27395.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34329e0] width 1280 pitch 5120 (/4 1280) >[ 27415.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3421490] >[ 27415.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3421490] width 1280 pitch 5120 (/4 1280) >[ 27485.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27485.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27485.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27485.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27485.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27485.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27486.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27487.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27487.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27487.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27496.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27496.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27496.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27496.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27496.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fdf80] >[ 27496.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fdf80] width 1280 pitch 5120 (/4 1280) >[ 27496.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3430310] >[ 27496.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3430310] width 1280 pitch 5120 (/4 1280) >[ 27501.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27501.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27502.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27502.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27516.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27516.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27516.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27516.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27516.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27516.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27516.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27516.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27517.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27517.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27517.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27517.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27517.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27517.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27517.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27517.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27518.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27518.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27518.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27518.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27518.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27518.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27518.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27518.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27518.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27519.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27519.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27519.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27519.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27519.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27519.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27520.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27520.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27520.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27520.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27520.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27520.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27520.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27520.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27520.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27520.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27521.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27521.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27521.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27522.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27522.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27522.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27523.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27523.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6944110] >[ 27523.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6944110] width 1280 pitch 5120 (/4 1280) >[ 27523.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6948750] >[ 27523.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6948750] width 1280 pitch 5120 (/4 1280) >[ 27524.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27524.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27524.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3502f40] >[ 27524.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3502f40] width 1280 pitch 5120 (/4 1280) >[ 27524.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694b460] >[ 27524.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694b460] width 1280 pitch 5120 (/4 1280) >[ 27715.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27715.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27715.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6754bb0] >[ 27715.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6754bb0] width 1280 pitch 5120 (/4 1280) >[ 27715.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27715.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27715.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6754bb0] >[ 27715.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6754bb0] width 1280 pitch 5120 (/4 1280) >[ 27715.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27715.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27715.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6754bb0] >[ 27715.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6754bb0] width 1280 pitch 5120 (/4 1280) >[ 27715.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27715.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27716.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6722190] >[ 27716.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6722190] width 1280 pitch 5120 (/4 1280) >[ 27716.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3462290] >[ 27716.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3462290] width 1280 pitch 5120 (/4 1280) >[ 27716.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x550fed0] >[ 27716.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x550fed0] width 1280 pitch 5120 (/4 1280) >[ 27716.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3462290] >[ 27716.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3462290] width 1280 pitch 5120 (/4 1280) >[ 27716.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6754640] >[ 27717.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6754640] width 1280 pitch 5120 (/4 1280) >[ 27717.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6754640] >[ 27717.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6754640] width 1280 pitch 5120 (/4 1280) >[ 27721.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6722430] >[ 27721.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6722430] width 1280 pitch 5120 (/4 1280) >[ 27721.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6754bb0] >[ 27721.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6754bb0] width 1280 pitch 5120 (/4 1280) >[ 27721.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6690e60] >[ 27721.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6690e60] width 1280 pitch 5120 (/4 1280) >[ 27721.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6754bb0] >[ 27721.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6754bb0] width 1280 pitch 5120 (/4 1280) >[ 27721.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6690e60] >[ 27721.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6690e60] width 1280 pitch 5120 (/4 1280) >[ 27749.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471e5b0] >[ 27749.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471e5b0] width 1280 pitch 5120 (/4 1280) >[ 27749.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4720df0] >[ 27749.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4720df0] width 1280 pitch 5120 (/4 1280) >[ 27749.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27749.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27749.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471cef0] >[ 27749.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471cef0] width 1280 pitch 5120 (/4 1280) >[ 27749.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27749.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27749.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ced3d0] >[ 27749.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ced3d0] width 1280 pitch 5120 (/4 1280) >[ 27749.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27749.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27749.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ced3d0] >[ 27749.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ced3d0] width 1280 pitch 5120 (/4 1280) >[ 27752.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27752.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27752.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669f570] >[ 27752.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669f570] width 1280 pitch 5120 (/4 1280) >[ 27754.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34321a0] >[ 27754.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34321a0] width 1280 pitch 5120 (/4 1280) >[ 27754.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x79ff7f0] >[ 27754.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x79ff7f0] width 1280 pitch 5120 (/4 1280) >[ 27754.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471d090] >[ 27754.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471d090] width 1280 pitch 5120 (/4 1280) >[ 27754.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47246d0] >[ 27754.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47246d0] width 1280 pitch 5120 (/4 1280) >[ 27754.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471d090] >[ 27754.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471d090] width 1280 pitch 5120 (/4 1280) >[ 27760.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3434050] >[ 27760.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3434050] width 1280 pitch 5120 (/4 1280) >[ 27760.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51e9f80] >[ 27760.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51e9f80] width 1280 pitch 5120 (/4 1280) >[ 27760.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3433ed0] >[ 27760.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3433ed0] width 1280 pitch 5120 (/4 1280) >[ 27760.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b9c0] >[ 27760.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b9c0] width 1280 pitch 5120 (/4 1280) >[ 27766.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66955e0] >[ 27766.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66955e0] width 1280 pitch 5120 (/4 1280) >[ 27766.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6695410] >[ 27766.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6695410] width 1280 pitch 5120 (/4 1280) >[ 27766.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342a340] >[ 27766.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342a340] width 1280 pitch 5120 (/4 1280) >[ 27766.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6695790] >[ 27766.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6695790] width 1280 pitch 5120 (/4 1280) >[ 27766.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342a500] >[ 27766.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342a500] width 1280 pitch 5120 (/4 1280) >[ 27766.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6697100] >[ 27766.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6697100] width 1280 pitch 5120 (/4 1280) >[ 27766.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b860] >[ 27766.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b860] width 1280 pitch 5120 (/4 1280) >[ 27767.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66a8710] >[ 27767.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66a8710] width 1280 pitch 5120 (/4 1280) >[ 27767.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6767800] >[ 27767.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6767800] width 1280 pitch 5120 (/4 1280) >[ 27768.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6767800] >[ 27768.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6767800] width 1280 pitch 5120 (/4 1280) >[ 27768.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b860] >[ 27768.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b860] width 1280 pitch 5120 (/4 1280) >[ 27768.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6757a30] >[ 27768.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6757a30] width 1280 pitch 5120 (/4 1280) >[ 27768.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67673e0] >[ 27768.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67673e0] width 1280 pitch 5120 (/4 1280) >[ 27808.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51e9f80] >[ 27808.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51e9f80] width 1280 pitch 5120 (/4 1280) >[ 27808.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4724760] >[ 27808.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4724760] width 1280 pitch 5120 (/4 1280) >[ 27808.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4724760] >[ 27808.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4724760] width 1280 pitch 5120 (/4 1280) >[ 27808.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4724760] >[ 27808.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4724760] width 1280 pitch 5120 (/4 1280) >[ 27808.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51e9f80] >[ 27808.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51e9f80] width 1280 pitch 5120 (/4 1280) >[ 27809.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4724760] >[ 27809.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4724760] width 1280 pitch 5120 (/4 1280) >[ 27809.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4724760] >[ 27809.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4724760] width 1280 pitch 5120 (/4 1280) >[ 27967.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x350a310] >[ 27967.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x350a310] width 1280 pitch 5120 (/4 1280) >[ 27979.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5418140] >[ 27979.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5418140] width 1280 pitch 5120 (/4 1280) >[ 27979.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55348a0] >[ 27979.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55348a0] width 1280 pitch 5120 (/4 1280) >[ 27985.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68775f0] >[ 27985.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68775f0] width 1280 pitch 5120 (/4 1280) >[ 27985.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68775f0] >[ 27985.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68775f0] width 1280 pitch 5120 (/4 1280) >[ 27985.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e2eb0] >[ 27985.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e2eb0] width 1280 pitch 5120 (/4 1280) >[ 27985.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68775f0] >[ 27985.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68775f0] width 1280 pitch 5120 (/4 1280) >[ 27985.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67522a0] >[ 27985.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67522a0] width 1280 pitch 5120 (/4 1280) >[ 27986.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c1c0] >[ 27986.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c1c0] width 1280 pitch 5120 (/4 1280) >[ 27987.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66a5d10] >[ 27987.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66a5d10] width 1280 pitch 5120 (/4 1280) >[ 28010.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68775f0] >[ 28010.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68775f0] width 1280 pitch 5120 (/4 1280) >[ 28010.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c790] >[ 28010.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c790] width 1280 pitch 5120 (/4 1280) >[ 28010.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34de1d0] >[ 28010.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34de1d0] width 1280 pitch 5120 (/4 1280) >[ 28010.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676c790] >[ 28010.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676c790] width 1280 pitch 5120 (/4 1280) >[ 28010.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68775f0] >[ 28010.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68775f0] width 1280 pitch 5120 (/4 1280) >[ 28100.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1cf40] >[ 28100.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1cf40] width 1280 pitch 5120 (/4 1280) >[ 28100.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544c600] >[ 28100.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544c600] width 1280 pitch 5120 (/4 1280) >[ 28100.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53abc50] >[ 28100.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53abc50] width 1280 pitch 5120 (/4 1280) >[ 28100.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544b0f0] >[ 28100.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544b0f0] width 1280 pitch 5120 (/4 1280) >[ 28101.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544c6a0] >[ 28101.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544c6a0] width 1280 pitch 5120 (/4 1280) >[ 28101.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543f7d0] >[ 28102.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543f7d0] width 1280 pitch 5120 (/4 1280) >[ 28102.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669c200] >[ 28102.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669c200] width 1280 pitch 5120 (/4 1280) >[ 28102.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543f7d0] >[ 28102.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543f7d0] width 1280 pitch 5120 (/4 1280) >[ 28102.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669c200] >[ 28102.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669c200] width 1280 pitch 5120 (/4 1280) >[ 28102.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x543f7d0] >[ 28102.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x543f7d0] width 1280 pitch 5120 (/4 1280) >[ 28109.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669c200] >[ 28109.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669c200] width 1280 pitch 5120 (/4 1280) >[ 28109.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669c200] >[ 28110.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669c200] width 1280 pitch 5120 (/4 1280) >[ 28110.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544d220] >[ 28110.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544d220] width 1280 pitch 5120 (/4 1280) >[ 28110.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66a2820] >[ 28110.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66a2820] width 1280 pitch 5120 (/4 1280) >[ 28110.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669c200] >[ 28110.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669c200] width 1280 pitch 5120 (/4 1280) >[ 28110.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669c200] >[ 28110.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669c200] width 1280 pitch 5120 (/4 1280) >[ 28116.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b960] >[ 28116.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b960] width 1280 pitch 5120 (/4 1280) >[ 28116.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x538b960] >[ 28116.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x538b960] width 1280 pitch 5120 (/4 1280) >[ 28116.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x676f250] >[ 28116.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x676f250] width 1280 pitch 5120 (/4 1280) >[ 28116.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544b1a0] >[ 28116.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544b1a0] width 1280 pitch 5120 (/4 1280) >[ 28116.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669c200] >[ 28117.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669c200] width 1280 pitch 5120 (/4 1280) >[ 28338.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1ea40] >[ 28338.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1ea40] width 1280 pitch 5120 (/4 1280) >[ 28338.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64820] >[ 28338.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64820] width 1280 pitch 5120 (/4 1280) >[ 28338.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e64820] >[ 28338.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e64820] width 1280 pitch 5120 (/4 1280) >[ 28338.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e52890] >[ 28338.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e52890] width 1280 pitch 5120 (/4 1280) >[ 28338.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66a9ea0] >[ 28338.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66a9ea0] width 1280 pitch 5120 (/4 1280) >[ 28385.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66a8f10] >[ 28385.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66a8f10] width 1280 pitch 5120 (/4 1280) >[ 28385.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e104a0] >[ 28385.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e104a0] width 1280 pitch 5120 (/4 1280) >[ 28385.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e21d50] >[ 28385.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e21d50] width 1280 pitch 5120 (/4 1280) >[ 28385.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e21d50] >[ 28385.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e21d50] width 1280 pitch 5120 (/4 1280) >[ 28385.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342e890] >[ 28385.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342e890] width 1280 pitch 5120 (/4 1280) >[ 28420.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e5e90] >[ 28420.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e5e90] width 1280 pitch 5120 (/4 1280) >[ 28420.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1ea70] >[ 28420.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1ea70] width 1280 pitch 5120 (/4 1280) >[ 28420.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1ea70] >[ 28420.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1ea70] width 1280 pitch 5120 (/4 1280) >[ 28421.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342e630] >[ 28421.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342e630] width 1280 pitch 5120 (/4 1280) >[ 28421.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66999a0] >[ 28421.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66999a0] width 1280 pitch 5120 (/4 1280) >[ 28574.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5412ac0] >[ 28574.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5412ac0] width 1280 pitch 5120 (/4 1280) >[ 28574.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669bfd0] >[ 28574.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669bfd0] width 1280 pitch 5120 (/4 1280) >[ 28574.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669bfd0] >[ 28574.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669bfd0] width 1280 pitch 5120 (/4 1280) >[ 28574.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342f130] >[ 28574.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342f130] width 1280 pitch 5120 (/4 1280) >[ 28574.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5412ac0] >[ 28574.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5412ac0] width 1280 pitch 5120 (/4 1280) >[ 28588.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a09e0] >[ 28588.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a09e0] width 1280 pitch 5120 (/4 1280) >[ 28588.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53aaf10] >[ 28588.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53aaf10] width 1280 pitch 5120 (/4 1280) >[ 28588.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dd460] >[ 28588.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dd460] width 1280 pitch 5120 (/4 1280) >[ 28588.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5438bb0] >[ 28588.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5438bb0] width 1280 pitch 5120 (/4 1280) >[ 28638.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5452f10] >[ 28638.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5452f10] width 1280 pitch 5120 (/4 1280) >[ 28638.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342f140] >[ 28638.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342f140] width 1280 pitch 5120 (/4 1280) >[ 28638.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46de250] >[ 28638.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46de250] width 1280 pitch 5120 (/4 1280) >[ 28638.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53a0520] >[ 28638.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53a0520] width 1280 pitch 5120 (/4 1280) >[ 28638.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66a9540] >[ 28638.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66a9540] width 1280 pitch 5120 (/4 1280) >[ 28638.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66a9540] >[ 28638.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66a9540] width 1280 pitch 5120 (/4 1280) >[ 28658.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53fa140] >[ 28658.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53fa140] width 1280 pitch 5120 (/4 1280) >[ 28658.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b4e000] >[ 28658.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b4e000] width 1280 pitch 5120 (/4 1280) >[ 28658.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b4e000] >[ 28658.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b4e000] width 1280 pitch 5120 (/4 1280) >[ 28658.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b4e000] >[ 28658.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b4e000] width 1280 pitch 5120 (/4 1280) >[ 28658.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b4e000] >[ 28658.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b4e000] width 1280 pitch 5120 (/4 1280) >[ 28658.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53fa140] >[ 28658.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53fa140] width 1280 pitch 5120 (/4 1280) >[ 28662.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669be20] >[ 28662.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669be20] width 1280 pitch 5120 (/4 1280) >[ 28662.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6765e00] >[ 28662.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6765e00] width 1280 pitch 5120 (/4 1280) >[ 28662.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669be20] >[ 28662.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669be20] width 1280 pitch 5120 (/4 1280) >[ 28662.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6765e00] >[ 28662.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6765e00] width 1280 pitch 5120 (/4 1280) >[ 28662.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1e6c0] >[ 28662.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1e6c0] width 1280 pitch 5120 (/4 1280) >[ 28662.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669be20] >[ 28662.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669be20] width 1280 pitch 5120 (/4 1280) >[ 28673.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54541c0] >[ 28673.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54541c0] width 1280 pitch 5120 (/4 1280) >[ 28673.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1e6c0] >[ 28673.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1e6c0] width 1280 pitch 5120 (/4 1280) >[ 28673.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46de250] >[ 28673.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46de250] width 1280 pitch 5120 (/4 1280) >[ 28673.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53e19b0] >[ 28673.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53e19b0] width 1280 pitch 5120 (/4 1280) >[ 28673.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46de250] >[ 28673.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46de250] width 1280 pitch 5120 (/4 1280) >[ 28674.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1e6c0] >[ 28674.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1e6c0] width 1280 pitch 5120 (/4 1280) >[ 28674.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6691d30] >[ 28674.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6691d30] width 1280 pitch 5120 (/4 1280) >[ 28674.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1e6c0] >[ 28674.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1e6c0] width 1280 pitch 5120 (/4 1280) >[ 28674.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5414ac0] >[ 28674.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5414ac0] width 1280 pitch 5120 (/4 1280) >[ 28674.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53abf90] >[ 28675.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53abf90] width 1280 pitch 5120 (/4 1280) >[ 28675.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669ee90] >[ 28675.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669ee90] width 1280 pitch 5120 (/4 1280) >[ 28675.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669ee90] >[ 28675.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669ee90] width 1280 pitch 5120 (/4 1280) >[ 28675.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e1e6c0] >[ 28675.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e1e6c0] width 1280 pitch 5120 (/4 1280) >[ 28675.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67966e0] >[ 28675.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67966e0] width 1280 pitch 5120 (/4 1280) >[ 28675.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7be5f50] >[ 28675.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7be5f50] width 1280 pitch 5120 (/4 1280) >[ 28675.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0ce60] >[ 28675.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0ce60] width 1280 pitch 5120 (/4 1280) >[ 28697.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf56d0] >[ 28697.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf56d0] width 1280 pitch 5120 (/4 1280) >[ 28701.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37500b0] >[ 28701.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37500b0] width 1280 pitch 5120 (/4 1280) >[ 28701.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67966e0] >[ 28701.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67966e0] width 1280 pitch 5120 (/4 1280) >[ 28717.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6721c60] >[ 28717.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6721c60] width 1280 pitch 5120 (/4 1280) >[ 28766.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5212a30] >[ 28766.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5212a30] width 1280 pitch 5120 (/4 1280) >[ 28774.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e3290] >[ 28774.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e3290] width 1280 pitch 5120 (/4 1280) >[ 28774.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c7300] >[ 28774.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c7300] width 1280 pitch 5120 (/4 1280) >[ 28801.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51fda90] >[ 28801.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51fda90] width 1280 pitch 5120 (/4 1280) >[ 28801.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51d8290] >[ 28801.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51d8290] width 1280 pitch 5120 (/4 1280) >[ 28801.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a100] >[ 28801.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a100] width 1280 pitch 5120 (/4 1280) >[ 28801.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a19920] >[ 28801.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a19920] width 1280 pitch 5120 (/4 1280) >[ 28801.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7be5f50] >[ 28801.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7be5f50] width 1280 pitch 5120 (/4 1280) >[ 28801.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6770fa0] >[ 28802.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6770fa0] width 1280 pitch 5120 (/4 1280) >[ 28807.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528aec0] >[ 28807.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528aec0] width 1280 pitch 5120 (/4 1280) >[ 28808.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54c7300] >[ 28808.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54c7300] width 1280 pitch 5120 (/4 1280) >[ 28808.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x680a020] >[ 28808.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x680a020] width 1280 pitch 5120 (/4 1280) >[ 28821.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf56d0] >[ 28821.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf56d0] width 1280 pitch 5120 (/4 1280) >[ 28821.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6721c60] >[ 28821.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6721c60] width 1280 pitch 5120 (/4 1280) >[ 28821.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c567b0] >[ 28821.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c567b0] width 1280 pitch 5120 (/4 1280) >[ 28821.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 28821.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 28827.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e0f5a0] >[ 28827.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e0f5a0] width 1280 pitch 5120 (/4 1280) >[ 28828.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67667b0] >[ 28828.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67667b0] width 1280 pitch 5120 (/4 1280) >[ 28828.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53bc0] >[ 28828.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53bc0] width 1280 pitch 5120 (/4 1280) >[ 28835.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ab900] >[ 28835.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ab900] width 1280 pitch 5120 (/4 1280) >[ 28840.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5632180] >[ 28840.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5632180] width 1280 pitch 5120 (/4 1280) >[ 28847.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ab900] >[ 28847.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ab900] width 1280 pitch 5120 (/4 1280) >[ 28856.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3462780] >[ 28856.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3462780] width 1280 pitch 5120 (/4 1280) >[ 28911.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e19240] >[ 28911.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e19240] width 1280 pitch 5120 (/4 1280) >[ 29055.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x544e2a0] >[ 29055.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x544e2a0] width 1280 pitch 5120 (/4 1280) >[ 29055.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c0090] >[ 29055.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c0090] width 1280 pitch 5120 (/4 1280) >[ 29055.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a52a00] >[ 29055.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a52a00] width 1280 pitch 5120 (/4 1280) >[ 29055.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31010] >[ 29055.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31010] width 1280 pitch 5120 (/4 1280) >[ 29055.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c0090] >[ 29056.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c0090] width 1280 pitch 5120 (/4 1280) >[ 29056.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31010] >[ 29056.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31010] width 1280 pitch 5120 (/4 1280) >[ 29056.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x52c0090] >[ 29056.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x52c0090] width 1280 pitch 5120 (/4 1280) >[ 29056.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31010] >[ 29056.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31010] width 1280 pitch 5120 (/4 1280) >[ 29150.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845e20] >[ 29150.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845e20] width 1280 pitch 5120 (/4 1280) >[ 29150.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a979c0] >[ 29150.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a979c0] width 1280 pitch 5120 (/4 1280) >[ 29151.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845e20] >[ 29151.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845e20] width 1280 pitch 5120 (/4 1280) >[ 29151.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a979c0] >[ 29151.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a979c0] width 1280 pitch 5120 (/4 1280) >[ 29151.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845e20] >[ 29151.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845e20] width 1280 pitch 5120 (/4 1280) >[ 29151.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a979c0] >[ 29151.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a979c0] width 1280 pitch 5120 (/4 1280) >[ 29151.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845e20] >[ 29151.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845e20] width 1280 pitch 5120 (/4 1280) >[ 29151.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a979c0] >[ 29152.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a979c0] width 1280 pitch 5120 (/4 1280) >[ 29153.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bcecf0] >[ 29153.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bcecf0] width 1280 pitch 5120 (/4 1280) >[ 29153.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x520ef00] >[ 29153.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x520ef00] width 1280 pitch 5120 (/4 1280) >[ 29153.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693a240] >[ 29153.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693a240] width 1280 pitch 5120 (/4 1280) >[ 29153.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a979c0] >[ 29153.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a979c0] width 1280 pitch 5120 (/4 1280) >[ 29163.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 29163.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 29163.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669be20] >[ 29163.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669be20] width 1280 pitch 5120 (/4 1280) >[ 29163.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6965370] >[ 29163.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6965370] width 1280 pitch 5120 (/4 1280) >[ 29163.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x471b580] >[ 29163.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x471b580] width 1280 pitch 5120 (/4 1280) >[ 29163.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a0ce60] >[ 29163.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a0ce60] width 1280 pitch 5120 (/4 1280) >[ 29163.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x473da10] >[ 29163.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x473da10] width 1280 pitch 5120 (/4 1280) >[ 29170.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c56950] >[ 29170.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c56950] width 1280 pitch 5120 (/4 1280) >[ 29170.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c740] >[ 29170.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c740] width 1280 pitch 5120 (/4 1280) >[ 29170.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53caf10] >[ 29170.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53caf10] width 1280 pitch 5120 (/4 1280) >[ 29170.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e0f5a0] >[ 29170.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e0f5a0] width 1280 pitch 5120 (/4 1280) >[ 29170.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5281540] >[ 29170.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5281540] width 1280 pitch 5120 (/4 1280) >[ 29170.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56294d0] >[ 29170.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56294d0] width 1280 pitch 5120 (/4 1280) >[ 29170.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5281540] >[ 29170.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5281540] width 1280 pitch 5120 (/4 1280) >[ 29170.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x56294d0] >[ 29170.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x56294d0] width 1280 pitch 5120 (/4 1280) >[ 29180.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51c8080] >[ 29180.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51c8080] width 1280 pitch 5120 (/4 1280) >[ 29181.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29181.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29181.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29181.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29181.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29181.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29181.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29182.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29182.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29182.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29182.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29182.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29182.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29182.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29182.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29182.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29182.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29182.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29182.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29182.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29182.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29183.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29183.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29183.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29183.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29183.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29184.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29184.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29184.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29185.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29185.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29185.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29186.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29186.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29186.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29186.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29186.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29187.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29187.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29187.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29187.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54a6250] >[ 29187.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54a6250] width 1280 pitch 5120 (/4 1280) >[ 29187.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x352c360] >[ 29188.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x352c360] width 1280 pitch 5120 (/4 1280) >[ 29188.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 29188.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 29189.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a100] >[ 29189.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a100] width 1280 pitch 5120 (/4 1280) >[ 29189.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 29189.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 29189.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a100] >[ 29189.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a100] width 1280 pitch 5120 (/4 1280) >[ 29190.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 29190.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 29192.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a100] >[ 29192.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a100] width 1280 pitch 5120 (/4 1280) >[ 29192.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 29192.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 29192.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a100] >[ 29192.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a100] width 1280 pitch 5120 (/4 1280) >[ 29193.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 29193.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 29193.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x563a100] >[ 29193.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x563a100] width 1280 pitch 5120 (/4 1280) >[ 29193.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a1c0a0] >[ 29193.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a1c0a0] width 1280 pitch 5120 (/4 1280) >[ 29193.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5281540] >[ 29194.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5281540] width 1280 pitch 5120 (/4 1280) >[ 29194.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46e3290] >[ 29194.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46e3290] width 1280 pitch 5120 (/4 1280) >[ 29194.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669be20] >[ 29194.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669be20] width 1280 pitch 5120 (/4 1280) >[ 29195.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669be20] >[ 29195.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669be20] width 1280 pitch 5120 (/4 1280) >[ 29195.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513b70] >[ 29195.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513b70] width 1280 pitch 5120 (/4 1280) >[ 29196.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669be20] >[ 29196.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669be20] width 1280 pitch 5120 (/4 1280) >[ 29199.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513b70] >[ 29199.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513b70] width 1280 pitch 5120 (/4 1280) >[ 29199.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x669be20] >[ 29199.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x669be20] width 1280 pitch 5120 (/4 1280) >[ 29203.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3513b70] >[ 29203.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3513b70] width 1280 pitch 5120 (/4 1280) >[ 29203.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x53ca140] >[ 29203.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x53ca140] width 1280 pitch 5120 (/4 1280) >[ 29203.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3446400] >[ 29203.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3446400] width 1280 pitch 5120 (/4 1280) >[ 29205.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0ba00] >[ 29205.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0ba00] width 1280 pitch 5120 (/4 1280) >[ 29205.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ee150] >[ 29205.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ee150] width 1280 pitch 5120 (/4 1280) >[ 29205.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690af90] >[ 29205.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690af90] width 1280 pitch 5120 (/4 1280) >[ 29205.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ee150] >[ 29205.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ee150] width 1280 pitch 5120 (/4 1280) >[ 29205.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690af90] >[ 29205.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690af90] width 1280 pitch 5120 (/4 1280) >[ 29205.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ee150] >[ 29205.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ee150] width 1280 pitch 5120 (/4 1280) >[ 29206.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ee150] >[ 29206.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ee150] width 1280 pitch 5120 (/4 1280) >[ 29206.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x690af90] >[ 29206.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x690af90] width 1280 pitch 5120 (/4 1280) >[ 29206.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ee150] >[ 29206.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ee150] width 1280 pitch 5120 (/4 1280) >[ 29206.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ee150] >[ 29206.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ee150] width 1280 pitch 5120 (/4 1280) >[ 29206.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67804f0] >[ 29206.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67804f0] width 1280 pitch 5120 (/4 1280) >[ 29207.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ee150] >[ 29207.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ee150] width 1280 pitch 5120 (/4 1280) >[ 29207.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67804f0] >[ 29207.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67804f0] width 1280 pitch 5120 (/4 1280) >[ 29207.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46ee150] >[ 29207.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46ee150] width 1280 pitch 5120 (/4 1280) >[ 29207.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cca6a0] >[ 29207.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cca6a0] width 1280 pitch 5120 (/4 1280) >[ 29225.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672e870] >[ 29225.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672e870] width 1280 pitch 5120 (/4 1280) >[ 29237.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3408c60] >[ 29237.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3408c60] width 1280 pitch 5120 (/4 1280) >[ 29237.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6bf60] >[ 29237.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6bf60] width 1280 pitch 5120 (/4 1280) >[ 29239.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c56950] >[ 29239.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c56950] width 1280 pitch 5120 (/4 1280) >[ 29239.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x528aec0] >[ 29239.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x528aec0] width 1280 pitch 5120 (/4 1280) >[ 29239.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6786560] >[ 29239.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6786560] width 1280 pitch 5120 (/4 1280) >[ 29240.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6721c60] >[ 29240.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6721c60] width 1280 pitch 5120 (/4 1280) >[ 29240.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4718940] >[ 29240.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4718940] width 1280 pitch 5120 (/4 1280) >[ 29241.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 29241.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 29241.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4718940] >[ 29241.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4718940] width 1280 pitch 5120 (/4 1280) >[ 29241.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 29241.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 29241.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4718940] >[ 29241.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4718940] width 1280 pitch 5120 (/4 1280) >[ 29241.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 29241.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 29241.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4718940] >[ 29242.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4718940] width 1280 pitch 5120 (/4 1280) >[ 29242.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 29242.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 29242.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4718940] >[ 29242.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4718940] width 1280 pitch 5120 (/4 1280) >[ 29243.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677ec30] >[ 29243.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677ec30] width 1280 pitch 5120 (/4 1280) >[ 29243.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4718940] >[ 29243.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4718940] width 1280 pitch 5120 (/4 1280) >[ 29249.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66e3300] >[ 29249.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66e3300] width 1280 pitch 5120 (/4 1280) >[ 29320.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6951c80] >[ 29320.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6951c80] width 1280 pitch 5120 (/4 1280) >[ 29320.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c3a00] >[ 29320.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c3a00] width 1280 pitch 5120 (/4 1280) >[ 29320.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6951c80] >[ 29320.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6951c80] width 1280 pitch 5120 (/4 1280) >[ 29320.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c3a00] >[ 29320.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c3a00] width 1280 pitch 5120 (/4 1280) >[ 29320.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6951c80] >[ 29320.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6951c80] width 1280 pitch 5120 (/4 1280) >[ 29321.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6737d00] >[ 29321.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6737d00] width 1280 pitch 5120 (/4 1280) >[ 29326.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3435370] >[ 29326.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3435370] width 1280 pitch 5120 (/4 1280) >[ 29326.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351bd80] >[ 29326.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351bd80] width 1280 pitch 5120 (/4 1280) >[ 29326.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351bd80] >[ 29326.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351bd80] width 1280 pitch 5120 (/4 1280) >[ 29328.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6737d40] >[ 29328.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6737d40] width 1280 pitch 5120 (/4 1280) >[ 29328.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340f6d0] >[ 29328.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340f6d0] width 1280 pitch 5120 (/4 1280) >[ 29328.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6737d40] >[ 29328.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6737d40] width 1280 pitch 5120 (/4 1280) >[ 29328.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340f6d0] >[ 29328.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340f6d0] width 1280 pitch 5120 (/4 1280) >[ 29328.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6737d40] >[ 29328.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6737d40] width 1280 pitch 5120 (/4 1280) >[ 29328.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340f6d0] >[ 29329.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340f6d0] width 1280 pitch 5120 (/4 1280) >[ 29329.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6737d40] >[ 29329.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6737d40] width 1280 pitch 5120 (/4 1280) >[ 29329.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340f6d0] >[ 29329.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340f6d0] width 1280 pitch 5120 (/4 1280) >[ 29329.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6737d40] >[ 29329.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6737d40] width 1280 pitch 5120 (/4 1280) >[ 29331.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340f6d0] >[ 29331.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340f6d0] width 1280 pitch 5120 (/4 1280) >[ 29332.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7b7e0] >[ 29332.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7b7e0] width 1280 pitch 5120 (/4 1280) >[ 29332.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346cae0] >[ 29332.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346cae0] width 1280 pitch 5120 (/4 1280) >[ 29343.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3444c90] >[ 29343.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3444c90] width 1280 pitch 5120 (/4 1280) >[ 29343.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346cae0] >[ 29343.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346cae0] width 1280 pitch 5120 (/4 1280) >[ 29343.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3444c90] >[ 29343.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3444c90] width 1280 pitch 5120 (/4 1280) >[ 29343.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346cae0] >[ 29343.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346cae0] width 1280 pitch 5120 (/4 1280) >[ 29344.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3444c90] >[ 29344.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3444c90] width 1280 pitch 5120 (/4 1280) >[ 29344.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346cae0] >[ 29344.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346cae0] width 1280 pitch 5120 (/4 1280) >[ 29344.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3444c90] >[ 29344.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3444c90] width 1280 pitch 5120 (/4 1280) >[ 29344.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346cae0] >[ 29344.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346cae0] width 1280 pitch 5120 (/4 1280) >[ 29345.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3444c90] >[ 29345.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3444c90] width 1280 pitch 5120 (/4 1280) >[ 29345.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342f330] >[ 29345.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342f330] width 1280 pitch 5120 (/4 1280) >[ 29345.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7b7e0] >[ 29345.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7b7e0] width 1280 pitch 5120 (/4 1280) >[ 29345.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67379f0] >[ 29345.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67379f0] width 1280 pitch 5120 (/4 1280) >[ 30225.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x472aa90] >[ 30225.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x472aa90] width 1280 pitch 5120 (/4 1280) >[ 30225.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x472aa90] >[ 30225.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x472aa90] width 1280 pitch 5120 (/4 1280) >[ 30571.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30571.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30571.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879c70] >[ 30571.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879c70] width 1280 pitch 5120 (/4 1280) >[ 30571.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30571.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30571.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879c70] >[ 30571.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879c70] width 1280 pitch 5120 (/4 1280) >[ 30571.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b351c0] >[ 30571.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b351c0] width 1280 pitch 5120 (/4 1280) >[ 30576.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30576.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30576.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879c70] >[ 30576.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879c70] width 1280 pitch 5120 (/4 1280) >[ 30576.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30577.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30577.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879c70] >[ 30577.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879c70] width 1280 pitch 5120 (/4 1280) >[ 30577.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30577.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30578.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879c70] >[ 30578.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879c70] width 1280 pitch 5120 (/4 1280) >[ 30578.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30578.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30578.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879c70] >[ 30578.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879c70] width 1280 pitch 5120 (/4 1280) >[ 30578.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30578.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30578.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30578.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30578.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b351c0] >[ 30578.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b351c0] width 1280 pitch 5120 (/4 1280) >[ 30578.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482620] >[ 30578.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482620] width 1280 pitch 5120 (/4 1280) >[ 30651.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34acfd0] >[ 30651.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34acfd0] width 1280 pitch 5120 (/4 1280) >[ 30651.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35062b0] >[ 30651.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35062b0] width 1280 pitch 5120 (/4 1280) >[ 30689.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b6d760] >[ 30689.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b6d760] width 1280 pitch 5120 (/4 1280) >[ 30689.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bdc140] >[ 30689.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bdc140] width 1280 pitch 5120 (/4 1280) >[ 30998.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5491360] >[ 30998.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5491360] width 1280 pitch 5120 (/4 1280) >[ 31017.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ec90] >[ 31017.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ec90] width 1280 pitch 5120 (/4 1280) >[ 31042.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x548ec90] >[ 31042.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x548ec90] width 1280 pitch 5120 (/4 1280) >[ 31933.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71c00] >[ 31933.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71c00] width 1280 pitch 5120 (/4 1280) >[ 31933.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e71c00] >[ 31933.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e71c00] width 1280 pitch 5120 (/4 1280) >[ 32429.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5468000] >[ 32429.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5468000] width 1280 pitch 5120 (/4 1280) >[ 32429.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462630] >[ 32429.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462630] width 1280 pitch 5120 (/4 1280) >[ 32431.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462630] >[ 32431.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462630] width 1280 pitch 5120 (/4 1280) >[ 32431.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462630] >[ 32431.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462630] width 1280 pitch 5120 (/4 1280) >[ 32431.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546bbf0] >[ 32431.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546bbf0] width 1280 pitch 5120 (/4 1280) >[ 32431.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54674d0] >[ 32431.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54674d0] width 1280 pitch 5120 (/4 1280) >[ 32432.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462630] >[ 32432.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462630] width 1280 pitch 5120 (/4 1280) >[ 32432.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546b920] >[ 32432.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546b920] width 1280 pitch 5120 (/4 1280) >[ 32432.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54674d0] >[ 32432.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54674d0] width 1280 pitch 5120 (/4 1280) >[ 32433.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462630] >[ 32433.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462630] width 1280 pitch 5120 (/4 1280) >[ 32433.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546f3b0] >[ 32433.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546f3b0] width 1280 pitch 5120 (/4 1280) >[ 32433.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54674d0] >[ 32433.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54674d0] width 1280 pitch 5120 (/4 1280) >[ 32433.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546f3b0] >[ 32433.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546f3b0] width 1280 pitch 5120 (/4 1280) >[ 32433.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54674d0] >[ 32433.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54674d0] width 1280 pitch 5120 (/4 1280) >[ 32434.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462630] >[ 32434.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462630] width 1280 pitch 5120 (/4 1280) >[ 32434.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546f3b0] >[ 32434.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546f3b0] width 1280 pitch 5120 (/4 1280) >[ 32434.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54674d0] >[ 32434.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54674d0] width 1280 pitch 5120 (/4 1280) >[ 32434.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546f3b0] >[ 32434.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546f3b0] width 1280 pitch 5120 (/4 1280) >[ 32434.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54674d0] >[ 32434.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54674d0] width 1280 pitch 5120 (/4 1280) >[ 32435.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546f3b0] >[ 32435.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546f3b0] width 1280 pitch 5120 (/4 1280) >[ 32435.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546c3d0] >[ 32435.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546c3d0] width 1280 pitch 5120 (/4 1280) >[ 32437.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5462630] >[ 32437.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5462630] width 1280 pitch 5120 (/4 1280) >[ 32437.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5495620] >[ 32437.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5495620] width 1280 pitch 5120 (/4 1280) >[ 32437.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54674d0] >[ 32437.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54674d0] width 1280 pitch 5120 (/4 1280) >[ 32442.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7aab610] >[ 32442.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7aab610] width 1280 pitch 5120 (/4 1280) >[ 32933.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x546ab90] >[ 32933.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x546ab90] width 1280 pitch 5120 (/4 1280) >[ 32934.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5495520] >[ 32934.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5495520] width 1280 pitch 5120 (/4 1280) >[ 32934.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7aaa570] >[ 32934.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7aaa570] width 1280 pitch 5120 (/4 1280) >[ 33644.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6547930] >[ 33644.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6547930] width 1280 pitch 5120 (/4 1280) >[ 33644.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7aca4f0] >[ 33644.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7aca4f0] width 1280 pitch 5120 (/4 1280) >[ 33644.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a80530] >[ 33644.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a80530] width 1280 pitch 5120 (/4 1280) >[ 33688.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x659c0e0] >[ 33688.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x659c0e0] width 1280 pitch 5120 (/4 1280) >[ 33688.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x653e8e0] >[ 33688.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x653e8e0] width 1280 pitch 5120 (/4 1280) >[ 33688.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x659f9d0] >[ 33688.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x659f9d0] width 1280 pitch 5120 (/4 1280) >[ 33700.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655f0e0] >[ 33701.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655f0e0] width 1280 pitch 5120 (/4 1280) >[ 33701.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5470940] >[ 33701.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5470940] width 1280 pitch 5120 (/4 1280) >[ 34125.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cf090] >[ 34125.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cf090] width 1280 pitch 5120 (/4 1280) >[ 34125.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a3050] >[ 34125.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a3050] width 1280 pitch 5120 (/4 1280) >[ 34125.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a3a00] >[ 34125.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a3a00] width 1280 pitch 5120 (/4 1280) >[ 34125.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a3050] >[ 34125.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a3050] width 1280 pitch 5120 (/4 1280) >[ 34126.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a3050] >[ 34126.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a3050] width 1280 pitch 5120 (/4 1280) >[ 34126.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65428c0] >[ 34126.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65428c0] width 1280 pitch 5120 (/4 1280) >[ 34127.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a3050] >[ 34127.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a3050] width 1280 pitch 5120 (/4 1280) >[ 34127.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bd290] >[ 34127.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bd290] width 1280 pitch 5120 (/4 1280) >[ 34127.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a3050] >[ 34128.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a3050] width 1280 pitch 5120 (/4 1280) >[ 34128.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bd290] >[ 34128.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bd290] width 1280 pitch 5120 (/4 1280) >[ 34128.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a3050] >[ 34128.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a3050] width 1280 pitch 5120 (/4 1280) >[ 34128.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65428c0] >[ 34128.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65428c0] width 1280 pitch 5120 (/4 1280) >[ 34129.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a49f0] >[ 34129.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a49f0] width 1280 pitch 5120 (/4 1280) >[ 34129.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a49f0] >[ 34129.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a49f0] width 1280 pitch 5120 (/4 1280) >[ 34129.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a3050] >[ 34129.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a3050] width 1280 pitch 5120 (/4 1280) >[ 34153.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a49f0] >[ 34153.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a49f0] width 1280 pitch 5120 (/4 1280) >[ 34153.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68d5a50] >[ 34153.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68d5a50] width 1280 pitch 5120 (/4 1280) >[ 34158.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cf0d0] >[ 34158.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cf0d0] width 1280 pitch 5120 (/4 1280) >[ 34158.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a2d10] >[ 34158.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a2d10] width 1280 pitch 5120 (/4 1280) >[ 34164.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65aab90] >[ 34164.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65aab90] width 1280 pitch 5120 (/4 1280) >[ 34164.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a49f0] >[ 34164.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a49f0] width 1280 pitch 5120 (/4 1280) >[ 34164.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x549e810] >[ 34164.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x549e810] width 1280 pitch 5120 (/4 1280) >[ 34164.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a49f0] >[ 34164.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a49f0] width 1280 pitch 5120 (/4 1280) >[ 34166.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65a5980] >[ 34166.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65a5980] width 1280 pitch 5120 (/4 1280) >[ 34300.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd2200] >[ 34300.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd2200] width 1280 pitch 5120 (/4 1280) >[ 34301.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd0a90] >[ 34301.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd0a90] width 1280 pitch 5120 (/4 1280) >[ 34301.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd2200] >[ 34301.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd2200] width 1280 pitch 5120 (/4 1280) >[ 34301.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd0a90] >[ 34301.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd0a90] width 1280 pitch 5120 (/4 1280) >[ 34301.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd2200] >[ 34301.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd2200] width 1280 pitch 5120 (/4 1280) >[ 34301.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd0a90] >[ 34302.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd0a90] width 1280 pitch 5120 (/4 1280) >[ 34302.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd2200] >[ 34302.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd2200] width 1280 pitch 5120 (/4 1280) >[ 34302.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd0a90] >[ 34302.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd0a90] width 1280 pitch 5120 (/4 1280) >[ 34302.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd2200] >[ 34302.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd2200] width 1280 pitch 5120 (/4 1280) >[ 34303.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd0a90] >[ 34303.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd0a90] width 1280 pitch 5120 (/4 1280) >[ 34303.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd2200] >[ 34303.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd2200] width 1280 pitch 5120 (/4 1280) >[ 34303.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd0a90] >[ 34303.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd0a90] width 1280 pitch 5120 (/4 1280) >[ 34303.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd2200] >[ 34303.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd2200] width 1280 pitch 5120 (/4 1280) >[ 34303.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd0a90] >[ 34303.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd0a90] width 1280 pitch 5120 (/4 1280) >[ 34325.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a2690] >[ 34325.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a2690] width 1280 pitch 5120 (/4 1280) >[ 34345.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d520] >[ 34345.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d520] width 1280 pitch 5120 (/4 1280) >[ 34371.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1ff0] >[ 34371.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1ff0] width 1280 pitch 5120 (/4 1280) >[ 34541.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65573d0] >[ 34541.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65573d0] width 1280 pitch 5120 (/4 1280) >[ 34541.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68a2470] >[ 34541.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68a2470] width 1280 pitch 5120 (/4 1280) >[ 34832.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bd4f90] >[ 34832.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bd4f90] width 1280 pitch 5120 (/4 1280) >[ 34832.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6592ab0] >[ 34832.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6592ab0] width 1280 pitch 5120 (/4 1280) >[ 34940.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6572fc0] >[ 34941.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6572fc0] width 1280 pitch 5120 (/4 1280) >[ 34941.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x655c7f0] >[ 34941.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x655c7f0] width 1280 pitch 5120 (/4 1280) >[ 34941.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bf9f0] >[ 34941.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bf9f0] width 1280 pitch 5120 (/4 1280) >[ 35051.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b2fa0] >[ 35051.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b2fa0] width 1280 pitch 5120 (/4 1280) >[ 35051.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b37d0] >[ 35051.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b37d0] width 1280 pitch 5120 (/4 1280) >[ 35051.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6595fd0] >[ 35051.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6595fd0] width 1280 pitch 5120 (/4 1280) >[ 35084.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bb120] >[ 35084.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bb120] width 1280 pitch 5120 (/4 1280) >[ 35084.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c1780] >[ 35084.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c1780] width 1280 pitch 5120 (/4 1280) >[ 35084.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6590c50] >[ 35084.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6590c50] width 1280 pitch 5120 (/4 1280) >[ 35087.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b2a30] >[ 35087.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b2a30] width 1280 pitch 5120 (/4 1280) >[ 35087.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c5340] >[ 35087.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c5340] width 1280 pitch 5120 (/4 1280) >[ 35088.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c1780] >[ 35088.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c1780] width 1280 pitch 5120 (/4 1280) >[ 35088.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b2a30] >[ 35088.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b2a30] width 1280 pitch 5120 (/4 1280) >[ 35088.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c1780] >[ 35088.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c1780] width 1280 pitch 5120 (/4 1280) >[ 35088.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b2a30] >[ 35088.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b2a30] width 1280 pitch 5120 (/4 1280) >[ 35088.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c4490] >[ 35089.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c4490] width 1280 pitch 5120 (/4 1280) >[ 35116.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c83f0] >[ 35116.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c83f0] width 1280 pitch 5120 (/4 1280) >[ 35117.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cce40] >[ 35117.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cce40] width 1280 pitch 5120 (/4 1280) >[ 35117.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cce40] >[ 35117.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cce40] width 1280 pitch 5120 (/4 1280) >[ 35117.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c83f0] >[ 35118.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c83f0] width 1280 pitch 5120 (/4 1280) >[ 35118.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c5d20] >[ 35118.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c5d20] width 1280 pitch 5120 (/4 1280) >[ 35118.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c6d10] >[ 35118.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c6d10] width 1280 pitch 5120 (/4 1280) >[ 35118.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65984b0] >[ 35118.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65984b0] width 1280 pitch 5120 (/4 1280) >[ 35119.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c9300] >[ 35119.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c9300] width 1280 pitch 5120 (/4 1280) >[ 35119.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c93e0] >[ 35119.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c93e0] width 1280 pitch 5120 (/4 1280) >[ 35119.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c5d20] >[ 35119.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c5d20] width 1280 pitch 5120 (/4 1280) >[ 35119.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c93e0] >[ 35119.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c93e0] width 1280 pitch 5120 (/4 1280) >[ 35120.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c9300] >[ 35120.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c9300] width 1280 pitch 5120 (/4 1280) >[ 35121.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c5130] >[ 35121.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c5130] width 1280 pitch 5120 (/4 1280) >[ 35121.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c5d20] >[ 35121.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c5d20] width 1280 pitch 5120 (/4 1280) >[ 35121.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65ce4a0] >[ 35121.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65ce4a0] width 1280 pitch 5120 (/4 1280) >[ 35122.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cce40] >[ 35122.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cce40] width 1280 pitch 5120 (/4 1280) >[ 35122.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cce40] >[ 35122.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cce40] width 1280 pitch 5120 (/4 1280) >[ 35122.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65ccd30] >[ 35122.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65ccd30] width 1280 pitch 5120 (/4 1280) >[ 35123.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c3c00] >[ 35123.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c3c00] width 1280 pitch 5120 (/4 1280) >[ 35123.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65ccd30] >[ 35123.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65ccd30] width 1280 pitch 5120 (/4 1280) >[ 35123.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c3c00] >[ 35123.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c3c00] width 1280 pitch 5120 (/4 1280) >[ 35123.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65ccd30] >[ 35123.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65ccd30] width 1280 pitch 5120 (/4 1280) >[ 35123.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c3c00] >[ 35123.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c3c00] width 1280 pitch 5120 (/4 1280) >[ 35123.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65ccd30] >[ 35124.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65ccd30] width 1280 pitch 5120 (/4 1280) >[ 35124.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65ccd30] >[ 35124.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65ccd30] width 1280 pitch 5120 (/4 1280) >[ 35124.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c3c00] >[ 35124.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c3c00] width 1280 pitch 5120 (/4 1280) >[ 35124.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c3c00] >[ 35124.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c3c00] width 1280 pitch 5120 (/4 1280) >[ 35124.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65ccd30] >[ 35124.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65ccd30] width 1280 pitch 5120 (/4 1280) >[ 35156.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6657070] >[ 35156.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6657070] width 1280 pitch 5120 (/4 1280) >[ 35157.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65c3c00] >[ 35157.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65c3c00] width 1280 pitch 5120 (/4 1280) >[ 35157.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cbb50] >[ 35157.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cbb50] width 1280 pitch 5120 (/4 1280) >[ 35157.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65ccd30] >[ 35157.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65ccd30] width 1280 pitch 5120 (/4 1280) >[ 35157.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6659970] >[ 35157.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6659970] width 1280 pitch 5120 (/4 1280) >[ 35410.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35410.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35410.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66593d0] >[ 35410.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66593d0] width 1280 pitch 5120 (/4 1280) >[ 35411.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35411.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35411.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66593d0] >[ 35411.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66593d0] width 1280 pitch 5120 (/4 1280) >[ 35411.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35411.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35411.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66593d0] >[ 35411.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66593d0] width 1280 pitch 5120 (/4 1280) >[ 35411.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35412.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35412.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bb270] >[ 35412.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bb270] width 1280 pitch 5120 (/4 1280) >[ 35412.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bdb40] >[ 35412.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bdb40] width 1280 pitch 5120 (/4 1280) >[ 35412.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bb270] >[ 35412.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bb270] width 1280 pitch 5120 (/4 1280) >[ 35412.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b20d0] >[ 35412.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b20d0] width 1280 pitch 5120 (/4 1280) >[ 35415.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68aff60] >[ 35415.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68aff60] width 1280 pitch 5120 (/4 1280) >[ 35415.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66593d0] >[ 35415.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66593d0] width 1280 pitch 5120 (/4 1280) >[ 35415.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35416.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35416.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b20d0] >[ 35416.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b20d0] width 1280 pitch 5120 (/4 1280) >[ 35416.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bb270] >[ 35416.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bb270] width 1280 pitch 5120 (/4 1280) >[ 35416.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68aff60] >[ 35416.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68aff60] width 1280 pitch 5120 (/4 1280) >[ 35416.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6663a60] >[ 35416.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6663a60] width 1280 pitch 5120 (/4 1280) >[ 35416.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35416.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35416.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b20d0] >[ 35416.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b20d0] width 1280 pitch 5120 (/4 1280) >[ 35417.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35417.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35417.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b20d0] >[ 35417.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b20d0] width 1280 pitch 5120 (/4 1280) >[ 35417.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35417.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35417.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35417.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35417.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a00f0] >[ 35417.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a00f0] width 1280 pitch 5120 (/4 1280) >[ 35417.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35418.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35418.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a00f0] >[ 35418.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a00f0] width 1280 pitch 5120 (/4 1280) >[ 35418.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b20d0] >[ 35418.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b20d0] width 1280 pitch 5120 (/4 1280) >[ 35418.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a00f0] >[ 35418.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a00f0] width 1280 pitch 5120 (/4 1280) >[ 35419.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65b20d0] >[ 35419.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65b20d0] width 1280 pitch 5120 (/4 1280) >[ 35419.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a00f0] >[ 35419.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a00f0] width 1280 pitch 5120 (/4 1280) >[ 35490.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668abb0] >[ 35490.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668abb0] width 1280 pitch 5120 (/4 1280) >[ 35509.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 35509.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 35529.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35529.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35529.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35529.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35529.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35529.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35529.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35529.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35530.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35530.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35530.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35530.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35530.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35530.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35530.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35530.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35530.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35530.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35531.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4250] >[ 35531.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4250] width 1280 pitch 5120 (/4 1280) >[ 35531.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35531.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35531.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4250] >[ 35531.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4250] width 1280 pitch 5120 (/4 1280) >[ 35531.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6662860] >[ 35531.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6662860] width 1280 pitch 5120 (/4 1280) >[ 35545.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 35545.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 35545.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bdb40] >[ 35545.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bdb40] width 1280 pitch 5120 (/4 1280) >[ 35545.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 35545.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 35545.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bdb40] >[ 35545.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bdb40] width 1280 pitch 5120 (/4 1280) >[ 35545.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 35546.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 35546.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bdb40] >[ 35546.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bdb40] width 1280 pitch 5120 (/4 1280) >[ 35546.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 35546.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 35546.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bdb40] >[ 35546.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bdb40] width 1280 pitch 5120 (/4 1280) >[ 35546.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 35546.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 35546.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bdb40] >[ 35546.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bdb40] width 1280 pitch 5120 (/4 1280) >[ 35547.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35547.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35547.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35547.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35547.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35547.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35548.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35548.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35548.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35548.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35548.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35548.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35549.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35549.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35549.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35549.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35549.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35549.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35549.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35549.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35550.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bb270] >[ 35550.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bb270] width 1280 pitch 5120 (/4 1280) >[ 35550.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bb270] >[ 35550.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bb270] width 1280 pitch 5120 (/4 1280) >[ 35550.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35550.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35574.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7bb72c0] >[ 35574.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7bb72c0] width 1280 pitch 5120 (/4 1280) >[ 35574.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1e80] >[ 35574.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1e80] width 1280 pitch 5120 (/4 1280) >[ 35599.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6663f10] >[ 35599.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6663f10] width 1280 pitch 5120 (/4 1280) >[ 35599.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6621440] >[ 35599.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6621440] width 1280 pitch 5120 (/4 1280) >[ 35984.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4723680] >[ 35984.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4723680] width 1280 pitch 5120 (/4 1280) >[ 35984.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4723610] >[ 35984.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4723610] width 1280 pitch 5120 (/4 1280) >[ 35984.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6589220] >[ 35984.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6589220] width 1280 pitch 5120 (/4 1280) >[ 35984.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65635f0] >[ 35984.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65635f0] width 1280 pitch 5120 (/4 1280) >[ 35984.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6589220] >[ 35984.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6589220] width 1280 pitch 5120 (/4 1280) >[ 35984.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65635f0] >[ 35984.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65635f0] width 1280 pitch 5120 (/4 1280) >[ 35988.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668a1d0] >[ 35988.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668a1d0] width 1280 pitch 5120 (/4 1280) >[ 35988.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65635f0] >[ 35988.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65635f0] width 1280 pitch 5120 (/4 1280) >[ 35988.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668a3f0] >[ 35988.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668a3f0] width 1280 pitch 5120 (/4 1280) >[ 35988.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65635f0] >[ 35989.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65635f0] width 1280 pitch 5120 (/4 1280) >[ 35989.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668a470] >[ 35989.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668a470] width 1280 pitch 5120 (/4 1280) >[ 35989.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65635f0] >[ 35989.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65635f0] width 1280 pitch 5120 (/4 1280) >[ 35990.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a816e0] >[ 35990.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a816e0] width 1280 pitch 5120 (/4 1280) >[ 35990.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65635f0] >[ 35990.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65635f0] width 1280 pitch 5120 (/4 1280) >[ 35990.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a816e0] >[ 35990.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a816e0] width 1280 pitch 5120 (/4 1280) >[ 35990.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65635f0] >[ 35990.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65635f0] width 1280 pitch 5120 (/4 1280) >[ 35990.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25ec0] >[ 35990.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25ec0] width 1280 pitch 5120 (/4 1280) >[ 35990.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65635f0] >[ 35990.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65635f0] width 1280 pitch 5120 (/4 1280) >[ 35990.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25ec0] >[ 35990.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25ec0] width 1280 pitch 5120 (/4 1280) >[ 36044.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25ec0] >[ 36044.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25ec0] width 1280 pitch 5120 (/4 1280) >[ 36044.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4723840] >[ 36044.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4723840] width 1280 pitch 5120 (/4 1280) >[ 36044.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68d8a60] >[ 36044.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68d8a60] width 1280 pitch 5120 (/4 1280) >[ 36044.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4723840] >[ 36045.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4723840] width 1280 pitch 5120 (/4 1280) >[ 36045.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6669e90] >[ 36045.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6669e90] width 1280 pitch 5120 (/4 1280) >[ 36046.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668a530] >[ 36046.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668a530] width 1280 pitch 5120 (/4 1280) >[ 36046.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668a530] >[ 36046.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668a530] width 1280 pitch 5120 (/4 1280) >[ 36046.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668a530] >[ 36046.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668a530] width 1280 pitch 5120 (/4 1280) >[ 36046.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668a270] >[ 36046.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668a270] width 1280 pitch 5120 (/4 1280) >[ 36046.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x668a270] >[ 36047.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x668a270] width 1280 pitch 5120 (/4 1280) >[ 36047.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6579130] >[ 36047.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6579130] width 1280 pitch 5120 (/4 1280) >[ 36047.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4723600] >[ 36047.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4723600] width 1280 pitch 5120 (/4 1280) >[ 36273.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6638fd0] >[ 36273.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6638fd0] width 1280 pitch 5120 (/4 1280) >[ 36273.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6635df0] >[ 36273.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6635df0] width 1280 pitch 5120 (/4 1280) >[ 36277.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6638fd0] >[ 36277.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6638fd0] width 1280 pitch 5120 (/4 1280) >[ 36277.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6615660] >[ 36277.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6615660] width 1280 pitch 5120 (/4 1280) >[ 36304.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661db10] >[ 36304.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661db10] width 1280 pitch 5120 (/4 1280) >[ 36304.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66141d0] >[ 36304.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66141d0] width 1280 pitch 5120 (/4 1280) >[ 36305.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661db10] >[ 36305.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661db10] width 1280 pitch 5120 (/4 1280) >[ 36305.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66141d0] >[ 36305.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66141d0] width 1280 pitch 5120 (/4 1280) >[ 36305.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661db10] >[ 36305.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661db10] width 1280 pitch 5120 (/4 1280) >[ 36305.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66141d0] >[ 36305.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66141d0] width 1280 pitch 5120 (/4 1280) >[ 36305.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661db10] >[ 36305.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661db10] width 1280 pitch 5120 (/4 1280) >[ 36306.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66141d0] >[ 36306.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66141d0] width 1280 pitch 5120 (/4 1280) >[ 36306.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661db10] >[ 36306.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661db10] width 1280 pitch 5120 (/4 1280) >[ 36306.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66141d0] >[ 36306.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66141d0] width 1280 pitch 5120 (/4 1280) >[ 36306.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661db10] >[ 36306.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661db10] width 1280 pitch 5120 (/4 1280) >[ 36306.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66141d0] >[ 36306.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66141d0] width 1280 pitch 5120 (/4 1280) >[ 36306.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661db10] >[ 36306.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661db10] width 1280 pitch 5120 (/4 1280) >[ 36307.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66141d0] >[ 36307.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66141d0] width 1280 pitch 5120 (/4 1280) >[ 36307.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x661db10] >[ 36307.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x661db10] width 1280 pitch 5120 (/4 1280) >[ 36308.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66141d0] >[ 36308.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66141d0] width 1280 pitch 5120 (/4 1280) >[ 36308.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x666ad90] >[ 36308.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x666ad90] width 1280 pitch 5120 (/4 1280) >[ 36363.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36363.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36408.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6642f10] >[ 36408.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6642f10] width 1280 pitch 5120 (/4 1280) >[ 36408.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6642f10] >[ 36408.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6642f10] width 1280 pitch 5120 (/4 1280) >[ 36408.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36408.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36408.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6642f10] >[ 36408.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6642f10] width 1280 pitch 5120 (/4 1280) >[ 36408.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36408.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36408.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6635df0] >[ 36408.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6635df0] width 1280 pitch 5120 (/4 1280) >[ 36408.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e6b00] >[ 36409.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e6b00] width 1280 pitch 5120 (/4 1280) >[ 36409.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c372a0] >[ 36409.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c372a0] width 1280 pitch 5120 (/4 1280) >[ 36409.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36409.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36409.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c372a0] >[ 36409.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c372a0] width 1280 pitch 5120 (/4 1280) >[ 36409.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36409.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36409.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6642f10] >[ 36409.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6642f10] width 1280 pitch 5120 (/4 1280) >[ 36420.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c372a0] >[ 36420.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c372a0] width 1280 pitch 5120 (/4 1280) >[ 36420.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e6b00] >[ 36420.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e6b00] width 1280 pitch 5120 (/4 1280) >[ 36420.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c372a0] >[ 36420.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c372a0] width 1280 pitch 5120 (/4 1280) >[ 36421.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e6b00] >[ 36421.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e6b00] width 1280 pitch 5120 (/4 1280) >[ 36421.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c372a0] >[ 36421.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c372a0] width 1280 pitch 5120 (/4 1280) >[ 36421.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e6b00] >[ 36421.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e6b00] width 1280 pitch 5120 (/4 1280) >[ 36421.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c372a0] >[ 36421.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c372a0] width 1280 pitch 5120 (/4 1280) >[ 36422.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6ea0] >[ 36422.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6ea0] width 1280 pitch 5120 (/4 1280) >[ 36422.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6663a60] >[ 36422.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6663a60] width 1280 pitch 5120 (/4 1280) >[ 36422.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65bdb40] >[ 36422.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65bdb40] width 1280 pitch 5120 (/4 1280) >[ 36422.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 36422.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 36425.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 36425.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 36425.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6635df0] >[ 36425.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6635df0] width 1280 pitch 5120 (/4 1280) >[ 36425.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 36425.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 36425.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6635df0] >[ 36425.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6635df0] width 1280 pitch 5120 (/4 1280) >[ 36425.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c3c0] >[ 36426.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c3c0] width 1280 pitch 5120 (/4 1280) >[ 36426.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6663a60] >[ 36426.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6663a60] width 1280 pitch 5120 (/4 1280) >[ 36426.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4250] >[ 36426.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4250] width 1280 pitch 5120 (/4 1280) >[ 36426.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36426.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36426.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6663a60] >[ 36426.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6663a60] width 1280 pitch 5120 (/4 1280) >[ 36426.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36426.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36426.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6663a60] >[ 36426.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6663a60] width 1280 pitch 5120 (/4 1280) >[ 36426.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36426.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36426.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6663a60] >[ 36426.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6663a60] width 1280 pitch 5120 (/4 1280) >[ 36426.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36426.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36426.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6663a60] >[ 36426.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6663a60] width 1280 pitch 5120 (/4 1280) >[ 36426.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6632b00] >[ 36426.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6632b00] width 1280 pitch 5120 (/4 1280) >[ 36487.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cba00] >[ 36487.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cba00] width 1280 pitch 5120 (/4 1280) >[ 36487.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36487.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36487.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cba00] >[ 36487.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cba00] width 1280 pitch 5120 (/4 1280) >[ 36487.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36487.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36488.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cba00] >[ 36488.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cba00] width 1280 pitch 5120 (/4 1280) >[ 36488.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36488.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36488.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cba00] >[ 36488.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cba00] width 1280 pitch 5120 (/4 1280) >[ 36488.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36488.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36488.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cba00] >[ 36489.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cba00] width 1280 pitch 5120 (/4 1280) >[ 36489.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cafa0] >[ 36489.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cafa0] width 1280 pitch 5120 (/4 1280) >[ 36489.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36489.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36489.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cafa0] >[ 36489.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cafa0] width 1280 pitch 5120 (/4 1280) >[ 36489.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36490.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36490.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cafa0] >[ 36490.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cafa0] width 1280 pitch 5120 (/4 1280) >[ 36490.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36490.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36490.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cafa0] >[ 36490.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cafa0] width 1280 pitch 5120 (/4 1280) >[ 36490.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36490.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36491.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cafa0] >[ 36491.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cafa0] width 1280 pitch 5120 (/4 1280) >[ 36491.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6dd0] >[ 36491.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6dd0] width 1280 pitch 5120 (/4 1280) >[ 36491.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cafa0] >[ 36491.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cafa0] width 1280 pitch 5120 (/4 1280) >[ 36493.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cafe0] >[ 36493.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cafe0] width 1280 pitch 5120 (/4 1280) >[ 36493.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x545b3c0] >[ 36493.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x545b3c0] width 1280 pitch 5120 (/4 1280) >[ 36495.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65cafa0] >[ 36495.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65cafa0] width 1280 pitch 5120 (/4 1280) >[ 36495.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6641ee0] >[ 36496.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6641ee0] width 1280 pitch 5120 (/4 1280) >[ 36496.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6641a20] >[ 36496.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6641a20] width 1280 pitch 5120 (/4 1280) >[ 36503.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6676af0] >[ 36503.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6676af0] width 1280 pitch 5120 (/4 1280) >[ 36503.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7a85700] >[ 36504.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7a85700] width 1280 pitch 5120 (/4 1280) >[ 36510.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e6420] >[ 36510.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e6420] width 1280 pitch 5120 (/4 1280) >[ 36510.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d8290] >[ 36510.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d8290] width 1280 pitch 5120 (/4 1280) >[ 36525.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d8290] >[ 36525.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d8290] width 1280 pitch 5120 (/4 1280) >[ 36525.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d8290] >[ 36525.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d8290] width 1280 pitch 5120 (/4 1280) >[ 36563.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36563.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36563.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36563.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36563.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36563.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36563.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6642440] >[ 36563.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6642440] width 1280 pitch 5120 (/4 1280) >[ 36563.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6675520] >[ 36563.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6675520] width 1280 pitch 5120 (/4 1280) >[ 36563.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36563.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36564.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36564.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36564.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36564.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36564.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36564.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36564.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36564.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36564.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f6440] >[ 36564.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f6440] width 1280 pitch 5120 (/4 1280) >[ 36564.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6675520] >[ 36564.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6675520] width 1280 pitch 5120 (/4 1280) >[ 36564.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36564.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36564.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36564.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36564.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36564.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36565.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36565.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36565.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6792910] >[ 36565.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6792910] width 1280 pitch 5120 (/4 1280) >[ 36565.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6675520] >[ 36565.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6675520] width 1280 pitch 5120 (/4 1280) >[ 36565.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36565.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36565.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6792910] >[ 36565.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6792910] width 1280 pitch 5120 (/4 1280) >[ 36566.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36566.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36566.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36566.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36566.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36566.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36566.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f62c0] >[ 36566.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f62c0] width 1280 pitch 5120 (/4 1280) >[ 36568.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f6000] >[ 36568.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f6000] width 1280 pitch 5120 (/4 1280) >[ 36569.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6792910] >[ 36569.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6792910] width 1280 pitch 5120 (/4 1280) >[ 36569.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f6c60] >[ 36569.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f6c60] width 1280 pitch 5120 (/4 1280) >[ 36570.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6675520] >[ 36570.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6675520] width 1280 pitch 5120 (/4 1280) >[ 36570.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dcf50] >[ 36570.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dcf50] width 1280 pitch 5120 (/4 1280) >[ 36570.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6621970] >[ 36570.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6621970] width 1280 pitch 5120 (/4 1280) >[ 36570.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f6c60] >[ 36570.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f6c60] width 1280 pitch 5120 (/4 1280) >[ 36570.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65f6c60] >[ 36570.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65f6c60] width 1280 pitch 5120 (/4 1280) >[ 36570.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6621970] >[ 36570.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6621970] width 1280 pitch 5120 (/4 1280) >[ 36570.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6621970] >[ 36570.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6621970] width 1280 pitch 5120 (/4 1280) >[ 36572.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x663f810] >[ 36572.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x663f810] width 1280 pitch 5120 (/4 1280) >[ 36572.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x663f810] >[ 36572.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x663f810] width 1280 pitch 5120 (/4 1280) >[ 36579.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47165b0] >[ 36579.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47165b0] width 1280 pitch 5120 (/4 1280) >[ 36619.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349dc50] >[ 36619.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349dc50] width 1280 pitch 5120 (/4 1280) >[ 36619.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349dc50] >[ 36619.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349dc50] width 1280 pitch 5120 (/4 1280) >[ 36635.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7ad4110] >[ 36635.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7ad4110] width 1280 pitch 5120 (/4 1280) >[ 36706.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d920] >[ 36706.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d920] width 1280 pitch 5120 (/4 1280) >[ 36706.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d840] >[ 36706.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d840] width 1280 pitch 5120 (/4 1280) >[ 36706.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d920] >[ 36706.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d920] width 1280 pitch 5120 (/4 1280) >[ 36706.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d840] >[ 36706.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d840] width 1280 pitch 5120 (/4 1280) >[ 36706.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af3b30] >[ 36706.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af3b30] width 1280 pitch 5120 (/4 1280) >[ 36706.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36706.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36706.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af3b30] >[ 36706.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af3b30] width 1280 pitch 5120 (/4 1280) >[ 36706.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af3b30] >[ 36706.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af3b30] width 1280 pitch 5120 (/4 1280) >[ 36706.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36706.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36706.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af3b30] >[ 36706.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af3b30] width 1280 pitch 5120 (/4 1280) >[ 36706.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36707.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36707.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af3b30] >[ 36707.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af3b30] width 1280 pitch 5120 (/4 1280) >[ 36707.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36707.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36707.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af3b30] >[ 36707.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af3b30] width 1280 pitch 5120 (/4 1280) >[ 36709.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36709.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36709.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36709.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36709.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fdde0] >[ 36709.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fdde0] width 1280 pitch 5120 (/4 1280) >[ 36709.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36709.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36709.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fdde0] >[ 36709.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fdde0] width 1280 pitch 5120 (/4 1280) >[ 36710.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36710.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36710.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fdde0] >[ 36710.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fdde0] width 1280 pitch 5120 (/4 1280) >[ 36710.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36710.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36710.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fdde0] >[ 36710.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fdde0] width 1280 pitch 5120 (/4 1280) >[ 36714.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36714.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36714.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d920] >[ 36714.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d920] width 1280 pitch 5120 (/4 1280) >[ 36714.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36714.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36714.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d920] >[ 36714.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d920] width 1280 pitch 5120 (/4 1280) >[ 36714.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fb0d0] >[ 36714.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fb0d0] width 1280 pitch 5120 (/4 1280) >[ 36714.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fb0b0] >[ 36714.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fb0b0] width 1280 pitch 5120 (/4 1280) >[ 36714.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fb220] >[ 36714.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fb220] width 1280 pitch 5120 (/4 1280) >[ 36714.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d920] >[ 36714.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d920] width 1280 pitch 5120 (/4 1280) >[ 36714.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fb150] >[ 36714.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fb150] width 1280 pitch 5120 (/4 1280) >[ 36715.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b3a9a0] >[ 36715.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b3a9a0] width 1280 pitch 5120 (/4 1280) >[ 36735.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2e0b0] >[ 36735.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2e0b0] width 1280 pitch 5120 (/4 1280) >[ 36762.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6606400] >[ 36762.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6606400] width 1280 pitch 5120 (/4 1280) >[ 36768.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1c30] >[ 36768.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1c30] width 1280 pitch 5120 (/4 1280) >[ 36769.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66215a0] >[ 36769.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66215a0] width 1280 pitch 5120 (/4 1280) >[ 36769.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36769.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36769.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66215a0] >[ 36769.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66215a0] width 1280 pitch 5120 (/4 1280) >[ 36769.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36769.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36769.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66215a0] >[ 36769.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66215a0] width 1280 pitch 5120 (/4 1280) >[ 36769.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36769.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36769.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66215a0] >[ 36769.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66215a0] width 1280 pitch 5120 (/4 1280) >[ 36770.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36770.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36770.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66215a0] >[ 36770.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66215a0] width 1280 pitch 5120 (/4 1280) >[ 36770.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36770.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36770.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66215a0] >[ 36770.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66215a0] width 1280 pitch 5120 (/4 1280) >[ 36771.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36771.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36771.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66215a0] >[ 36771.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66215a0] width 1280 pitch 5120 (/4 1280) >[ 36772.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36772.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36772.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6609ce0] >[ 36772.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6609ce0] width 1280 pitch 5120 (/4 1280) >[ 36772.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36772.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36774.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1c30] >[ 36774.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1c30] width 1280 pitch 5120 (/4 1280) >[ 36774.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36774.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36774.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349ca30] >[ 36774.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349ca30] width 1280 pitch 5120 (/4 1280) >[ 36774.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6754b10] >[ 36774.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6754b10] width 1280 pitch 5120 (/4 1280) >[ 36784.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a34cd0] >[ 36784.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a34cd0] width 1280 pitch 5120 (/4 1280) >[ 36792.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36792.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36792.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a34cd0] >[ 36792.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a34cd0] width 1280 pitch 5120 (/4 1280) >[ 36792.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349ca30] >[ 36793.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349ca30] width 1280 pitch 5120 (/4 1280) >[ 36793.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36793.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36793.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6611330] >[ 36793.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6611330] width 1280 pitch 5120 (/4 1280) >[ 36793.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36793.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36793.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36793.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36793.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a37d90] >[ 36793.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a37d90] width 1280 pitch 5120 (/4 1280) >[ 36793.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36793.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36793.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a37d90] >[ 36793.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a37d90] width 1280 pitch 5120 (/4 1280) >[ 36793.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36793.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36794.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a37d90] >[ 36794.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a37d90] width 1280 pitch 5120 (/4 1280) >[ 36794.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36794.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36794.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a37d90] >[ 36794.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a37d90] width 1280 pitch 5120 (/4 1280) >[ 36794.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36794.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36794.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54947b0] >[ 36794.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54947b0] width 1280 pitch 5120 (/4 1280) >[ 36794.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6609ce0] >[ 36794.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6609ce0] width 1280 pitch 5120 (/4 1280) >[ 36794.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x66064d0] >[ 36794.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x66064d0] width 1280 pitch 5120 (/4 1280) >[ 36794.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1c30] >[ 36794.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1c30] width 1280 pitch 5120 (/4 1280) >[ 36794.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349ca30] >[ 36794.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349ca30] width 1280 pitch 5120 (/4 1280) >[ 36794.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a2430] >[ 36794.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a2430] width 1280 pitch 5120 (/4 1280) >[ 36794.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349ca30] >[ 36794.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349ca30] width 1280 pitch 5120 (/4 1280) >[ 36794.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6675520] >[ 36795.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6675520] width 1280 pitch 5120 (/4 1280) >[ 36795.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6611330] >[ 36795.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6611330] width 1280 pitch 5120 (/4 1280) >[ 36795.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6675520] >[ 36795.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6675520] width 1280 pitch 5120 (/4 1280) >[ 36943.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 36943.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 36943.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36943.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36943.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34226a0] >[ 36943.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34226a0] width 1280 pitch 5120 (/4 1280) >[ 36943.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36943.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36943.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34226a0] >[ 36944.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34226a0] width 1280 pitch 5120 (/4 1280) >[ 36945.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 36945.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 36945.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 36945.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 36945.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36945.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36945.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 36945.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 36945.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36945.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36945.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36945.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36946.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34226a0] >[ 36946.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34226a0] width 1280 pitch 5120 (/4 1280) >[ 36946.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36946.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36947.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34226a0] >[ 36947.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34226a0] width 1280 pitch 5120 (/4 1280) >[ 36947.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 36947.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 36949.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4715c00] >[ 36949.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4715c00] width 1280 pitch 5120 (/4 1280) >[ 36949.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34226a0] >[ 36949.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34226a0] width 1280 pitch 5120 (/4 1280) >[ 36949.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4715c00] >[ 36949.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4715c00] width 1280 pitch 5120 (/4 1280) >[ 36949.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34226a0] >[ 36949.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34226a0] width 1280 pitch 5120 (/4 1280) >[ 36949.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4715c00] >[ 36949.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4715c00] width 1280 pitch 5120 (/4 1280) >[ 36949.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34226a0] >[ 36949.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34226a0] width 1280 pitch 5120 (/4 1280) >[ 36976.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4715c00] >[ 36976.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4715c00] width 1280 pitch 5120 (/4 1280) >[ 36976.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34226a0] >[ 36976.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34226a0] width 1280 pitch 5120 (/4 1280) >[ 36976.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36976.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36976.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36976.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36976.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d69b0] >[ 36976.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d69b0] width 1280 pitch 5120 (/4 1280) >[ 36977.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4715c00] >[ 36977.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4715c00] width 1280 pitch 5120 (/4 1280) >[ 36977.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d69b0] >[ 36977.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d69b0] width 1280 pitch 5120 (/4 1280) >[ 36977.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d69b0] >[ 36977.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d69b0] width 1280 pitch 5120 (/4 1280) >[ 36977.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 36977.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 36977.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 36977.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 36977.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65fea60] >[ 36977.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65fea60] width 1280 pitch 5120 (/4 1280) >[ 36977.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d69b0] >[ 36977.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d69b0] width 1280 pitch 5120 (/4 1280) >[ 36977.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d69b0] >[ 36977.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d69b0] width 1280 pitch 5120 (/4 1280) >[ 36977.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d69b0] >[ 36978.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d69b0] width 1280 pitch 5120 (/4 1280) >[ 36978.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d69b0] >[ 36978.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d69b0] width 1280 pitch 5120 (/4 1280) >[ 37114.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a31a40] >[ 37114.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a31a40] width 1280 pitch 5120 (/4 1280) >[ 37120.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c203a0] >[ 37120.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c203a0] width 1280 pitch 5120 (/4 1280) >[ 37139.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b9a530] >[ 37139.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b9a530] width 1280 pitch 5120 (/4 1280) >[ 37151.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2fda0] >[ 37151.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2fda0] width 1280 pitch 5120 (/4 1280) >[ 37151.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b9a770] >[ 37151.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b9a770] width 1280 pitch 5120 (/4 1280) >[ 37151.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2fda0] >[ 37152.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2fda0] width 1280 pitch 5120 (/4 1280) >[ 37152.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a32530] >[ 37152.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a32530] width 1280 pitch 5120 (/4 1280) >[ 37152.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 37152.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 37183.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37183.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37184.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2fda0] >[ 37184.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2fda0] width 1280 pitch 5120 (/4 1280) >[ 37184.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37184.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37184.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2fda0] >[ 37184.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2fda0] width 1280 pitch 5120 (/4 1280) >[ 37184.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37184.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37184.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2fda0] >[ 37184.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2fda0] width 1280 pitch 5120 (/4 1280) >[ 37185.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37185.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37186.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2fda0] >[ 37186.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2fda0] width 1280 pitch 5120 (/4 1280) >[ 37186.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37186.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37186.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2fda0] >[ 37186.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2fda0] width 1280 pitch 5120 (/4 1280) >[ 37186.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37186.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37186.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 37186.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 37187.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e9a40] >[ 37187.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e9a40] width 1280 pitch 5120 (/4 1280) >[ 37188.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af2cd0] >[ 37188.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af2cd0] width 1280 pitch 5120 (/4 1280) >[ 37188.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 37188.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 37188.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5af2cd0] >[ 37188.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5af2cd0] width 1280 pitch 5120 (/4 1280) >[ 37191.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37191.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37191.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab4550] >[ 37191.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab4550] width 1280 pitch 5120 (/4 1280) >[ 37191.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37192.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37192.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab4550] >[ 37192.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab4550] width 1280 pitch 5120 (/4 1280) >[ 37192.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37192.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37192.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab4550] >[ 37192.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab4550] width 1280 pitch 5120 (/4 1280) >[ 37192.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a46490] >[ 37192.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a46490] width 1280 pitch 5120 (/4 1280) >[ 37193.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b9a770] >[ 37193.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b9a770] width 1280 pitch 5120 (/4 1280) >[ 37193.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 37193.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 37193.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b9a770] >[ 37194.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b9a770] width 1280 pitch 5120 (/4 1280) >[ 37194.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e9a40] >[ 37194.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e9a40] width 1280 pitch 5120 (/4 1280) >[ 37194.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b9a770] >[ 37194.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b9a770] width 1280 pitch 5120 (/4 1280) >[ 37194.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e9a40] >[ 37194.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e9a40] width 1280 pitch 5120 (/4 1280) >[ 37195.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b9a770] >[ 37195.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b9a770] width 1280 pitch 5120 (/4 1280) >[ 37195.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e9a40] >[ 37195.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e9a40] width 1280 pitch 5120 (/4 1280) >[ 37196.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x65e9a40] >[ 37196.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x65e9a40] width 1280 pitch 5120 (/4 1280) >[ 37196.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 37196.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 37197.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 37197.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 37197.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab4550] >[ 37197.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab4550] width 1280 pitch 5120 (/4 1280) >[ 37197.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a52370] >[ 37198.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a52370] width 1280 pitch 5120 (/4 1280) >[ 37199.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab4550] >[ 37199.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab4550] width 1280 pitch 5120 (/4 1280) >[ 37199.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x7b9a770] >[ 37199.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x7b9a770] width 1280 pitch 5120 (/4 1280) >[ 37384.914] [mi] EQ overflowing. Additional events will be discarded until existing events are processed. >[ 37384.915] >[ 37384.915] Backtrace: >[ 37385.319] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326] >[ 37385.319] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x55155b] >[ 37385.319] 2: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22] >[ 37385.640] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7fa3823b8000+0x60e4) [0x7fa3823be0e4] >[ 37385.640] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817] >[ 37385.640] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00] >[ 37385.640] 6: /lib64/libpthread.so.0 (0x3da0a00000+0xefe0) [0x3da0a0efe0] >[ 37385.640] 7: /lib64/libc.so.6 (0x3da0600000+0x7b987) [0x3da067b987] >[ 37385.640] 8: /usr/bin/Xorg (0x400000+0x4e729) [0x44e729] >[ 37385.640] 9: /usr/bin/Xorg (0x400000+0x4bbf5) [0x44bbf5] >[ 37385.640] 10: /usr/bin/Xorg (DeletePassiveGrab+0x56) [0x44be46] >[ 37385.640] 11: /usr/bin/Xorg (0x400000+0x554a2) [0x4554a2] >[ 37385.640] 12: /usr/bin/Xorg (FreeClientResources+0x95) [0x4562a5] >[ 37385.640] 13: /usr/bin/Xorg (CloseDownClient+0x5a) [0x4338aa] >[ 37385.640] 14: /usr/bin/Xorg (0x400000+0x3434f) [0x43434f] >[ 37385.640] 15: /usr/bin/Xorg (0x400000+0x23475) [0x423475] >[ 37385.640] 16: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3da0621735] >[ 37385.640] 17: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d] >[ 37385.640] >[ 37385.640] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack. >[ 37385.640] [mi] mieq is *NOT* the cause. It is a victim. >[ 37387.007] [mi] Increasing EQ size to 1024 to prevent dropped events. >[ 37387.022] [mi] EQ processing has resumed after 33 dropped events. >[ 37387.022] [mi] This may be caused my a misbehaving driver monopolizing the server's resources. >[ 37388.654] (II) evdev: Power Button: Close >[ 37388.813] (II) UnloadModule: "evdev" >[ 37388.856] (II) evdev: Power Button: Close >[ 37388.882] (II) UnloadModule: "evdev" >[ 37388.887] (II) evdev: Logitech Logitech USB Keyboard: Close >[ 37388.887] (II) UnloadModule: "evdev" >[ 37388.897] (II) evdev: A4Tech USB Mouse: Close >[ 37388.897] (II) UnloadModule: "evdev" >[ 37389.621] (II) RADEON(0): RADEONCloseScreen >[ 37389.952] Server terminated successfully (0). Closing log file.
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