Attachment 673241 Details for Bug 892240 – host cpuid

host cpuid

cpuid.txt (text/plain), 318.59 KB, created by Mark Wu on 2013-01-06 04:04:14 UTC

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Creator: Mark Wu

Created: 2013-01-06 04:04:14 UTC

Size: 318.59 KB

patch

obsolete

>CPU 0:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x0 (0)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 0
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 0
>   hypervisor_id = "           "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 1:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x2 (2)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 2
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 2
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 2:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x4 (4)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 4
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 4
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 3:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x10 (16)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 16
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 16
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 4:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x12 (18)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 18
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 18
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 5:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x14 (20)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 20
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 20
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 6:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x20 (32)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 32
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 32
>   hypervisor_id = "           "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=16 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 7:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x22 (34)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 34
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 34
>   hypervisor_id = "       "   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=17 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 8:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x24 (36)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 36
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 36
>   hypervisor_id = "       $   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=18 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 9:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x30 (48)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 48
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 48
>   hypervisor_id = "       0   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=24 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 10:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x32 (50)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 50
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 50
>   hypervisor_id = "       2   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=25 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 11:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x34 (52)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 52
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 52
>   hypervisor_id = "       4   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=26 SMT_ID=0
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 12:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x1 (1)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 1
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 1
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 13:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x3 (3)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 3
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 3
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 14:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x5 (5)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 5
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 5
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 15:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x11 (17)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 17
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 17
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 16:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x13 (19)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 19
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 19
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 17:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x15 (21)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 21
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 21
>   hypervisor_id = "          "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 18:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x21 (33)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 33
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 33
>   hypervisor_id = "       !   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=16 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 19:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x23 (35)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 35
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 35
>   hypervisor_id = "       #   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=17 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 20:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x25 (37)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 37
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 37
>   hypervisor_id = "       %   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=18 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 21:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x31 (49)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 49
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 49
>   hypervisor_id = "       1   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=24 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 22:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x33 (51)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 51
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 51
>   hypervisor_id = "       3   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=25 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>CPU 23:
>   vendor_id = "GenuineIntel"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
>      model           = 0xc (12)
>      stepping id     = 0x2 (2)
>      extended family = 0x0 (0)
>      extended model  = 0x2 (2)
>      (simple synth)  = Intel Core i7-900 (Gulftown B1) / Core i7-980X (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x35 (53)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      virtual-8086 mode enhancement          = true
>      debugging extensions                   = true
>      page size extensions                   = true
>      time stamp counter                     = true
>      RDMSR and WRMSR support                = true
>      physical address extensions            = true
>      machine check exception                = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      memory type range registers            = true
>      PTE global bit                         = true
>      machine check architecture             = true
>      conditional move/compare instruction   = true
>      page attribute table                   = true
>      page size extension                    = true
>      processor serial number                = false
>      CLFLUSH instruction                    = true
>      debug store                            = true
>      thermal monitor and clock ctrl         = true
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      self snoop                             = true
>      hyper-threading / multi-core supported = true
>      therm. monitor                         = true
>      IA64                                   = false
>      pending break event                    = true
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      64-bit debug store                      = true
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = true
>      VMX: virtual machine extensions         = true
>      SMX: safer mode extensions              = true
>      Enhanced Intel SpeedStep Technology     = true
>      thermal monitor 2                       = true
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      FMA instruction                         = false
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = true
>      perfmon and debug                       = true
>      process context identifiers             = true
>      direct cache access                     = true
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      extended xAPIC support                  = false
>      MOVBE instruction                       = false
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = false
>      OS-enabled XSAVE/XSTOR                  = false
>      AVX: advanced vector extensions         = false
>      F16C half-precision convert instruction = false
>      RDRAND instruction                      = false
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
>      0x03: data TLB: 4K pages, 4-way, 64 entries
>      0x55: instruction TLB: 2M/4M pages, fully, 7 entries
>      0xff: cache data is in CPUID 4
>      0xb2: instruction TLB: 4K, 4-way, 64 entries
>      0xf0: 64 byte prefetching
>      0xca: L2 TLB: 4K, 4-way, 512 entries
>   processor serial number: 0002-06C2-0000-0000-0000-0000
>   deterministic cache parameters (4):
>      --- cache 0 ---
>      cache type                           = data cache (1)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 63
>      --- cache 1 ---
>      cache type                           = instruction cache (2)
>      cache level                          = 0x1 (1)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x3 (3)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 127
>      --- cache 2 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x2 (2)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1 (1)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0x7 (7)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = false
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 511
>      --- cache 3 ---
>      cache type                           = unified cache (3)
>      cache level                          = 0x3 (3)
>      self-initializing cache level        = true
>      fully associative cache              = false
>      extra threads sharing this cache     = 0x1f (31)
>      extra processor cores on this die    = 0xf (15)
>      system coherency line size           = 0x3f (63)
>      physical line partitions             = 0x0 (0)
>      ways of associativity                = 0xf (15)
>      WBINVD/INVD behavior on lower caches = false
>      inclusive to lower caches            = true
>      complex cache indexing               = false
>      number of sets - 1 (s)               = 12287
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x0 (0)
>      number of C1 sub C-states using MWAIT    = 0x2 (2)
>      number of C2 sub C-states using MWAIT    = 0x1 (1)
>      number of C3/C6 sub C-states using MWAIT = 0x1 (1)
>      number of C4/C7 sub C-states using MWAIT = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = true
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      digital thermometer thresholds          = 0x2 (2)
>      ACNT/MCNT supported performance measure = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = true
>   extended feature flags (7):
>      FSGSBASE instructions                   = false
>      BMI instruction                         = false
>      SMEP support                            = false
>      enhanced REP MOVSB/STOSB                = false
>      INVPCID instruction                     = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x3 (3)
>      number of counters per logical processor = 0x4 (4)
>      bit width of counter                     = 0x30 (48)
>      length of EBX bit vector                 = 0x7 (7)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = true
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x3 (3)
>      bit width of fixed counters = 0x30 (48)
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 53
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x5 (5)
>      logical processors at this level  = 0xc (12)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 53
>   hypervisor_id = "       5   "
>   extended feature flags (0x80000001/edx):
>      SYSCALL and SYSRET instructions        = true
>      execution disable                      = true
>      1-GB large page support                = true
>      RDTSCP                                 = true
>      64-bit extensions technology available = true
>   Intel feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode = true
>   brand = "Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz"
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = 0x0 (0)
>      data # entries            = 0x0 (0)
>      data associativity        = 0x0 (0)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x0 (0)
>      lines per tag     = 0x0 (0)
>      associativity     = 0x0 (0)
>      size (Kb)         = 0x0 (0)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x0 (0)
>      associativity     = 8-way (6)
>      size (Kb)         = 0x100 (256)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x0 (0)
>      lines per tag         = 0x0 (0)
>      associativity         = L2 off (0)
>      size (in 512Kb units) = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      temperature sensing diode      = false
>      frequency ID (FID) control     = false
>      voltage ID (VID) control       = false
>      thermal trip (TTP)             = false
>      thermal monitor (TM)           = false
>      software thermal control (STC) = false
>      100 MHz multiplier control     = false
>      hardware P-State control       = false
>      TscInvariant                   = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x28 (40)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x0 (0)
>      ApicIdCoreIdSize        = 0x0 (0)
>   (multi-processing synth): multi-core (c=6), hyper-threaded (t=2)
>   (multi-processing method): Intel leaf 0xb
>   (APIC widths synth): CORE_width=5 SMT_width=1
>   (APIC synth): PKG_ID=0 CORE_ID=26 SMT_ID=1
>   (synth) = Intel Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Westmere-EP B1), 32nm

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Attachments on bug 892240: 673241