Attachment 698798 Details for Bug 912285 – File: Xorg.0.log

File: Xorg.0.log

Xorg.0.log (text/plain), 620.62 KB, created by Mohamed Tangour on 2013-02-18 09:59:35 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Mohamed Tangour

Created: 2013-02-18 09:59:35 UTC

Size: 620.62 KB

patch

obsolete

>[    50.050] 
>X.Org X Server 1.12.4
>Release Date: 2012-08-27
>[    50.050] X Protocol Version 11, Revision 0
>[    50.050] Build Operating System:  2.6.32-279.9.1.el6.x86_64 
>[    50.050] Current Operating System: Linux GlobalTIC 3.7.3-101.fc17.x86_64 #1 SMP Fri Jan 18 17:40:57 UTC 2013 x86_64
>[    50.050] Kernel command line: BOOT_IMAGE=/vmlinuz-3.7.3-101.fc17.x86_64 root=UUID=aac5b510-db1e-4703-b87e-70da84ff2b24 ro rd.md=0 rd.lvm=0 rd.dm=0 SYSFONT=True rd.luks=0 KEYTABLE=fr-latin9 LANG=fr_FR.UTF-8 rhgb quiet
>[    50.050] Build Date: 14 December 2012  08:13:38PM
>[    50.050] Build ID: xorg-x11-server 1.12.4-2.fc17 
>[    50.050] Current version of pixman: 0.24.4
>[    50.050] 	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>[    50.050] Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>[    50.050] (==) Log file: "/var/log/Xorg.0.log", Time: Sun Feb 17 14:52:02 2013
>[    50.051] (==) Using config directory: "/etc/X11/xorg.conf.d"
>[    50.051] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
>[    50.051] (==) No Layout section.  Using the first Screen section.
>[    50.051] (==) No screen section available. Using defaults.
>[    50.051] (**) |-->Screen "Default Screen Section" (0)
>[    50.051] (**) |   |-->Monitor "<default monitor>"
>[    50.051] (==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>[    50.051] (==) Automatically adding devices
>[    50.051] (==) Automatically enabling devices
>[    50.051] (==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>[    50.051] (==) ModulePath set to "/usr/lib64/xorg/modules"
>[    50.051] (II) The server relies on udev to provide the list of input devices.
>	If no devices become available, reconfigure udev or disable AutoAddDevices.
>[    50.051] (II) Loader magic: 0x7c6ac0
>[    50.051] (II) Module ABI versions:
>[    50.051] 	X.Org ANSI C Emulation: 0.4
>[    50.051] 	X.Org Video Driver: 12.1
>[    50.051] 	X.Org XInput driver : 16.0
>[    50.051] 	X.Org Server Extension : 6.0
>[    50.052] (--) PCI:*(0:1:0:0) 1002:95c2:104d:9045 rev 0, Mem @ 0xc0000000/268435456, 0xd0020000/65536, I/O @ 0x0000d000/256, BIOS @ 0x????????/131072
>[    50.053] (II) LoadModule: "extmod"
>[    50.070] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so
>[    50.071] (II) Module extmod: vendor="X.Org Foundation"
>[    50.071] 	compiled for 1.12.4, module version = 1.0.0
>[    50.071] 	Module class: X.Org Server Extension
>[    50.071] 	ABI class: X.Org Server Extension, version 6.0
>[    50.071] (II) Loading extension SELinux
>[    50.071] (II) Loading extension MIT-SCREEN-SAVER
>[    50.071] (II) Loading extension XFree86-VidModeExtension
>[    50.071] (II) Loading extension XFree86-DGA
>[    50.071] (II) Loading extension DPMS
>[    50.071] (II) Loading extension XVideo
>[    50.072] (II) Loading extension XVideo-MotionCompensation
>[    50.072] (II) Loading extension X-Resource
>[    50.072] (II) LoadModule: "dbe"
>[    50.072] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so
>[    50.072] (II) Module dbe: vendor="X.Org Foundation"
>[    50.072] 	compiled for 1.12.4, module version = 1.0.0
>[    50.072] 	Module class: X.Org Server Extension
>[    50.072] 	ABI class: X.Org Server Extension, version 6.0
>[    50.072] (II) Loading extension DOUBLE-BUFFER
>[    50.072] (II) LoadModule: "glx"
>[    50.072] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so
>[    50.072] (II) Module glx: vendor="X.Org Foundation"
>[    50.072] 	compiled for 1.12.4, module version = 1.0.0
>[    50.072] 	ABI class: X.Org Server Extension, version 6.0
>[    50.072] (==) AIGLX enabled
>[    50.072] (II) Loading extension GLX
>[    50.072] (II) LoadModule: "record"
>[    50.072] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so
>[    50.073] (II) Module record: vendor="X.Org Foundation"
>[    50.073] 	compiled for 1.12.4, module version = 1.13.0
>[    50.073] 	Module class: X.Org Server Extension
>[    50.073] 	ABI class: X.Org Server Extension, version 6.0
>[    50.073] (II) Loading extension RECORD
>[    50.073] (II) LoadModule: "dri"
>[    50.073] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so
>[    50.073] (II) Module dri: vendor="X.Org Foundation"
>[    50.073] 	compiled for 1.12.4, module version = 1.0.0
>[    50.073] 	ABI class: X.Org Server Extension, version 6.0
>[    50.073] (II) Loading extension XFree86-DRI
>[    50.073] (II) LoadModule: "dri2"
>[    50.073] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so
>[    50.073] (II) Module dri2: vendor="X.Org Foundation"
>[    50.073] 	compiled for 1.12.4, module version = 1.2.0
>[    50.073] 	ABI class: X.Org Server Extension, version 6.0
>[    50.073] (II) Loading extension DRI2
>[    50.073] (==) Matched ati as autoconfigured driver 0
>[    50.073] (==) Matched vesa as autoconfigured driver 1
>[    50.073] (==) Matched modesetting as autoconfigured driver 2
>[    50.073] (==) Matched fbdev as autoconfigured driver 3
>[    50.073] (==) Assigned the driver to the xf86ConfigLayout
>[    50.073] (II) LoadModule: "ati"
>[    50.074] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so
>[    50.074] (II) Module ati: vendor="X.Org Foundation"
>[    50.074] 	compiled for 1.12.0, module version = 6.14.99
>[    50.074] 	Module class: X.Org Video Driver
>[    50.074] 	ABI class: X.Org Video Driver, version 12.0
>[    50.074] (II) LoadModule: "radeon"
>[    50.074] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so
>[    50.074] (II) Module radeon: vendor="X.Org Foundation"
>[    50.074] 	compiled for 1.12.0, module version = 6.14.99
>[    50.074] 	Module class: X.Org Video Driver
>[    50.074] 	ABI class: X.Org Video Driver, version 12.0
>[    50.074] (II) LoadModule: "vesa"
>[    50.074] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so
>[    50.074] (II) Module vesa: vendor="X.Org Foundation"
>[    50.074] 	compiled for 1.12.0, module version = 2.3.1
>[    50.074] 	Module class: X.Org Video Driver
>[    50.074] 	ABI class: X.Org Video Driver, version 12.0
>[    50.074] (II) LoadModule: "modesetting"
>[    50.075] (WW) Warning, couldn't open module modesetting
>[    50.075] (II) UnloadModule: "modesetting"
>[    50.075] (II) Unloading modesetting
>[    50.075] (EE) Failed to load module "modesetting" (module does not exist, 0)
>[    50.075] (II) LoadModule: "fbdev"
>[    50.075] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so
>[    50.075] (II) Module fbdev: vendor="X.Org Foundation"
>[    50.075] 	compiled for 1.11.99.901, module version = 0.4.2
>[    50.075] 	ABI class: X.Org Video Driver, version 12.0
>[    50.075] (II) RADEON: Driver for ATI Radeon chipsets:
>	ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI),
>	ATI Radeon Mobility X300 (M24) 3152 (PCIE),
>	ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI),
>	ATI Radeon X600 (RV380) 3E50 (PCIE),
>	ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136,
>	ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP),
>	ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP),
>	ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP),
>	ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP),
>	ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP),
>	ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP),
>	ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650,
>	ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237,
>	ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336,
>	ATI Radeon IGP330M/340M/350M (U2) 4337,
>	ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI),
>	ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP),
>	ATI Radeon X800PRO (R420) JI (AGP),
>	ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP),
>	ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP),
>	ATI Radeon Mobility 9800 (M18) JN (AGP),
>	ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP),
>	ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP),
>	ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP),
>	ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP),
>	ATI Radeon Mobility M7 LW (AGP),
>	ATI Mobility FireGL 7800 M7 LX (AGP),
>	ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP),
>	ATI FireGL Mobility 9000 (M9) Ld (AGP),
>	ATI Radeon Mobility 9000 (M9) Lf (AGP),
>	ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI,
>	ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP),
>	ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP),
>	ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP),
>	ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP),
>	ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP),
>	ATI Radeon Mobility 9600 (M10) NQ (AGP),
>	ATI Radeon Mobility 9600 (M11) NR (AGP),
>	ATI Radeon Mobility 9600 (M10) NS (AGP),
>	ATI FireGL Mobility T2 (M10) NT (AGP),
>	ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP),
>	ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP),
>	ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP),
>	ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI),
>	ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI),
>	ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI),
>	ATI Radeon Mobility X300 (M22) 5460 (PCIE),
>	ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE),
>	ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE),
>	ATI Radeon X800PRO (R423) UI (PCIE),
>	ATI Radeon X800LE (R423) UJ (PCIE),
>	ATI Radeon X800SE (R423) UK (PCIE),
>	ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE),
>	ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE),
>	ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE),
>	ATI FireGL unknown (R423) UR (PCIE),
>	ATI FireGL unknown (R423) UT (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility Radeon X700 XL (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834,
>	ATI Radeon Mobility 9100 IGP (U3) 5835,
>	ATI Radeon XPRESS 200 5954 (PCIE),
>	ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP),
>	ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP),
>	ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI),
>	ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE),
>	ATI Radeon XPRESS 200M 5975 (PCIE),
>	ATI Radeon XPRESS 200 5A41 (PCIE),
>	ATI Radeon XPRESS 200M 5A42 (PCIE),
>	ATI Radeon XPRESS 200 5A61 (PCIE),
>	ATI Radeon XPRESS 200M 5A62 (PCIE),
>	ATI Radeon X300 (RV370) 5B60 (PCIE),
>	ATI Radeon X600 (RV370) 5B62 (PCIE),
>	ATI Radeon X550 (RV370) 5B63 (PCIE),
>	ATI FireGL V3100 (RV370) 5B64 (PCIE),
>	ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE),
>	ATI Radeon Mobility 9200 (M9+) 5C61 (AGP),
>	ATI Radeon Mobility 9200 (M9+) 5C63 (AGP),
>	ATI Mobility Radeon X800 XT (M28) (PCIE),
>	ATI Mobility FireGL V5100 (M28) (PCIE),
>	ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE),
>	ATI Radeon X850 XT PE (R480) (PCIE),
>	ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE),
>	ATI unknown Radeon / FireGL (R480) 5D50 (PCIE),
>	ATI Radeon X850 XT (R480) (PCIE),
>	ATI Radeon X800XT (R423) 5D57 (PCIE),
>	ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE),
>	ATI Radeon X700 PRO (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800,
>	ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800,
>	ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300,
>	ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800,
>	ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800,
>	ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505,
>	ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL,
>	ATI Mobility Radeon X1400, ATI Radeon X1300/X1550,
>	ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300,
>	ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350,
>	ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550,
>	ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450,
>	ATI Radeon X1300/X1550, ATI Mobility Radeon X2300,
>	ATI Mobility Radeon X2300, ATI Mobility Radeon X1350,
>	ATI Mobility Radeon X1350, ATI Mobility Radeon X1450,
>	ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350,
>	ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600,
>	ATI Mobility FireGL V5200, ATI Mobility Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600,
>	ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400,
>	ATI Mobility FireGL V5250, ATI Mobility Radeon X1700,
>	ATI Mobility Radeon X1700 XT, ATI FireGL V5200,
>	ATI Mobility Radeon X1700, ATI Radeon X2300HD,
>	ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300,
>	ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950,
>	ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560,
>	ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400,
>	ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560,
>	ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835,
>	ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200,
>	ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740,
>	ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT,
>	ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT,
>	ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600,
>	ATI Radeon 4800 Series, ATI Radeon HD 4870 x2,
>	ATI Radeon 4800 Series, ATI Radeon HD 4850 x2,
>	ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL),
>	ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2,
>	ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270,
>	AMD FireStream 9250, ATI FirePro V8700 (FireGL),
>	ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98,
>	ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series,
>	ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98,
>	ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP),
>	ATI Mobility Radeon HD 4670, ATI FirePro M5750,
>	ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP),
>	ATI RV730XT [Radeon HD 4670], ATI RADEON E4600,
>	ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650],
>	ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL),
>	ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830,
>	ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740,
>	ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770,
>	ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT,
>	ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000,
>	ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT,
>	ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610,
>	ATI FireMV 2260, ATI RV670, ATI Radeon HD3870,
>	ATI Mobility Radeon HD 3850, ATI Radeon HD3850,
>	ATI Mobility Radeon HD 3850 X2, ATI RV670,
>	ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2,
>	ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850,
>	ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550,
>	ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710,
>	ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series,
>	ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series,
>	ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630,
>	ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT,
>	ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP,
>	ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630,
>	ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600,
>	ATI FireGL V3600, ATI Radeon HD 2600 LE,
>	ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470,
>	ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series,
>	ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430,
>	ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450,
>	ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series,
>	ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO,
>	ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO,
>	ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670,
>	ATI Mobility FireGL V5700, ATI Mobility FireGL V5725,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics,
>	ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2,
>	SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200,
>	ATI Radeon 4100, ATI Mobility Radeon HD 4200,
>	ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250,
>	AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics,
>	AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics,
>	AMD Radeon HD 6300 Series Graphics,
>	AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370,
>	AMD Firestream 9350, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series,
>	ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series,
>	ATI Mobility Radeon HD 5800 Series,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670,
>	ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics,
>	ATI Mobility Radeon Graphics, CEDAR,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR,
>	ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN,
>	CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series,
>	BARTS, BARTS, Mobility Radeon HD 6000 Series,
>	Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS,
>	AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series,
>	AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA,
>	ARUBA, ARUBA, ARUBA, ARUBA
>[    50.086] (II) VESA: driver for VESA chipsets: vesa
>[    50.086] (II) FBDEV: driver for framebuffer: fbdev
>[    50.086] (++) using VT number 1
>
>[    50.086] (II) [KMS] Kernel modesetting enabled.
>[    50.086] (WW) Falling back to old probe method for vesa
>[    50.086] (WW) Falling back to old probe method for fbdev
>[    50.086] (II) Loading sub module "fbdevhw"
>[    50.086] (II) LoadModule: "fbdevhw"
>[    50.087] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so
>[    50.087] (II) Module fbdevhw: vendor="X.Org Foundation"
>[    50.087] 	compiled for 1.12.4, module version = 0.0.2
>[    50.087] 	ABI class: X.Org Video Driver, version 12.1
>[    50.087] (II) RADEON(0): RADEONPreInit_KMS
>[    50.087] (II) RADEON(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>[    50.087] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32
>[    50.087] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
>[    50.087] (==) RADEON(0): Default visual is TrueColor
>[    50.087] (==) RADEON(0): RGB weight 888
>[    50.087] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC)
>[    50.087] (--) RADEON(0): Chipset: "ATI Mobility Radeon HD 3430" (ChipID = 0x95c2)
>[    50.087] (II) RADEON(0): PCIE card detected
>[    50.087] drmOpenDevice: node name is /dev/dri/card0
>[    50.087] drmOpenDevice: open result is 8, (OK)
>[    50.087] drmOpenByBusid: Searching for BusID pci:0000:01:00.0
>[    50.087] drmOpenDevice: node name is /dev/dri/card0
>[    50.087] drmOpenDevice: open result is 8, (OK)
>[    50.087] drmOpenByBusid: drmOpenMinor returns 8
>[    50.087] drmOpenByBusid: drmGetBusid reports pci:0000:01:00.0
>[    50.087] (II) Loading sub module "exa"
>[    50.087] (II) LoadModule: "exa"
>[    50.087] (II) Loading /usr/lib64/xorg/modules/libexa.so
>[    50.088] (II) Module exa: vendor="X.Org Foundation"
>[    50.088] 	compiled for 1.12.4, module version = 2.5.0
>[    50.088] 	ABI class: X.Org Video Driver, version 12.1
>[    50.088] (II) RADEON(0): KMS Color Tiling: enabled
>[    50.088] (II) RADEON(0): KMS Pageflipping: enabled
>[    50.088] (II) RADEON(0): SwapBuffers wait for vsync: enabled
>[    50.129] (II) RADEON(0): Output VGA-0 has no monitor section
>[    50.129] (II) RADEON(0): Output LVDS has no monitor section
>[    50.173] (II) RADEON(0): EDID for output VGA-0
>[    50.173] (II) RADEON(0): Manufacturer: FUS  Model: 7df  Serial#: 1
>[    50.173] (II) RADEON(0): Year: 2010  Week: 6
>[    50.173] (II) RADEON(0): EDID Version: 1.3
>[    50.173] (II) RADEON(0): Analog Display Input,  Input Voltage Level: 0.700/0.700 V
>[    50.173] (II) RADEON(0): Sync:  Separate
>[    50.173] (II) RADEON(0): Max Image Size [cm]: horiz.: 44  vert.: 25
>[    50.173] (II) RADEON(0): Gamma: 2.30
>[    50.173] (II) RADEON(0): DPMS capabilities: Off; RGB/Color Display
>[    50.173] (II) RADEON(0): First detailed timing is preferred mode
>[    50.173] (II) RADEON(0): redX: 0.644 redY: 0.333   greenX: 0.286 greenY: 0.605
>[    50.173] (II) RADEON(0): blueX: 0.152 blueY: 0.076   whiteX: 0.313 whiteY: 0.329
>[    50.173] (II) RADEON(0): Supported established timings:
>[    50.173] (II) RADEON(0): 720x400@70Hz
>[    50.173] (II) RADEON(0): 640x480@60Hz
>[    50.173] (II) RADEON(0): 640x480@75Hz
>[    50.173] (II) RADEON(0): 800x600@60Hz
>[    50.173] (II) RADEON(0): 800x600@75Hz
>[    50.173] (II) RADEON(0): 1024x768@60Hz
>[    50.173] (II) RADEON(0): 1024x768@75Hz
>[    50.173] (II) RADEON(0): Manufacturer's mask: 0
>[    50.173] (II) RADEON(0): Supported standard timings:
>[    50.173] (II) RADEON(0): #0: hsize: 1280  vsize 720  refresh: 60  vid: 49281
>[    50.173] (II) RADEON(0): Supported detailed timing:
>[    50.173] (II) RADEON(0): clock: 97.8 MHz   Image Size:  442 x 249 mm
>[    50.173] (II) RADEON(0): h_active: 1600  h_sync: 1648  h_sync_end 1680 h_blank_end 1760 h_border: 0
>[    50.173] (II) RADEON(0): v_active: 900  v_sync: 903  v_sync_end 908 v_blanking: 926 v_border: 0
>[    50.173] (II) RADEON(0): Monitor name: L20T-1 ECO
>[    50.173] (II) RADEON(0): Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 82 kHz, PixClock max 165 MHz
>[    50.173] (II) RADEON(0): Serial No: YV3J703671
>[    50.173] (II) RADEON(0): EDID (in hex):
>[    50.173] (II) RADEON(0): 	00ffffffffffff001ab3df0701000000
>[    50.173] (II) RADEON(0): 	06140103682c19822ad425a455499b27
>[    50.173] (II) RADEON(0): 	135054a54a0081c00101010101010101
>[    50.173] (II) RADEON(0): 	0101010101012f2640a060841a303020
>[    50.173] (II) RADEON(0): 	3500baf91000001a000000fc004c3230
>[    50.173] (II) RADEON(0): 	542d312045434f0a2020000000fd0038
>[    50.173] (II) RADEON(0): 	4c1e5210000a202020202020000000ff
>[    50.173] (II) RADEON(0): 	005956334a3730333637310a2020000f
>[    50.173] (II) RADEON(0): EDID vendor "FUS", prod id 2015
>[    50.173] (II) RADEON(0): Using EDID range info for horizontal sync
>[    50.173] (II) RADEON(0): Using EDID range info for vertical refresh
>[    50.173] (II) RADEON(0): Printing DDC gathered Modelines:
>[    50.173] (II) RADEON(0): Modeline "1600x900"x0.0   97.75  1600 1648 1680 1760  900 903 908 926 +hsync -vsync (55.5 kHz eP)
>[    50.173] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    50.173] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    50.173] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    50.173] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    50.173] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1280x720"x60.0   74.48  1280 1336 1472 1664  720 721 724 746 -hsync +vsync (44.8 kHz e)
>[    50.173] (II) RADEON(0): Printing probed modes for output VGA-0
>[    50.173] (II) RADEON(0): Modeline "1600x900"x60.0   97.75  1600 1648 1680 1760  900 903 908 926 +hsync -vsync (55.5 kHz eP)
>[    50.173] (II) RADEON(0): Modeline "1440x900"x75.0  136.75  1440 1536 1688 1936  900 903 909 942 -hsync +vsync (70.6 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1440x900"x59.9  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1366x768"x60.0   85.89  1366 1439 1583 1800  768 769 772 795 -hsync +vsync (47.7 kHz)
>[    50.173] (II) RADEON(0): Modeline "1360x768"x60.0   85.50  1360 1424 1536 1792  768 771 777 795 +hsync +vsync (47.7 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1280x800"x74.9  106.50  1280 1360 1488 1696  800 803 809 838 -hsync +vsync (62.8 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1280x800"x59.8   83.50  1280 1352 1480 1680  800 803 809 831 +hsync -vsync (49.7 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1152x864"x75.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1280x768"x74.9  102.25  1280 1360 1488 1696  768 771 778 805 +hsync -vsync (60.3 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1280x768"x59.9   79.50  1280 1344 1472 1664  768 771 778 798 -hsync +vsync (47.8 kHz e)
>[    50.173] (II) RADEON(0): Modeline "1280x720"x60.0   74.44  1280 1336 1472 1664  720 721 724 746 -hsync +vsync (44.7 kHz)
>[    50.174] (II) RADEON(0): Modeline "1024x768"x75.1   78.80  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.1 kHz e)
>[    50.174] (II) RADEON(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    50.174] (II) RADEON(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    50.174] (II) RADEON(0): Modeline "1024x576"x60.0   46.97  1024 1064 1168 1312  576 577 580 597 -hsync +vsync (35.8 kHz)
>[    50.174] (II) RADEON(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    50.174] (II) RADEON(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    50.174] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    50.174] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    50.174] (II) RADEON(0): Modeline "848x480"x60.0   33.75  848 864 976 1088  480 486 494 517 +hsync +vsync (31.0 kHz e)
>[    50.174] (II) RADEON(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[    50.174] (II) RADEON(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    50.174] (II) RADEON(0): Modeline "640x480"x60.0   25.20  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    50.174] (II) RADEON(0): Modeline "720x400"x70.1   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    50.174] (II) RADEON(0): EDID for output LVDS
>[    50.174] (II) RADEON(0): Printing probed modes for output LVDS
>[    50.174] (II) RADEON(0): Modeline "1280x800"x59.8   68.00  1280 1312 1376 1408  800 802 804 808 -hsync -vsync (48.3 kHz eP)
>[    50.174] (II) RADEON(0): Modeline "1280x720"x59.9   74.50  1280 1344 1472 1664  720 723 728 748 -hsync +vsync (44.8 kHz)
>[    50.174] (II) RADEON(0): Modeline "1152x768"x59.8   71.75  1152 1216 1328 1504  768 771 781 798 -hsync +vsync (47.7 kHz)
>[    50.174] (II) RADEON(0): Modeline "1024x768"x120.1  133.47  1024 1100 1212 1400  768 768 770 794 doublescan -hsync +vsync (95.3 kHz d)
>[    50.174] (II) RADEON(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz d)
>[    50.174] (II) RADEON(0): Modeline "1024x768"x59.9   63.50  1024 1072 1176 1328  768 771 775 798 -hsync +vsync (47.8 kHz)
>[    50.174] (II) RADEON(0): Modeline "960x720"x120.0  117.00  960 1024 1128 1300  720 720 722 750 doublescan -hsync +vsync (90.0 kHz d)
>[    50.174] (II) RADEON(0): Modeline "928x696"x120.1  109.15  928 976 1088 1264  696 696 698 719 doublescan -hsync +vsync (86.4 kHz d)
>[    50.174] (II) RADEON(0): Modeline "896x672"x120.0  102.40  896 960 1060 1224  672 672 674 697 doublescan -hsync +vsync (83.7 kHz d)
>[    50.174] (II) RADEON(0): Modeline "800x600"x120.0   81.00  800 832 928 1080  600 600 602 625 doublescan +hsync +vsync (75.0 kHz d)
>[    50.174] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz d)
>[    50.174] (II) RADEON(0): Modeline "800x600"x59.9   38.25  800 832 912 1024  600 603 607 624 -hsync +vsync (37.4 kHz)
>[    50.174] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz d)
>[    50.174] (II) RADEON(0): Modeline "848x480"x59.7   31.50  848 872 952 1056  480 483 493 500 -hsync +vsync (29.8 kHz)
>[    50.174] (II) RADEON(0): Modeline "700x525"x120.0   61.00  700 744 820 940  525 526 532 541 doublescan +hsync +vsync (64.9 kHz d)
>[    50.174] (II) RADEON(0): Modeline "720x480"x59.7   26.75  720 744 808 896  480 483 493 500 -hsync +vsync (29.9 kHz)
>[    50.174] (II) RADEON(0): Modeline "640x512"x120.0   54.00  640 664 720 844  512 512 514 533 doublescan +hsync +vsync (64.0 kHz d)
>[    50.174] (II) RADEON(0): Modeline "640x480"x120.0   54.00  640 688 744 900  480 480 482 500 doublescan +hsync +vsync (60.0 kHz d)
>[    50.174] (II) RADEON(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz d)
>[    50.174] (II) RADEON(0): Modeline "640x480"x59.4   23.75  640 664 720 800  480 483 487 500 -hsync +vsync (29.7 kHz)
>[    50.174] (II) RADEON(0): Modeline "512x384"x120.0   32.50  512 524 592 672  384 385 388 403 doublescan -hsync -vsync (48.4 kHz d)
>[    50.174] (II) RADEON(0): Modeline "400x300"x120.6   20.00  400 420 484 528  300 300 302 314 doublescan +hsync +vsync (37.9 kHz d)
>[    50.174] (II) RADEON(0): Modeline "400x300"x112.7   18.00  400 412 448 512  300 300 301 312 doublescan +hsync +vsync (35.2 kHz d)
>[    50.174] (II) RADEON(0): Modeline "320x240"x120.1   12.59  320 328 376 400  240 245 246 262 doublescan -hsync -vsync (31.5 kHz d)
>[    50.174] (II) RADEON(0): Output VGA-0 connected
>[    50.174] (II) RADEON(0): Output LVDS connected
>[    50.174] (II) RADEON(0): Using spanning desktop for initial modes
>[    50.174] (II) RADEON(0): Output VGA-0 using initial mode 1600x900 +0+0
>[    50.174] (II) RADEON(0): Output LVDS using initial mode 1280x800 +1600+0
>[    50.174] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>[    50.174] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:10000000 visible:fa3b000
>[    50.174] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM
>[    50.174] (**) RADEON(0): Display dimensions: (440, 250) mm
>[    50.174] (**) RADEON(0): DPI set to (166, 91)
>[    50.174] (II) Loading sub module "fb"
>[    50.174] (II) LoadModule: "fb"
>[    50.174] (II) Loading /usr/lib64/xorg/modules/libfb.so
>[    50.175] (II) Module fb: vendor="X.Org Foundation"
>[    50.175] 	compiled for 1.12.4, module version = 1.0.0
>[    50.175] 	ABI class: X.Org ANSI C Emulation, version 0.4
>[    50.175] (II) Loading sub module "ramdac"
>[    50.175] (II) LoadModule: "ramdac"
>[    50.175] (II) Module "ramdac" already built-in
>[    50.175] (II) UnloadModule: "vesa"
>[    50.175] (II) Unloading vesa
>[    50.175] (II) UnloadModule: "fbdev"
>[    50.175] (II) Unloading fbdev
>[    50.175] (II) UnloadSubModule: "fbdevhw"
>[    50.175] (II) Unloading fbdevhw
>[    50.175] (--) Depth 24 pixmap format is 32 bpp
>[    50.175] (II) RADEON(0): [DRI2] Setup complete
>[    50.175] (II) RADEON(0): [DRI2]   DRI driver: r600
>[    50.175] (II) RADEON(0): [DRI2]   VDPAU driver: r600
>[    50.175] (II) RADEON(0): Front buffer size: 10172K
>[    50.175] (II) RADEON(0): VRAM usage limit set to 221457K
>[    50.175] (II) RADEON(0): Initializing backing store
>[    50.175] (==) RADEON(0): Backing store disabled
>[    50.175] (II) RADEON(0): Direct rendering enabled
>[    50.175] (II) RADEON(0): Initializing Acceleration
>[    50.175] (II) RADEON(0): Setting EXA maxPitchBytes
>[    50.175] (II) EXA(0): Driver allocated offscreen pixmaps
>[    50.175] (II) EXA(0): Driver registered support for the following operations:
>[    50.175] (II)         Solid
>[    50.175] (II)         Copy
>[    50.175] (II)         Composite (RENDER acceleration)
>[    50.175] (II)         UploadToScreen
>[    50.175] (II)         DownloadFromScreen
>[    50.176] (II) RADEON(0): Acceleration enabled
>[    50.176] (II) RADEON(0): Initializing DPMS
>[    50.176] (==) RADEON(0): DPMS enabled
>[    50.176] (II) RADEON(0): Initializing Cursor
>[    50.176] (==) RADEON(0): Silken mouse enabled
>[    50.176] (II) RADEON(0): Initializing Xv
>[    50.176] (II) RADEON(0): Set up textured video
>[    50.176] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video.
>[    50.176] (II) RADEON(0): [XvMC] Extension initialized.
>[    50.176] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>[    50.176] (II) RADEON(0): Initializing kms color map
>[    50.176] (II) RADEON(0): RADEONScreenInit finished
>[    50.176] (--) RandR disabled
>[    50.176] (II) Initializing built-in extension Generic Event Extension
>[    50.176] (II) Initializing built-in extension SHAPE
>[    50.176] (II) Initializing built-in extension MIT-SHM
>[    50.176] (II) Initializing built-in extension XInputExtension
>[    50.176] (II) Initializing built-in extension XTEST
>[    50.176] (II) Initializing built-in extension BIG-REQUESTS
>[    50.176] (II) Initializing built-in extension SYNC
>[    50.176] (II) Initializing built-in extension XKEYBOARD
>[    50.176] (II) Initializing built-in extension XC-MISC
>[    50.176] (II) Initializing built-in extension XINERAMA
>[    50.176] (II) Initializing built-in extension XFIXES
>[    50.176] (II) Initializing built-in extension RENDER
>[    50.176] (II) Initializing built-in extension RANDR
>[    50.176] (II) Initializing built-in extension COMPOSITE
>[    50.176] (II) Initializing built-in extension DAMAGE
>[    50.176] (II) SELinux: Disabled on system
>[    51.062] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>[    51.062] (II) AIGLX: enabled GLX_INTEL_swap_event
>[    51.062] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>[    51.062] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>[    51.062] (II) AIGLX: Loaded and initialized r600
>[    51.062] (II) GLX: Initialized DRI2 GL provider for screen 0
>[    51.072] (II) RADEON(0): Setting screen physical size to 762 x 238
>[    51.168] (II) XKB: Reusing cached keymap
>[    51.171] (II) config/udev: Adding input device Sony Vaio Keys (/dev/input/event8)
>[    51.171] (**) Sony Vaio Keys: Applying InputClass "evdev keyboard catchall"
>[    51.171] (**) Sony Vaio Keys: Applying InputClass "system-keyboard"
>[    51.171] (II) LoadModule: "evdev"
>[    51.173] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so
>[    51.173] (II) Module evdev: vendor="X.Org Foundation"
>[    51.173] 	compiled for 1.12.0, module version = 2.7.0
>[    51.173] 	Module class: X.Org XInput Driver
>[    51.173] 	ABI class: X.Org XInput driver, version 16.0
>[    51.173] (II) Using input driver 'evdev' for 'Sony Vaio Keys'
>[    51.173] 	Option "XkbRules" "evdev"
>[    51.173] 	Option "XkbModel" "evdev"
>[    51.173] 	Option "XkbLayout" "fr,ara"
>[    51.173] 	Option "_source" "server/udev"
>[    51.173] 	Option "name" "Sony Vaio Keys"
>[    51.173] 	Option "path" "/dev/input/event8"
>[    51.173] 	Option "device" "/dev/input/event8"
>[    51.173] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:00/SNY5001:00/input/input8/event8"
>[    51.173] 	Option "driver" "evdev"
>[    51.173] 	Option "XkbVariant" "azerty_digits"
>[    51.173] (**) Sony Vaio Keys: always reports core events
>[    51.173] (**) evdev: Sony Vaio Keys: Device: "/dev/input/event8"
>[    51.178] (--) evdev: Sony Vaio Keys: Vendor 0x104d Product 0
>[    51.178] (--) evdev: Sony Vaio Keys: Found keys
>[    51.178] (II) evdev: Sony Vaio Keys: Configuring as keyboard
>[    51.178] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:00/SNY5001:00/input/input8/event8"
>[    51.178] (II) XINPUT: Adding extended input device "Sony Vaio Keys" (type: KEYBOARD, id 6)
>[    51.178] (**) Option "xkb_rules" "evdev"
>[    51.178] (**) Option "xkb_model" "evdev"
>[    51.178] (**) Option "xkb_layout" "fr,ara"
>[    51.178] (**) Option "xkb_variant" "azerty_digits"
>[    51.227] (II) config/udev: Adding input device Sony Vaio Jogdial (/dev/input/event9)
>[    51.227] (II) No input driver specified, ignoring this device.
>[    51.227] (II) This device may have been added with another device file.
>[    51.228] (II) config/udev: Adding input device Sony Vaio Jogdial (/dev/input/mouse2)
>[    51.228] (II) No input driver specified, ignoring this device.
>[    51.228] (II) This device may have been added with another device file.
>[    51.228] (II) config/udev: Adding input device Video Bus (/dev/input/event7)
>[    51.228] (**) Video Bus: Applying InputClass "evdev keyboard catchall"
>[    51.228] (**) Video Bus: Applying InputClass "system-keyboard"
>[    51.228] (II) Using input driver 'evdev' for 'Video Bus'
>[    51.228] 	Option "XkbRules" "evdev"
>[    51.228] 	Option "XkbModel" "evdev"
>[    51.228] 	Option "XkbLayout" "fr,ara"
>[    51.228] 	Option "_source" "server/udev"
>[    51.228] 	Option "name" "Video Bus"
>[    51.228] 	Option "path" "/dev/input/event7"
>[    51.228] 	Option "device" "/dev/input/event7"
>[    51.228] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:18/LNXVIDEO:01/input/input7/event7"
>[    51.228] 	Option "driver" "evdev"
>[    51.228] 	Option "XkbVariant" "azerty_digits"
>[    51.228] (**) Video Bus: always reports core events
>[    51.228] (**) evdev: Video Bus: Device: "/dev/input/event7"
>[    51.228] (--) evdev: Video Bus: Vendor 0 Product 0x6
>[    51.228] (--) evdev: Video Bus: Found keys
>[    51.228] (II) evdev: Video Bus: Configuring as keyboard
>[    51.228] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:18/LNXVIDEO:01/input/input7/event7"
>[    51.228] (II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD, id 7)
>[    51.228] (**) Option "xkb_rules" "evdev"
>[    51.228] (**) Option "xkb_model" "evdev"
>[    51.228] (**) Option "xkb_layout" "fr,ara"
>[    51.228] (**) Option "xkb_variant" "azerty_digits"
>[    51.228] (II) XKB: Reusing cached keymap
>[    51.229] (II) config/udev: Adding input device Power Button (/dev/input/event1)
>[    51.229] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    51.229] (**) Power Button: Applying InputClass "system-keyboard"
>[    51.229] (II) Using input driver 'evdev' for 'Power Button'
>[    51.229] 	Option "XkbRules" "evdev"
>[    51.229] 	Option "XkbModel" "evdev"
>[    51.229] 	Option "XkbLayout" "fr,ara"
>[    51.229] 	Option "_source" "server/udev"
>[    51.229] 	Option "name" "Power Button"
>[    51.229] 	Option "path" "/dev/input/event1"
>[    51.229] 	Option "device" "/dev/input/event1"
>[    51.229] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1/event1"
>[    51.229] 	Option "driver" "evdev"
>[    51.229] 	Option "XkbVariant" "azerty_digits"
>[    51.229] (**) Power Button: always reports core events
>[    51.229] (**) evdev: Power Button: Device: "/dev/input/event1"
>[    51.229] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    51.229] (--) evdev: Power Button: Found keys
>[    51.229] (II) evdev: Power Button: Configuring as keyboard
>[    51.229] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1/event1"
>[    51.229] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 8)
>[    51.229] (**) Option "xkb_rules" "evdev"
>[    51.229] (**) Option "xkb_model" "evdev"
>[    51.229] (**) Option "xkb_layout" "fr,ara"
>[    51.229] (**) Option "xkb_variant" "azerty_digits"
>[    51.229] (II) XKB: Reusing cached keymap
>[    51.230] (II) config/udev: Adding input device Lid Switch (/dev/input/event0)
>[    51.230] (II) No input driver specified, ignoring this device.
>[    51.230] (II) This device may have been added with another device file.
>[    51.230] (II) config/udev: Adding input device UVC Camera (05ca:18b3) (/dev/input/event12)
>[    51.230] (**) UVC Camera (05ca:18b3): Applying InputClass "evdev keyboard catchall"
>[    51.230] (**) UVC Camera (05ca:18b3): Applying InputClass "system-keyboard"
>[    51.230] (II) Using input driver 'evdev' for 'UVC Camera (05ca:18b3)'
>[    51.230] 	Option "XkbRules" "evdev"
>[    51.230] 	Option "XkbModel" "evdev"
>[    51.230] 	Option "XkbLayout" "fr,ara"
>[    51.230] 	Option "_source" "server/udev"
>[    51.230] 	Option "name" "UVC Camera (05ca:18b3)"
>[    51.230] 	Option "path" "/dev/input/event12"
>[    51.230] 	Option "device" "/dev/input/event12"
>[    51.230] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.7/usb1/1-2/1-2:1.0/input/input12/event12"
>[    51.230] 	Option "driver" "evdev"
>[    51.230] 	Option "XkbVariant" "azerty_digits"
>[    51.230] (**) UVC Camera (05ca:18b3): always reports core events
>[    51.230] (**) evdev: UVC Camera (05ca:18b3): Device: "/dev/input/event12"
>[    51.230] (--) evdev: UVC Camera (05ca:18b3): Vendor 0x5ca Product 0x18b3
>[    51.230] (--) evdev: UVC Camera (05ca:18b3): Found keys
>[    51.231] (II) evdev: UVC Camera (05ca:18b3): Configuring as keyboard
>[    51.231] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.7/usb1/1-2/1-2:1.0/input/input12/event12"
>[    51.231] (II) XINPUT: Adding extended input device "UVC Camera (05ca:18b3)" (type: KEYBOARD, id 9)
>[    51.231] (**) Option "xkb_rules" "evdev"
>[    51.231] (**) Option "xkb_model" "evdev"
>[    51.231] (**) Option "xkb_layout" "fr,ara"
>[    51.231] (**) Option "xkb_variant" "azerty_digits"
>[    51.231] (II) XKB: Reusing cached keymap
>[    51.231] (II) config/udev: Adding input device HDA Intel Mic (/dev/input/event10)
>[    51.231] (II) No input driver specified, ignoring this device.
>[    51.231] (II) This device may have been added with another device file.
>[    51.232] (II) config/udev: Adding input device HDA Intel Headphone (/dev/input/event11)
>[    51.232] (II) No input driver specified, ignoring this device.
>[    51.232] (II) This device may have been added with another device file.
>[    51.232] (II) config/udev: Adding input device  USB OPTICAL MOUSE (/dev/input/event4)
>[    51.232] (**)  USB OPTICAL MOUSE: Applying InputClass "evdev pointer catchall"
>[    51.232] (II) Using input driver 'evdev' for ' USB OPTICAL MOUSE'
>[    51.232] 	Option "XkbRules" "evdev"
>[    51.232] 	Option "XkbModel" "evdev"
>[    51.232] 	Option "XkbLayout" "us"
>[    51.232] 	Option "_source" "server/udev"
>[    51.232] 	Option "name" " USB OPTICAL MOUSE"
>[    51.232] 	Option "path" "/dev/input/event4"
>[    51.232] 	Option "device" "/dev/input/event4"
>[    51.232] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb6/6-1/6-1:1.0/input/input4/event4"
>[    51.232] 	Option "driver" "evdev"
>[    51.232] (**)  USB OPTICAL MOUSE: always reports core events
>[    51.232] (**) evdev:  USB OPTICAL MOUSE: Device: "/dev/input/event4"
>[    51.232] (--) evdev:  USB OPTICAL MOUSE: Vendor 0x15d9 Product 0xa4d
>[    51.232] (--) evdev:  USB OPTICAL MOUSE: Found 3 mouse buttons
>[    51.232] (--) evdev:  USB OPTICAL MOUSE: Found scroll wheel(s)
>[    51.232] (--) evdev:  USB OPTICAL MOUSE: Found relative axes
>[    51.232] (--) evdev:  USB OPTICAL MOUSE: Found x and y relative axes
>[    51.232] (II) evdev:  USB OPTICAL MOUSE: Configuring as mouse
>[    51.232] (II) evdev:  USB OPTICAL MOUSE: Adding scrollwheel support
>[    51.232] (**) evdev:  USB OPTICAL MOUSE: YAxisMapping: buttons 4 and 5
>[    51.232] (**) evdev:  USB OPTICAL MOUSE: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    51.232] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb6/6-1/6-1:1.0/input/input4/event4"
>[    51.232] (II) XINPUT: Adding extended input device " USB OPTICAL MOUSE" (type: MOUSE, id 10)
>[    51.232] (II) evdev:  USB OPTICAL MOUSE: initialized for relative axes.
>[    51.233] (**)  USB OPTICAL MOUSE: (accel) keeping acceleration scheme 1
>[    51.233] (**)  USB OPTICAL MOUSE: (accel) acceleration profile 0
>[    51.238] (**)  USB OPTICAL MOUSE: (accel) acceleration factor: 2.000
>[    51.238] (**)  USB OPTICAL MOUSE: (accel) acceleration threshold: 4
>[    51.238] (II) config/udev: Adding input device  USB OPTICAL MOUSE (/dev/input/mouse1)
>[    51.238] (II) No input driver specified, ignoring this device.
>[    51.238] (II) This device may have been added with another device file.
>[    51.239] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event5)
>[    51.239] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[    51.239] (**) USB USB Keykoard: Applying InputClass "system-keyboard"
>[    51.239] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[    51.239] 	Option "XkbRules" "evdev"
>[    51.239] 	Option "XkbModel" "evdev"
>[    51.239] 	Option "XkbLayout" "fr,ara"
>[    51.239] 	Option "_source" "server/udev"
>[    51.239] 	Option "name" "USB USB Keykoard"
>[    51.239] 	Option "path" "/dev/input/event5"
>[    51.239] 	Option "device" "/dev/input/event5"
>[    51.239] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb6/6-2/6-2:1.0/input/input5/event5"
>[    51.239] 	Option "driver" "evdev"
>[    51.239] 	Option "XkbVariant" "azerty_digits"
>[    51.239] (**) USB USB Keykoard: always reports core events
>[    51.239] (**) evdev: USB USB Keykoard: Device: "/dev/input/event5"
>[    51.239] (--) evdev: USB USB Keykoard: Vendor 0x1a2c Product 0x2
>[    51.239] (--) evdev: USB USB Keykoard: Found keys
>[    51.239] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[    51.239] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb6/6-2/6-2:1.0/input/input5/event5"
>[    51.239] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 11)
>[    51.239] (**) Option "xkb_rules" "evdev"
>[    51.239] (**) Option "xkb_model" "evdev"
>[    51.239] (**) Option "xkb_layout" "fr,ara"
>[    51.239] (**) Option "xkb_variant" "azerty_digits"
>[    51.239] (II) XKB: Reusing cached keymap
>[    51.242] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event6)
>[    51.242] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[    51.242] (**) USB USB Keykoard: Applying InputClass "system-keyboard"
>[    51.242] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[    51.242] 	Option "XkbRules" "evdev"
>[    51.242] 	Option "XkbModel" "evdev"
>[    51.242] 	Option "XkbLayout" "fr,ara"
>[    51.242] 	Option "_source" "server/udev"
>[    51.242] 	Option "name" "USB USB Keykoard"
>[    51.242] 	Option "path" "/dev/input/event6"
>[    51.242] 	Option "device" "/dev/input/event6"
>[    51.242] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb6/6-2/6-2:1.1/input/input6/event6"
>[    51.242] 	Option "driver" "evdev"
>[    51.242] 	Option "XkbVariant" "azerty_digits"
>[    51.242] (**) USB USB Keykoard: always reports core events
>[    51.242] (**) evdev: USB USB Keykoard: Device: "/dev/input/event6"
>[    51.242] (--) evdev: USB USB Keykoard: absolute axis 0x20 [572..0]
>[    51.242] (--) evdev: USB USB Keykoard: Vendor 0x1a2c Product 0x2
>[    51.242] (--) evdev: USB USB Keykoard: Found 1 mouse buttons
>[    51.242] (--) evdev: USB USB Keykoard: Found scroll wheel(s)
>[    51.242] (--) evdev: USB USB Keykoard: Found relative axes
>[    51.242] (II) evdev: USB USB Keykoard: Forcing relative x/y axes to exist.
>[    51.242] (--) evdev: USB USB Keykoard: Found absolute axes
>[    51.242] (II) evdev: USB USB Keykoard: Forcing absolute x/y axes to exist.
>[    51.242] (--) evdev: USB USB Keykoard: Found keys
>[    51.242] (II) evdev: USB USB Keykoard: Configuring as mouse
>[    51.242] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[    51.242] (II) evdev: USB USB Keykoard: Adding scrollwheel support
>[    51.242] (**) evdev: USB USB Keykoard: YAxisMapping: buttons 4 and 5
>[    51.242] (**) evdev: USB USB Keykoard: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    51.242] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb6/6-2/6-2:1.1/input/input6/event6"
>[    51.242] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 12)
>[    51.242] (**) Option "xkb_rules" "evdev"
>[    51.242] (**) Option "xkb_model" "evdev"
>[    51.245] (**) Option "xkb_layout" "fr,ara"
>[    51.245] (**) Option "xkb_variant" "azerty_digits"
>[    51.245] (II) XKB: Reusing cached keymap
>[    51.245] (II) evdev: USB USB Keykoard: initialized for relative axes.
>[    51.245] (WW) evdev: USB USB Keykoard: ignoring absolute axes.
>[    51.246] (**) USB USB Keykoard: (accel) keeping acceleration scheme 1
>[    51.246] (**) USB USB Keykoard: (accel) acceleration profile 0
>[    51.246] (**) USB USB Keykoard: (accel) acceleration factor: 2.000
>[    51.246] (**) USB USB Keykoard: (accel) acceleration threshold: 4
>[    51.246] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event2)
>[    51.246] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall"
>[    51.246] (**) AT Translated Set 2 keyboard: Applying InputClass "system-keyboard"
>[    51.246] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard'
>[    51.246] 	Option "XkbRules" "evdev"
>[    51.246] 	Option "XkbModel" "evdev"
>[    51.246] 	Option "XkbLayout" "fr,ara"
>[    51.246] 	Option "_source" "server/udev"
>[    51.246] 	Option "name" "AT Translated Set 2 keyboard"
>[    51.246] 	Option "path" "/dev/input/event2"
>[    51.246] 	Option "device" "/dev/input/event2"
>[    51.246] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input2/event2"
>[    51.246] 	Option "driver" "evdev"
>[    51.246] 	Option "XkbVariant" "azerty_digits"
>[    51.246] (**) AT Translated Set 2 keyboard: always reports core events
>[    51.246] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event2"
>[    51.246] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1
>[    51.246] (--) evdev: AT Translated Set 2 keyboard: Found keys
>[    51.246] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard
>[    51.246] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input2/event2"
>[    51.247] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 13)
>[    51.247] (**) Option "xkb_rules" "evdev"
>[    51.247] (**) Option "xkb_model" "evdev"
>[    51.247] (**) Option "xkb_layout" "fr,ara"
>[    51.247] (**) Option "xkb_variant" "azerty_digits"
>[    51.247] (II) XKB: Reusing cached keymap
>[    51.250] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/event3)
>[    51.250] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "evdev touchpad catchall"
>[    51.250] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "touchpad catchall"
>[    51.250] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "Default clickpad buttons"
>[    51.250] (II) LoadModule: "synaptics"
>[    51.252] (II) Loading /usr/lib64/xorg/modules/input/synaptics_drv.so
>[    51.252] (II) Module synaptics: vendor="X.Org Foundation"
>[    51.252] 	compiled for 1.12.3, module version = 1.6.2
>[    51.252] 	Module class: X.Org XInput Driver
>[    51.252] 	ABI class: X.Org XInput driver, version 16.0
>[    51.252] (II) Using input driver 'synaptics' for 'SynPS/2 Synaptics TouchPad'
>[    51.252] 	Option "_source" "server/udev"
>[    51.252] 	Option "name" "SynPS/2 Synaptics TouchPad"
>[    51.252] 	Option "path" "/dev/input/event3"
>[    51.252] 	Option "device" "/dev/input/event3"
>[    51.252] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input3/event3"
>[    51.252] 	Option "driver" "synaptics"
>[    51.252] 	Option "SoftButtonAreas" "50% 0 82% 0 0 0 0 0"
>[    51.252] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    51.252] (**) Option "Device" "/dev/input/event3"
>[    51.276] (**) Option "Device" "/dev/input/event3"
>[    51.276] port opened successfully
>[    51.276] (--) synaptics: SynPS/2 Synaptics TouchPad: x-axis range 1472 - 5696
>[    51.276] (--) synaptics: SynPS/2 Synaptics TouchPad: y-axis range 1408 - 5232
>[    51.276] (--) synaptics: SynPS/2 Synaptics TouchPad: pressure range 0 - 255
>[    51.276] (--) synaptics: SynPS/2 Synaptics TouchPad: finger width range 0 - 15
>[    51.276] (--) synaptics: SynPS/2 Synaptics TouchPad: buttons: left right
>[    51.276] (--) synaptics: SynPS/2 Synaptics TouchPad: Vendor 0x2 Product 0x7
>[    51.276] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    51.276] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    51.289] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input3/event3"
>[    51.289] (II) XINPUT: Adding extended input device "SynPS/2 Synaptics TouchPad" (type: TOUCHPAD, id 14)
>[    51.289] (**) synaptics: SynPS/2 Synaptics TouchPad: (accel) MinSpeed is now constant deceleration 2.5
>[    51.289] (**) synaptics: SynPS/2 Synaptics TouchPad: MaxSpeed is now 1.75
>[    51.289] (**) synaptics: SynPS/2 Synaptics TouchPad: AccelFactor is now 0.035
>[    51.289] (**) SynPS/2 Synaptics TouchPad: (accel) keeping acceleration scheme 1
>[    51.289] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration profile 1
>[    51.289] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration factor: 2.000
>[    51.289] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration threshold: 4
>[    51.289] (**) Option "Device" "/dev/input/event3"
>[    51.289] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    51.289] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/mouse0)
>[    51.289] (II) No input driver specified, ignoring this device.
>[    51.289] (II) This device may have been added with another device file.
>[    51.294] (II) RADEON(0): RADEONSaveScreen(2)
>[    55.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc1320]
>[    55.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc1320] width 2880 pitch 11520 (/4 2880)
>[    55.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc12c0]
>[    55.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc12c0] width 2880 pitch 11520 (/4 2880)
>[    55.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc1320]
>[    55.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc1320] width 2880 pitch 11520 (/4 2880)
>[    55.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc12c0]
>[    55.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc12c0] width 2880 pitch 11520 (/4 2880)
>[    55.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc1320]
>[    55.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc1320] width 2880 pitch 11520 (/4 2880)
>[    55.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc12c0]
>[    55.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc12c0] width 2880 pitch 11520 (/4 2880)
>[    55.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc1320]
>[    55.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc1320] width 2880 pitch 11520 (/4 2880)
>[    55.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc14b0]
>[    55.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc14b0] width 2880 pitch 11520 (/4 2880)
>[    56.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    56.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc32f0]
>[    56.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc32f0] width 2880 pitch 11520 (/4 2880)
>[    56.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc3290]
>[    56.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc3290] width 2880 pitch 11520 (/4 2880)
>[    57.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    57.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    57.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abf440]
>[    57.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abf440] width 2880 pitch 11520 (/4 2880)
>[    57.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    57.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    57.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abf440]
>[    57.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abf440] width 2880 pitch 11520 (/4 2880)
>[    57.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    57.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    57.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abf440]
>[    57.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abf440] width 2880 pitch 11520 (/4 2880)
>[    57.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    57.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    57.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abf440]
>[    57.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abf440] width 2880 pitch 11520 (/4 2880)
>[    57.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    57.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    57.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abf440]
>[    57.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abf440] width 2880 pitch 11520 (/4 2880)
>[    57.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    57.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    57.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abf440]
>[    57.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abf440] width 2880 pitch 11520 (/4 2880)
>[    57.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    57.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    57.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abf440]
>[    57.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abf440] width 2880 pitch 11520 (/4 2880)
>[    57.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    57.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    57.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1abf440]
>[    57.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1abf440] width 2880 pitch 11520 (/4 2880)
>[    57.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e970]
>[    58.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e970] width 2880 pitch 11520 (/4 2880)
>[    58.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    58.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    58.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    58.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    58.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    59.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    59.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    59.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    59.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    60.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    60.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    60.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    60.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    60.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    60.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    60.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    60.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    61.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    61.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    62.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    62.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    62.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x184e890]
>[    62.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x184e890] width 2880 pitch 11520 (/4 2880)
>[    62.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc15e0]
>[    62.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc15e0] width 2880 pitch 11520 (/4 2880)
>[    64.989] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[    65.014] (II) RADEON(0): VRAM usage limit set to 225527K
>[    67.293] (II) RADEON(0): EDID vendor "FUS", prod id 2015
>[    67.293] (II) RADEON(0): Using hsync ranges from config file
>[    67.293] (II) RADEON(0): Using vrefresh ranges from config file
>[    67.293] (II) RADEON(0): Printing DDC gathered Modelines:
>[    67.293] (II) RADEON(0): Modeline "1600x900"x0.0   97.75  1600 1648 1680 1760  900 903 908 926 +hsync -vsync (55.5 kHz eP)
>[    67.293] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    67.293] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    67.293] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    67.293] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    67.293] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    67.293] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    67.293] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    67.293] (II) RADEON(0): Modeline "1280x720"x60.0   74.48  1280 1336 1472 1664  720 721 724 746 -hsync +vsync (44.8 kHz e)
>[    96.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[    96.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[    96.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f7740]
>[    96.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f7740] width 1600 pitch 6400 (/4 1600)
>[    96.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[    96.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[    97.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8b00]
>[    97.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8b00] width 1600 pitch 6400 (/4 1600)
>[    97.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcaf30]
>[    97.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcaf30] width 1600 pitch 6400 (/4 1600)
>[    97.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fcaa0]
>[    97.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fcaa0] width 1600 pitch 6400 (/4 1600)
>[    97.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcaf30]
>[    97.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcaf30] width 1600 pitch 6400 (/4 1600)
>[    97.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb360]
>[    97.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb360] width 1600 pitch 6400 (/4 1600)
>[    97.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc490]
>[    97.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc490] width 1600 pitch 6400 (/4 1600)
>[    97.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[    97.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[    97.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc490]
>[    97.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc490] width 1600 pitch 6400 (/4 1600)
>[    97.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[    97.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[    97.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc490]
>[    97.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc490] width 1600 pitch 6400 (/4 1600)
>[    97.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[    98.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[    98.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[    98.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[    98.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[    98.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[    98.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[    98.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[    98.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[    98.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[    98.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[    98.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[    98.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[    98.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[    99.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fceb0]
>[    99.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fceb0] width 1600 pitch 6400 (/4 1600)
>[   101.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   101.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   101.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   101.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   101.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   101.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   101.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   101.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   101.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   101.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   101.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   101.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   101.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   101.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   101.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   101.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   102.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   102.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   102.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   102.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   102.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   102.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   102.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   102.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   104.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   104.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   104.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   104.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   105.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   105.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   105.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   105.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   105.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   105.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   105.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22661b0]
>[   105.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22661b0] width 1600 pitch 6400 (/4 1600)
>[   105.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2266af0]
>[   105.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2266af0] width 1600 pitch 6400 (/4 1600)
>[   106.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250580]
>[   106.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250580] width 1600 pitch 6400 (/4 1600)
>[   106.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2290330]
>[   106.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2290330] width 1600 pitch 6400 (/4 1600)
>[   106.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2255640]
>[   106.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2255640] width 1600 pitch 6400 (/4 1600)
>[   106.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2290330]
>[   106.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2290330] width 1600 pitch 6400 (/4 1600)
>[   106.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2255640]
>[   106.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2255640] width 1600 pitch 6400 (/4 1600)
>[   106.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2290330]
>[   106.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2290330] width 1600 pitch 6400 (/4 1600)
>[   106.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2255640]
>[   106.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2255640] width 1600 pitch 6400 (/4 1600)
>[   106.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2290330]
>[   106.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2290330] width 1600 pitch 6400 (/4 1600)
>[   115.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   115.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   115.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   115.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   116.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   116.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   116.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   116.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   116.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc7d20]
>[   116.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc7d20] width 1600 pitch 6400 (/4 1600)
>[   116.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   116.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   116.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   116.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   116.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc7d20]
>[   116.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc7d20] width 1600 pitch 6400 (/4 1600)
>[   116.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230bd60]
>[   116.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230bd60] width 1600 pitch 6400 (/4 1600)
>[   116.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6fd0]
>[   116.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6fd0] width 1600 pitch 6400 (/4 1600)
>[   117.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230bd60]
>[   117.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230bd60] width 1600 pitch 6400 (/4 1600)
>[   117.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6fd0]
>[   117.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6fd0] width 1600 pitch 6400 (/4 1600)
>[   117.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230bd60]
>[   117.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230bd60] width 1600 pitch 6400 (/4 1600)
>[   117.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6fd0]
>[   117.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6fd0] width 1600 pitch 6400 (/4 1600)
>[   117.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230bd60]
>[   117.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230bd60] width 1600 pitch 6400 (/4 1600)
>[   117.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6fd0]
>[   117.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6fd0] width 1600 pitch 6400 (/4 1600)
>[   117.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230bd60]
>[   117.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230bd60] width 1600 pitch 6400 (/4 1600)
>[   117.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x19e6840]
>[   117.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x19e6840] width 1600 pitch 6400 (/4 1600)
>[   117.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230bc30]
>[   117.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230bc30] width 1600 pitch 6400 (/4 1600)
>[   117.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22575a0]
>[   117.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22575a0] width 1600 pitch 6400 (/4 1600)
>[   117.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230bd60]
>[   117.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230bd60] width 1600 pitch 6400 (/4 1600)
>[   119.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[   119.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[   119.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   119.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   119.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[   119.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[   119.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   119.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   119.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[   119.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[   119.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   119.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   119.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[   119.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[   119.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   119.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   119.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[   119.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[   119.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   119.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   119.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[   119.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[   119.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   119.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   119.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[   119.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[   119.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   119.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   119.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[   119.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[   121.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   121.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   121.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   121.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   121.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   121.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   121.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   121.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   121.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   121.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   121.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   121.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   121.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   121.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   122.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   122.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   122.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   122.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   122.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   122.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   122.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   122.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   122.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   122.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   122.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   122.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   122.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   122.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   122.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   122.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   122.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   122.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   122.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   122.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   122.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f6280]
>[   122.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f6280] width 1600 pitch 6400 (/4 1600)
>[   122.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bcb3f0]
>[   122.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bcb3f0] width 1600 pitch 6400 (/4 1600)
>[   122.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   122.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   122.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   122.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   122.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   122.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   122.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   122.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   122.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   122.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   122.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   122.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   122.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   122.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   122.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   122.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   122.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   122.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   122.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   122.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   122.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   122.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   122.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   122.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   122.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   122.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   123.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   123.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   123.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   123.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   123.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   123.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   123.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   123.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   124.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   124.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   124.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   124.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   124.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   124.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   124.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   124.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   124.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   124.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   124.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   124.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   124.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   124.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   124.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   124.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   124.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   124.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   124.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   124.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   124.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   124.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   124.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   124.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   124.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   124.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   124.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   124.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   124.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   124.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   125.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   125.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   125.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   125.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   125.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   125.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   125.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b730]
>[   125.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b730] width 1600 pitch 6400 (/4 1600)
>[   125.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   125.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   125.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b730]
>[   125.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b730] width 1600 pitch 6400 (/4 1600)
>[   125.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   125.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   125.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b730]
>[   125.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b730] width 1600 pitch 6400 (/4 1600)
>[   125.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258790]
>[   125.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258790] width 1600 pitch 6400 (/4 1600)
>[   125.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224b730]
>[   125.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224b730] width 1600 pitch 6400 (/4 1600)
>[   125.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1befa40]
>[   125.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1befa40] width 1600 pitch 6400 (/4 1600)
>[   129.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b98f0]
>[   132.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b98f0] width 1600 pitch 6400 (/4 1600)
>[   132.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b94f0]
>[   132.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b94f0] width 1600 pitch 6400 (/4 1600)
>[   132.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x225a0d0]
>[   132.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x225a0d0] width 1600 pitch 6400 (/4 1600)
>[   132.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aace0]
>[   132.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aace0] width 1600 pitch 6400 (/4 1600)
>[   132.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aace0]
>[   132.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aace0] width 1600 pitch 6400 (/4 1600)
>[   134.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226e850]
>[   135.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226e850] width 1600 pitch 6400 (/4 1600)
>[   135.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2274c70]
>[   135.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2274c70] width 1600 pitch 6400 (/4 1600)
>[   135.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226f3e0]
>[   135.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226f3e0] width 1600 pitch 6400 (/4 1600)
>[   135.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2270b90]
>[   135.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2270b90] width 1600 pitch 6400 (/4 1600)
>[   135.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2274c70]
>[   135.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2274c70] width 1600 pitch 6400 (/4 1600)
>[   135.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226e850]
>[   135.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226e850] width 1600 pitch 6400 (/4 1600)
>[   135.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226f3e0]
>[   135.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226f3e0] width 1600 pitch 6400 (/4 1600)
>[   135.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2270b90]
>[   135.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2270b90] width 1600 pitch 6400 (/4 1600)
>[   145.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a2e0]
>[   145.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a2e0] width 1600 pitch 6400 (/4 1600)
>[   145.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2289790]
>[   145.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2289790] width 1600 pitch 6400 (/4 1600)
>[   145.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a130]
>[   145.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a130] width 1600 pitch 6400 (/4 1600)
>[   145.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b5070]
>[   145.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b5070] width 1600 pitch 6400 (/4 1600)
>[   145.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a130]
>[   145.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a130] width 1600 pitch 6400 (/4 1600)
>[   145.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b4fe0]
>[   145.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b4fe0] width 1600 pitch 6400 (/4 1600)
>[   145.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d0690]
>[   145.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d0690] width 1600 pitch 6400 (/4 1600)
>[   145.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b5070]
>[   145.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b5070] width 1600 pitch 6400 (/4 1600)
>[   145.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22895d0]
>[   145.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22895d0] width 1600 pitch 6400 (/4 1600)
>[   146.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284450]
>[   146.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284450] width 1600 pitch 6400 (/4 1600)
>[   146.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22846a0]
>[   146.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22846a0] width 1600 pitch 6400 (/4 1600)
>[   146.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284450]
>[   146.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284450] width 1600 pitch 6400 (/4 1600)
>[   146.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22846a0]
>[   146.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22846a0] width 1600 pitch 6400 (/4 1600)
>[   146.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284450]
>[   146.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284450] width 1600 pitch 6400 (/4 1600)
>[   146.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d50f0]
>[   146.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d50f0] width 1600 pitch 6400 (/4 1600)
>[   146.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d50f0]
>[   146.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d50f0] width 1600 pitch 6400 (/4 1600)
>[   146.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d50f0]
>[   146.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d50f0] width 1600 pitch 6400 (/4 1600)
>[   146.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284450]
>[   146.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284450] width 1600 pitch 6400 (/4 1600)
>[   146.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d50f0]
>[   146.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d50f0] width 1600 pitch 6400 (/4 1600)
>[   146.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284450]
>[   146.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284450] width 1600 pitch 6400 (/4 1600)
>[   156.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222bc80]
>[   156.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222bc80] width 1600 pitch 6400 (/4 1600)
>[   156.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a0f0]
>[   156.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a0f0] width 1600 pitch 6400 (/4 1600)
>[   156.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284a40]
>[   156.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284a40] width 1600 pitch 6400 (/4 1600)
>[   156.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a0f0]
>[   156.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a0f0] width 1600 pitch 6400 (/4 1600)
>[   156.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284a40]
>[   156.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284a40] width 1600 pitch 6400 (/4 1600)
>[   156.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a0f0]
>[   156.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a0f0] width 1600 pitch 6400 (/4 1600)
>[   156.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284a40]
>[   156.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284a40] width 1600 pitch 6400 (/4 1600)
>[   156.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a0f0]
>[   156.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a0f0] width 1600 pitch 6400 (/4 1600)
>[   156.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284a40]
>[   156.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284a40] width 1600 pitch 6400 (/4 1600)
>[   156.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a0f0]
>[   156.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a0f0] width 1600 pitch 6400 (/4 1600)
>[   156.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284a40]
>[   156.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284a40] width 1600 pitch 6400 (/4 1600)
>[   156.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x222a0f0]
>[   156.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x222a0f0] width 1600 pitch 6400 (/4 1600)
>[   156.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2284a40]
>[   156.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2284a40] width 1600 pitch 6400 (/4 1600)
>[   201.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22cd5f0]
>[   201.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22cd5f0] width 1600 pitch 6400 (/4 1600)
>[   201.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22cf710]
>[   201.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22cf710] width 1600 pitch 6400 (/4 1600)
>[   443.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226a170]
>[   443.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226a170] width 1600 pitch 6400 (/4 1600)
>[   443.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd4630]
>[   443.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd4630] width 1600 pitch 6400 (/4 1600)
>[   443.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226a170]
>[   443.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226a170] width 1600 pitch 6400 (/4 1600)
>[   443.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd4630]
>[   443.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd4630] width 1600 pitch 6400 (/4 1600)
>[   485.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2239220]
>[   485.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2239220] width 1600 pitch 6400 (/4 1600)
>[   485.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1140]
>[   485.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1140] width 1600 pitch 6400 (/4 1600)
>[   489.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   489.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   489.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   489.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   489.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   489.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   489.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   489.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   489.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   489.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   489.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   489.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   489.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   489.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   489.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   489.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   489.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   489.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   489.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   489.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   490.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   490.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   490.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   490.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   491.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   491.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   491.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   491.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   491.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   491.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   491.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   491.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   491.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   491.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   491.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   491.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   491.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   491.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   491.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22be940]
>[   491.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22be940] width 1600 pitch 6400 (/4 1600)
>[   491.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   491.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   508.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bf090]
>[   508.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bf090] width 1600 pitch 6400 (/4 1600)
>[   508.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22bed80]
>[   508.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22bed80] width 1600 pitch 6400 (/4 1600)
>[   527.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220d300]
>[   527.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220d300] width 1600 pitch 6400 (/4 1600)
>[   527.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x220ba90]
>[   527.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x220ba90] width 1600 pitch 6400 (/4 1600)
>[   553.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22fcf40]
>[   554.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22fcf40] width 1600 pitch 6400 (/4 1600)
>[   554.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2204f70]
>[   554.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2204f70] width 1600 pitch 6400 (/4 1600)
>[  1762.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22dee60]
>[  1762.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22dee60] width 1600 pitch 6400 (/4 1600)
>[  1762.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22df810]
>[  1762.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22df810] width 1600 pitch 6400 (/4 1600)
>[  1836.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230e440]
>[  1836.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230e440] width 1600 pitch 6400 (/4 1600)
>[  1836.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230e440]
>[  1836.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230e440] width 1600 pitch 6400 (/4 1600)
>[  3960.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x231b500]
>[  3960.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x231b500] width 1600 pitch 6400 (/4 1600)
>[  3960.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x231a9e0]
>[  3960.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x231a9e0] width 1600 pitch 6400 (/4 1600)
>[  6107.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x231e9b0]
>[  6107.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x231e9b0] width 1600 pitch 6400 (/4 1600)
>[  6107.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2338b10]
>[  6107.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2338b10] width 1600 pitch 6400 (/4 1600)
>[  6154.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2323e40]
>[  6154.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2323e40] width 1600 pitch 6400 (/4 1600)
>[  6154.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2323e40]
>[  6154.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2323e40] width 1600 pitch 6400 (/4 1600)
>[  6363.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6363.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6363.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2351cc0]
>[  6363.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2351cc0] width 1600 pitch 6400 (/4 1600)
>[  6377.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2352110]
>[  6377.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2352110] width 1600 pitch 6400 (/4 1600)
>[  6377.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6377.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6378.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x231a650]
>[  6378.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x231a650] width 1600 pitch 6400 (/4 1600)
>[  6379.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2206530]
>[  6379.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2206530] width 1600 pitch 6400 (/4 1600)
>[  6383.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6383.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6384.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6384.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6384.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6384.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6384.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6384.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6384.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6384.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6384.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6384.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6384.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6384.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6384.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6384.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6384.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6384.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6385.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6385.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6386.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6386.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6386.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6386.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6386.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6386.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6386.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6386.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6386.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6386.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6386.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6386.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6386.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6386.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  6386.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23699f0]
>[  6386.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23699f0] width 1600 pitch 6400 (/4 1600)
>[  6386.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236c690]
>[  6386.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236c690] width 1600 pitch 6400 (/4 1600)
>[  8145.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23875a0]
>[  8145.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23875a0] width 1600 pitch 6400 (/4 1600)
>[  8145.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x236fdd0]
>[  8145.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x236fdd0] width 1600 pitch 6400 (/4 1600)
>[  8297.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2370640]
>[  8297.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2370640] width 1600 pitch 6400 (/4 1600)
>[  8297.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2370a60]
>[  8297.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2370a60] width 1600 pitch 6400 (/4 1600)
>[  8310.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x237db60]
>[  8310.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x237db60] width 1600 pitch 6400 (/4 1600)
>[  8310.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x237eb60]
>[  8310.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x237eb60] width 1600 pitch 6400 (/4 1600)
>[  8891.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2370640]
>[  8891.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2370640] width 1600 pitch 6400 (/4 1600)
>[  8891.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2388170]
>[  8891.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2388170] width 1600 pitch 6400 (/4 1600)
>[  9288.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23aa300]
>[  9288.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23aa300] width 1600 pitch 6400 (/4 1600)
>[  9288.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23aa300]
>[  9288.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23aa300] width 1600 pitch 6400 (/4 1600)
>[ 10333.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2152980]
>[ 10334.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2152980] width 1600 pitch 6400 (/4 1600)
>[ 10350.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214bcf0]
>[ 10350.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214bcf0] width 1600 pitch 6400 (/4 1600)
>[ 10350.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x215f160]
>[ 10350.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x215f160] width 1600 pitch 6400 (/4 1600)
>[ 10351.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214bcf0]
>[ 10351.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214bcf0] width 1600 pitch 6400 (/4 1600)
>[ 10351.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x215f160]
>[ 10351.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x215f160] width 1600 pitch 6400 (/4 1600)
>[ 10417.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2158f50]
>[ 10417.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2158f50] width 1600 pitch 6400 (/4 1600)
>[ 10417.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214b950]
>[ 10417.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214b950] width 1600 pitch 6400 (/4 1600)
>[ 10417.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21585f0]
>[ 10417.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21585f0] width 1600 pitch 6400 (/4 1600)
>[ 10417.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214b950]
>[ 10417.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214b950] width 1600 pitch 6400 (/4 1600)
>[ 10417.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21585f0]
>[ 10417.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21585f0] width 1600 pitch 6400 (/4 1600)
>[ 10417.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214b950]
>[ 10417.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214b950] width 1600 pitch 6400 (/4 1600)
>[ 10417.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21585f0]
>[ 10417.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21585f0] width 1600 pitch 6400 (/4 1600)
>[ 10418.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21585f0]
>[ 10418.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21585f0] width 1600 pitch 6400 (/4 1600)
>[ 10418.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214b950]
>[ 10418.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214b950] width 1600 pitch 6400 (/4 1600)
>[ 10418.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21585f0]
>[ 10418.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21585f0] width 1600 pitch 6400 (/4 1600)
>[ 10418.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214b950]
>[ 10418.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214b950] width 1600 pitch 6400 (/4 1600)
>[ 10418.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21585f0]
>[ 10418.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21585f0] width 1600 pitch 6400 (/4 1600)
>[ 10418.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214b950]
>[ 10418.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214b950] width 1600 pitch 6400 (/4 1600)
>[ 10418.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21585f0]
>[ 10418.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21585f0] width 1600 pitch 6400 (/4 1600)
>[ 10418.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214b950]
>[ 10418.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214b950] width 1600 pitch 6400 (/4 1600)
>[ 10418.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21585f0]
>[ 10418.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21585f0] width 1600 pitch 6400 (/4 1600)
>[ 10418.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214b950]
>[ 10418.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214b950] width 1600 pitch 6400 (/4 1600)
>[ 11192.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23de860]
>[ 11192.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23de860] width 1600 pitch 6400 (/4 1600)
>[ 11195.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2201010]
>[ 11195.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2201010] width 1600 pitch 6400 (/4 1600)
>[ 11197.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x243dc70]
>[ 11197.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x243dc70] width 1600 pitch 6400 (/4 1600)
>[ 11197.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x211b0f0]
>[ 11197.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x211b0f0] width 1600 pitch 6400 (/4 1600)
>[ 11197.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21312c0]
>[ 11197.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21312c0] width 1600 pitch 6400 (/4 1600)
>[ 11197.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x211b0f0]
>[ 11197.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x211b0f0] width 1600 pitch 6400 (/4 1600)
>[ 11199.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ef3c0]
>[ 11199.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ef3c0] width 1600 pitch 6400 (/4 1600)
>[ 11199.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f5610]
>[ 11199.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f5610] width 1600 pitch 6400 (/4 1600)
>[ 11199.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ef3c0]
>[ 11199.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ef3c0] width 1600 pitch 6400 (/4 1600)
>[ 11199.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f5610]
>[ 11199.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f5610] width 1600 pitch 6400 (/4 1600)
>[ 11200.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ef3c0]
>[ 11200.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ef3c0] width 1600 pitch 6400 (/4 1600)
>[ 11276.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213a5a0]
>[ 11276.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213a5a0] width 1600 pitch 6400 (/4 1600)
>[ 11276.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23f5610]
>[ 11276.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23f5610] width 1600 pitch 6400 (/4 1600)
>[ 11277.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c8160]
>[ 11277.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c8160] width 1600 pitch 6400 (/4 1600)
>[ 11277.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2159840]
>[ 11277.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2159840] width 1600 pitch 6400 (/4 1600)
>[ 11277.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c8160]
>[ 11277.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c8160] width 1600 pitch 6400 (/4 1600)
>[ 11277.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2159840]
>[ 11277.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2159840] width 1600 pitch 6400 (/4 1600)
>[ 11277.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x241ec10]
>[ 11277.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x241ec10] width 1600 pitch 6400 (/4 1600)
>[ 11277.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2159840]
>[ 11277.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2159840] width 1600 pitch 6400 (/4 1600)
>[ 11277.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d87a0]
>[ 11277.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d87a0] width 1600 pitch 6400 (/4 1600)
>[ 11277.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ef3c0]
>[ 11277.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ef3c0] width 1600 pitch 6400 (/4 1600)
>[ 11277.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c8160]
>[ 11277.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c8160] width 1600 pitch 6400 (/4 1600)
>[ 11283.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d87a0]
>[ 11283.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d87a0] width 1600 pitch 6400 (/4 1600)
>[ 11283.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x241ec10]
>[ 11283.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x241ec10] width 1600 pitch 6400 (/4 1600)
>[ 11283.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ef3c0]
>[ 11283.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ef3c0] width 1600 pitch 6400 (/4 1600)
>[ 11283.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x241ec10]
>[ 11283.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x241ec10] width 1600 pitch 6400 (/4 1600)
>[ 11283.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213a5a0]
>[ 11283.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213a5a0] width 1600 pitch 6400 (/4 1600)
>[ 11283.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x241ec10]
>[ 11283.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x241ec10] width 1600 pitch 6400 (/4 1600)
>[ 11283.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213a5a0]
>[ 11283.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213a5a0] width 1600 pitch 6400 (/4 1600)
>[ 11283.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x241ec10]
>[ 11283.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x241ec10] width 1600 pitch 6400 (/4 1600)
>[ 11283.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c8160]
>[ 11283.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c8160] width 1600 pitch 6400 (/4 1600)
>[ 11283.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x241ec10]
>[ 11283.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x241ec10] width 1600 pitch 6400 (/4 1600)
>[ 11645.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2159840]
>[ 11645.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2159840] width 1600 pitch 6400 (/4 1600)
>[ 11645.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ef3c0]
>[ 11645.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ef3c0] width 1600 pitch 6400 (/4 1600)
>[ 11647.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d0c70]
>[ 11647.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d0c70] width 1600 pitch 6400 (/4 1600)
>[ 11647.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213a5a0]
>[ 11647.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213a5a0] width 1600 pitch 6400 (/4 1600)
>[ 12034.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d6c70]
>[ 12034.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d6c70] width 1600 pitch 6400 (/4 1600)
>[ 12034.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 12034.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 12126.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e2dc0]
>[ 12126.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e2dc0] width 1600 pitch 6400 (/4 1600)
>[ 12153.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 12153.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 12153.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 12153.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 12166.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e02a0]
>[ 12166.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e02a0] width 1600 pitch 6400 (/4 1600)
>[ 12166.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2492100]
>[ 12166.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2492100] width 1600 pitch 6400 (/4 1600)
>[ 12261.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23eabc0]
>[ 12261.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23eabc0] width 1600 pitch 6400 (/4 1600)
>[ 12261.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2362680]
>[ 12261.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2362680] width 1600 pitch 6400 (/4 1600)
>[ 12445.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e6a70]
>[ 12445.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e6a70] width 1600 pitch 6400 (/4 1600)
>[ 12445.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e6a70]
>[ 12445.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e6a70] width 1600 pitch 6400 (/4 1600)
>[ 12766.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd64c0]
>[ 12766.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd64c0] width 1600 pitch 6400 (/4 1600)
>[ 12766.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213c780]
>[ 12767.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213c780] width 1600 pitch 6400 (/4 1600)
>[ 13127.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242e040]
>[ 13127.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242e040] width 1600 pitch 6400 (/4 1600)
>[ 13127.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242e040]
>[ 13127.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242e040] width 1600 pitch 6400 (/4 1600)
>[ 13159.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ea520]
>[ 13159.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ea520] width 1600 pitch 6400 (/4 1600)
>[ 13159.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23d61a0]
>[ 13159.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23d61a0] width 1600 pitch 6400 (/4 1600)
>[ 13159.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23db8b0]
>[ 13159.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23db8b0] width 1600 pitch 6400 (/4 1600)
>[ 13159.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22084e0]
>[ 13159.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22084e0] width 1600 pitch 6400 (/4 1600)
>[ 13159.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22dba60]
>[ 13159.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22dba60] width 1600 pitch 6400 (/4 1600)
>[ 13160.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e2b40]
>[ 13160.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e2b40] width 1600 pitch 6400 (/4 1600)
>[ 13160.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24269a0]
>[ 13160.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24269a0] width 1600 pitch 6400 (/4 1600)
>[ 13160.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2405f10]
>[ 13160.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2405f10] width 1600 pitch 6400 (/4 1600)
>[ 13160.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23dd8e0]
>[ 13160.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23dd8e0] width 1600 pitch 6400 (/4 1600)
>[ 13160.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2491c10]
>[ 13160.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2491c10] width 1600 pitch 6400 (/4 1600)
>[ 13160.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22624b0]
>[ 13160.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22624b0] width 1600 pitch 6400 (/4 1600)
>[ 13160.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23daf80]
>[ 13160.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23daf80] width 1600 pitch 6400 (/4 1600)
>[ 13160.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240aa10]
>[ 13160.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240aa10] width 1600 pitch 6400 (/4 1600)
>[ 13160.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23da3d0]
>[ 13160.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23da3d0] width 1600 pitch 6400 (/4 1600)
>[ 13160.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24285c0]
>[ 13160.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24285c0] width 1600 pitch 6400 (/4 1600)
>[ 13192.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2431eb0]
>[ 13192.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2431eb0] width 1600 pitch 6400 (/4 1600)
>[ 13202.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242b660]
>[ 13202.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242b660] width 1600 pitch 6400 (/4 1600)
>[ 13202.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2447410]
>[ 13202.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2447410] width 1600 pitch 6400 (/4 1600)
>[ 13202.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242b660]
>[ 13203.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242b660] width 1600 pitch 6400 (/4 1600)
>[ 13203.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2447410]
>[ 13203.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2447410] width 1600 pitch 6400 (/4 1600)
>[ 13213.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24132e0]
>[ 13213.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24132e0] width 1600 pitch 6400 (/4 1600)
>[ 13218.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2201010]
>[ 13218.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2201010] width 1600 pitch 6400 (/4 1600)
>[ 13218.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24775d0]
>[ 13218.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24775d0] width 1600 pitch 6400 (/4 1600)
>[ 13218.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2400490]
>[ 13218.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2400490] width 1600 pitch 6400 (/4 1600)
>[ 13218.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24775d0]
>[ 13218.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24775d0] width 1600 pitch 6400 (/4 1600)
>[ 13218.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2400490]
>[ 13218.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2400490] width 1600 pitch 6400 (/4 1600)
>[ 13218.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24775d0]
>[ 13218.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24775d0] width 1600 pitch 6400 (/4 1600)
>[ 13218.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13218.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13218.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24458e0]
>[ 13218.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24458e0] width 1600 pitch 6400 (/4 1600)
>[ 13218.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13218.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13218.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24458e0]
>[ 13218.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24458e0] width 1600 pitch 6400 (/4 1600)
>[ 13218.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13218.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13218.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24458e0]
>[ 13218.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24458e0] width 1600 pitch 6400 (/4 1600)
>[ 13219.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445820]
>[ 13219.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445820] width 1600 pitch 6400 (/4 1600)
>[ 13219.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13219.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13219.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445820]
>[ 13219.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445820] width 1600 pitch 6400 (/4 1600)
>[ 13219.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13219.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13219.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445820]
>[ 13219.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445820] width 1600 pitch 6400 (/4 1600)
>[ 13219.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13219.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13219.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445820]
>[ 13219.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445820] width 1600 pitch 6400 (/4 1600)
>[ 13219.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13219.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13219.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445820]
>[ 13219.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445820] width 1600 pitch 6400 (/4 1600)
>[ 13219.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13220.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13220.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445820]
>[ 13220.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445820] width 1600 pitch 6400 (/4 1600)
>[ 13220.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13220.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13220.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445820]
>[ 13220.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445820] width 1600 pitch 6400 (/4 1600)
>[ 13220.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445980]
>[ 13220.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445980] width 1600 pitch 6400 (/4 1600)
>[ 13220.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445ae0]
>[ 13220.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445ae0] width 1600 pitch 6400 (/4 1600)
>[ 13220.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445a80]
>[ 13220.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445a80] width 1600 pitch 6400 (/4 1600)
>[ 13220.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445730]
>[ 13220.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445730] width 1600 pitch 6400 (/4 1600)
>[ 13221.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2445730]
>[ 13221.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2445730] width 1600 pitch 6400 (/4 1600)
>[ 13221.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24457a0]
>[ 13221.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24457a0] width 1600 pitch 6400 (/4 1600)
>[ 13221.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24457a0]
>[ 13221.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24457a0] width 1600 pitch 6400 (/4 1600)
>[ 13221.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24444d0]
>[ 13221.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24444d0] width 1600 pitch 6400 (/4 1600)
>[ 13221.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24457a0]
>[ 13221.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24457a0] width 1600 pitch 6400 (/4 1600)
>[ 13221.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24458c0]
>[ 13221.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24458c0] width 1600 pitch 6400 (/4 1600)
>[ 13221.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24457a0]
>[ 13221.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24457a0] width 1600 pitch 6400 (/4 1600)
>[ 13221.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24458c0]
>[ 13221.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24458c0] width 1600 pitch 6400 (/4 1600)
>[ 13221.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24457a0]
>[ 13221.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24457a0] width 1600 pitch 6400 (/4 1600)
>[ 13221.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24458c0]
>[ 13221.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24458c0] width 1600 pitch 6400 (/4 1600)
>[ 13221.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24457a0]
>[ 13221.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24457a0] width 1600 pitch 6400 (/4 1600)
>[ 13221.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24458c0]
>[ 13221.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24458c0] width 1600 pitch 6400 (/4 1600)
>[ 13221.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444480]
>[ 13221.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444480] width 1600 pitch 6400 (/4 1600)
>[ 13223.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2471290]
>[ 13223.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2471290] width 1600 pitch 6400 (/4 1600)
>[ 13229.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a05e0]
>[ 13229.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a05e0] width 1600 pitch 6400 (/4 1600)
>[ 13229.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242b390]
>[ 13229.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242b390] width 1600 pitch 6400 (/4 1600)
>[ 13229.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a05e0]
>[ 13229.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a05e0] width 1600 pitch 6400 (/4 1600)
>[ 13229.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x249fdc0]
>[ 13229.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x249fdc0] width 1600 pitch 6400 (/4 1600)
>[ 13236.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24775d0]
>[ 13236.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24775d0] width 1600 pitch 6400 (/4 1600)
>[ 13238.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2201010]
>[ 13238.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2201010] width 1600 pitch 6400 (/4 1600)
>[ 13257.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2432a70]
>[ 13257.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2432a70] width 1600 pitch 6400 (/4 1600)
>[ 13257.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x231f200]
>[ 13257.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x231f200] width 1600 pitch 6400 (/4 1600)
>[ 13257.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2432a70]
>[ 13257.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2432a70] width 1600 pitch 6400 (/4 1600)
>[ 13257.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x231f200]
>[ 13257.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x231f200] width 1600 pitch 6400 (/4 1600)
>[ 13257.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2432a70]
>[ 13257.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2432a70] width 1600 pitch 6400 (/4 1600)
>[ 13257.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240cf50]
>[ 13257.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240cf50] width 1600 pitch 6400 (/4 1600)
>[ 13257.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2432a70]
>[ 13257.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2432a70] width 1600 pitch 6400 (/4 1600)
>[ 13257.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240cf50]
>[ 13257.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240cf50] width 1600 pitch 6400 (/4 1600)
>[ 13257.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2432a70]
>[ 13257.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2432a70] width 1600 pitch 6400 (/4 1600)
>[ 13257.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240cf50]
>[ 13257.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240cf50] width 1600 pitch 6400 (/4 1600)
>[ 13257.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2432a70]
>[ 13257.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2432a70] width 1600 pitch 6400 (/4 1600)
>[ 13257.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240cf50]
>[ 13257.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240cf50] width 1600 pitch 6400 (/4 1600)
>[ 13257.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24072c0]
>[ 13257.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24072c0] width 1600 pitch 6400 (/4 1600)
>[ 13257.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240cf50]
>[ 13257.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240cf50] width 1600 pitch 6400 (/4 1600)
>[ 13257.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2477a20]
>[ 13257.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2477a20] width 1600 pitch 6400 (/4 1600)
>[ 13258.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2478db0]
>[ 13258.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2478db0] width 1600 pitch 6400 (/4 1600)
>[ 13258.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245b260]
>[ 13258.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245b260] width 1600 pitch 6400 (/4 1600)
>[ 13258.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2478db0]
>[ 13258.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2478db0] width 1600 pitch 6400 (/4 1600)
>[ 13258.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245b260]
>[ 13258.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245b260] width 1600 pitch 6400 (/4 1600)
>[ 13258.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2478db0]
>[ 13258.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2478db0] width 1600 pitch 6400 (/4 1600)
>[ 13258.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245b260]
>[ 13258.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245b260] width 1600 pitch 6400 (/4 1600)
>[ 13258.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2478db0]
>[ 13258.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2478db0] width 1600 pitch 6400 (/4 1600)
>[ 13258.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245b260]
>[ 13258.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245b260] width 1600 pitch 6400 (/4 1600)
>[ 13258.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2478db0]
>[ 13258.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2478db0] width 1600 pitch 6400 (/4 1600)
>[ 13258.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245b260]
>[ 13258.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245b260] width 1600 pitch 6400 (/4 1600)
>[ 13258.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2478db0]
>[ 13258.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2478db0] width 1600 pitch 6400 (/4 1600)
>[ 13258.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245b260]
>[ 13258.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245b260] width 1600 pitch 6400 (/4 1600)
>[ 13258.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2478db0]
>[ 13258.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2478db0] width 1600 pitch 6400 (/4 1600)
>[ 13258.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245b260]
>[ 13258.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245b260] width 1600 pitch 6400 (/4 1600)
>[ 13261.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2287670]
>[ 13261.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2287670] width 1600 pitch 6400 (/4 1600)
>[ 13261.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13261.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13261.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2287670]
>[ 13261.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2287670] width 1600 pitch 6400 (/4 1600)
>[ 13264.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13264.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13264.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13264.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13264.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13264.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13264.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13264.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13264.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13264.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13264.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13264.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13264.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13264.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13265.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13265.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13265.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13265.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13265.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13265.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13265.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13265.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13265.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13265.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13265.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13265.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13265.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13266.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13266.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13266.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13266.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13266.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13266.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13266.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13266.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13266.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13266.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13266.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13266.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13266.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13266.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13266.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13268.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258a240]
>[ 13268.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258a240] width 1600 pitch 6400 (/4 1600)
>[ 13277.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24720a0]
>[ 13278.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24720a0] width 1600 pitch 6400 (/4 1600)
>[ 13278.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2449080]
>[ 13278.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2449080] width 1600 pitch 6400 (/4 1600)
>[ 13278.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2474010]
>[ 13278.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2474010] width 1600 pitch 6400 (/4 1600)
>[ 13278.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e250]
>[ 13278.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e250] width 1600 pitch 6400 (/4 1600)
>[ 13320.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7130]
>[ 13320.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7130] width 1600 pitch 6400 (/4 1600)
>[ 13320.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7130]
>[ 13320.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7130] width 1600 pitch 6400 (/4 1600)
>[ 13320.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7130]
>[ 13320.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7130] width 1600 pitch 6400 (/4 1600)
>[ 13320.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258c070]
>[ 13320.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258c070] width 1600 pitch 6400 (/4 1600)
>[ 13538.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22fdfc0]
>[ 13538.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22fdfc0] width 1600 pitch 6400 (/4 1600)
>[ 13538.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc60]
>[ 13538.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc60] width 1600 pitch 6400 (/4 1600)
>[ 13538.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22fdfc0]
>[ 13538.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22fdfc0] width 1600 pitch 6400 (/4 1600)
>[ 13538.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586080]
>[ 13538.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586080] width 1600 pitch 6400 (/4 1600)
>[ 13538.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25907b0]
>[ 13538.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25907b0] width 1600 pitch 6400 (/4 1600)
>[ 13538.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25907b0]
>[ 13538.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25907b0] width 1600 pitch 6400 (/4 1600)
>[ 13538.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc60]
>[ 13538.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc60] width 1600 pitch 6400 (/4 1600)
>[ 13538.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22fdfc0]
>[ 13538.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22fdfc0] width 1600 pitch 6400 (/4 1600)
>[ 13539.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25907b0]
>[ 13539.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25907b0] width 1600 pitch 6400 (/4 1600)
>[ 13550.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc60]
>[ 13550.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc60] width 1600 pitch 6400 (/4 1600)
>[ 13550.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586080]
>[ 13550.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586080] width 1600 pitch 6400 (/4 1600)
>[ 13550.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc60]
>[ 13550.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc60] width 1600 pitch 6400 (/4 1600)
>[ 13550.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25907b0]
>[ 13550.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25907b0] width 1600 pitch 6400 (/4 1600)
>[ 13550.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22fdfc0]
>[ 13550.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22fdfc0] width 1600 pitch 6400 (/4 1600)
>[ 13550.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25907b0]
>[ 13550.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25907b0] width 1600 pitch 6400 (/4 1600)
>[ 13550.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x246dc60]
>[ 13550.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x246dc60] width 1600 pitch 6400 (/4 1600)
>[ 13550.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25907b0]
>[ 13550.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25907b0] width 1600 pitch 6400 (/4 1600)
>[ 13737.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25979c0]
>[ 13737.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25979c0] width 1600 pitch 6400 (/4 1600)
>[ 13737.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2580910]
>[ 13737.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2580910] width 1600 pitch 6400 (/4 1600)
>[ 13790.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a05c0]
>[ 13790.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a05c0] width 1600 pitch 6400 (/4 1600)
>[ 13790.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a3430]
>[ 13790.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a3430] width 1600 pitch 6400 (/4 1600)
>[ 14150.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25306b0]
>[ 14150.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25306b0] width 1600 pitch 6400 (/4 1600)
>[ 14150.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2542a40]
>[ 14150.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2542a40] width 1600 pitch 6400 (/4 1600)
>[ 14169.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24638d0]
>[ 14169.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24638d0] width 1600 pitch 6400 (/4 1600)
>[ 14169.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2596200]
>[ 14169.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2596200] width 1600 pitch 6400 (/4 1600)
>[ 14596.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2596200]
>[ 14596.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2596200] width 1600 pitch 6400 (/4 1600)
>[ 14596.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213bc10]
>[ 14597.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213bc10] width 1600 pitch 6400 (/4 1600)
>[ 14597.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2542a40]
>[ 14597.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2542a40] width 1600 pitch 6400 (/4 1600)
>[ 14597.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213bc10]
>[ 14597.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213bc10] width 1600 pitch 6400 (/4 1600)
>[ 14598.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213bc10]
>[ 14598.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213bc10] width 1600 pitch 6400 (/4 1600)
>[ 14598.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25306b0]
>[ 14598.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25306b0] width 1600 pitch 6400 (/4 1600)
>[ 14598.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22fe1a0]
>[ 14598.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22fe1a0] width 1600 pitch 6400 (/4 1600)
>[ 14598.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2596200]
>[ 14598.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2596200] width 1600 pitch 6400 (/4 1600)
>[ 14598.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213bc10]
>[ 14598.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213bc10] width 1600 pitch 6400 (/4 1600)
>[ 14598.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2596200]
>[ 14598.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2596200] width 1600 pitch 6400 (/4 1600)
>[ 14598.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25306b0]
>[ 14598.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25306b0] width 1600 pitch 6400 (/4 1600)
>[ 14599.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213bc10]
>[ 14599.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213bc10] width 1600 pitch 6400 (/4 1600)
>[ 14599.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25306b0]
>[ 14599.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25306b0] width 1600 pitch 6400 (/4 1600)
>[ 14599.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22fe1a0]
>[ 14599.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22fe1a0] width 1600 pitch 6400 (/4 1600)
>[ 14599.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2542a40]
>[ 14600.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2542a40] width 1600 pitch 6400 (/4 1600)
>[ 14600.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x213bc10]
>[ 14600.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x213bc10] width 1600 pitch 6400 (/4 1600)
>[ 14600.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2596200]
>[ 14600.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2596200] width 1600 pitch 6400 (/4 1600)
>[ 14662.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14662.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14663.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14663.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14663.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2582ac0]
>[ 14663.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2582ac0] width 1600 pitch 6400 (/4 1600)
>[ 14663.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f500]
>[ 14663.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f500] width 1600 pitch 6400 (/4 1600)
>[ 14663.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14663.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14663.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14663.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14665.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14665.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14665.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14665.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14665.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14665.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14665.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14665.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14665.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14665.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14666.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14666.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14670.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14670.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14670.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14670.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14670.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2465350]
>[ 14670.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2465350] width 1600 pitch 6400 (/4 1600)
>[ 14670.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f500]
>[ 14670.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f500] width 1600 pitch 6400 (/4 1600)
>[ 14670.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14670.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14670.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253ac50]
>[ 14670.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253ac50] width 1600 pitch 6400 (/4 1600)
>[ 14670.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f500]
>[ 14670.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f500] width 1600 pitch 6400 (/4 1600)
>[ 14670.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f100]
>[ 14670.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f100] width 1600 pitch 6400 (/4 1600)
>[ 14670.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2465350]
>[ 14670.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2465350] width 1600 pitch 6400 (/4 1600)
>[ 14670.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f500]
>[ 14670.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f500] width 1600 pitch 6400 (/4 1600)
>[ 14678.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253a900]
>[ 14678.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253a900] width 1600 pitch 6400 (/4 1600)
>[ 14678.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f910]
>[ 14678.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f910] width 1600 pitch 6400 (/4 1600)
>[ 14698.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2554ad0]
>[ 14698.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2554ad0] width 1600 pitch 6400 (/4 1600)
>[ 14698.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2554ad0]
>[ 14698.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2554ad0] width 1600 pitch 6400 (/4 1600)
>[ 14841.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23fd060]
>[ 14841.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23fd060] width 1600 pitch 6400 (/4 1600)
>[ 14841.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25798a0]
>[ 14841.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25798a0] width 1600 pitch 6400 (/4 1600)
>[ 14862.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x256c290]
>[ 14862.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x256c290] width 1600 pitch 6400 (/4 1600)
>[ 14862.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254a320]
>[ 14862.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254a320] width 1600 pitch 6400 (/4 1600)
>[ 14972.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255f3e0]
>[ 14972.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255f3e0] width 1600 pitch 6400 (/4 1600)
>[ 14972.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255f3e0]
>[ 14972.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255f3e0] width 1600 pitch 6400 (/4 1600)
>[ 14972.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255eeb0]
>[ 14972.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255eeb0] width 1600 pitch 6400 (/4 1600)
>[ 14973.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254ad20]
>[ 14973.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254ad20] width 1600 pitch 6400 (/4 1600)
>[ 14973.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1920]
>[ 14973.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1920] width 1600 pitch 6400 (/4 1600)
>[ 14973.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255f3e0]
>[ 14973.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255f3e0] width 1600 pitch 6400 (/4 1600)
>[ 14973.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bc170]
>[ 14973.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bc170] width 1600 pitch 6400 (/4 1600)
>[ 14973.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255eeb0]
>[ 14973.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255eeb0] width 1600 pitch 6400 (/4 1600)
>[ 14973.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254ad20]
>[ 14973.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254ad20] width 1600 pitch 6400 (/4 1600)
>[ 14973.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254ad20]
>[ 14973.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254ad20] width 1600 pitch 6400 (/4 1600)
>[ 14973.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255eeb0]
>[ 14973.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255eeb0] width 1600 pitch 6400 (/4 1600)
>[ 14992.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254ad20]
>[ 14992.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254ad20] width 1600 pitch 6400 (/4 1600)
>[ 14992.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255f3e0]
>[ 14993.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255f3e0] width 1600 pitch 6400 (/4 1600)
>[ 15032.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24bbec0]
>[ 15032.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24bbec0] width 1600 pitch 6400 (/4 1600)
>[ 15032.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255f3e0]
>[ 15032.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255f3e0] width 1600 pitch 6400 (/4 1600)
>[ 16174.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c98a0]
>[ 16174.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c98a0] width 1600 pitch 6400 (/4 1600)
>[ 16174.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c4700]
>[ 16174.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c4700] width 1600 pitch 6400 (/4 1600)
>[ 16174.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c98a0]
>[ 16174.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c98a0] width 1600 pitch 6400 (/4 1600)
>[ 16174.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2528720]
>[ 16174.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2528720] width 1600 pitch 6400 (/4 1600)
>[ 16174.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c98a0]
>[ 16174.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c98a0] width 1600 pitch 6400 (/4 1600)
>[ 16174.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c4700]
>[ 16175.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c4700] width 1600 pitch 6400 (/4 1600)
>[ 16175.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2528720]
>[ 16175.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2528720] width 1600 pitch 6400 (/4 1600)
>[ 16175.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2528720]
>[ 16175.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2528720] width 1600 pitch 6400 (/4 1600)
>[ 16176.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c98a0]
>[ 16176.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c98a0] width 1600 pitch 6400 (/4 1600)
>[ 16176.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c4700]
>[ 16176.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c4700] width 1600 pitch 6400 (/4 1600)
>[ 16176.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c98a0]
>[ 16176.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c98a0] width 1600 pitch 6400 (/4 1600)
>[ 16176.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2528720]
>[ 16176.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2528720] width 1600 pitch 6400 (/4 1600)
>[ 16176.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c98a0]
>[ 16176.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c98a0] width 1600 pitch 6400 (/4 1600)
>[ 16176.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c4700]
>[ 16176.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c4700] width 1600 pitch 6400 (/4 1600)
>[ 16176.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c98a0]
>[ 16176.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c98a0] width 1600 pitch 6400 (/4 1600)
>[ 16176.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c4700]
>[ 16176.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c4700] width 1600 pitch 6400 (/4 1600)
>[ 16176.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c98a0]
>[ 16176.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c98a0] width 1600 pitch 6400 (/4 1600)
>[ 16180.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c4700]
>[ 16180.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c4700] width 1600 pitch 6400 (/4 1600)
>[ 16180.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c4700]
>[ 16180.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c4700] width 1600 pitch 6400 (/4 1600)
>[ 16345.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c13c0]
>[ 16345.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c13c0] width 1600 pitch 6400 (/4 1600)
>[ 16345.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2556390]
>[ 16345.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2556390] width 1600 pitch 6400 (/4 1600)
>[ 16427.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c2a00]
>[ 16427.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c2a00] width 1600 pitch 6400 (/4 1600)
>[ 16427.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c2a00]
>[ 16427.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c2a00] width 1600 pitch 6400 (/4 1600)
>[ 16594.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d0b70]
>[ 16594.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d0b70] width 1600 pitch 6400 (/4 1600)
>[ 16594.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ca7f0]
>[ 16594.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ca7f0] width 1600 pitch 6400 (/4 1600)
>[ 16890.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f5280]
>[ 16890.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f5280] width 1600 pitch 6400 (/4 1600)
>[ 16890.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f5280]
>[ 16890.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f5280] width 1600 pitch 6400 (/4 1600)
>[ 16890.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f7140]
>[ 16890.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f7140] width 1600 pitch 6400 (/4 1600)
>[ 16891.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f7140]
>[ 16891.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f7140] width 1600 pitch 6400 (/4 1600)
>[ 16891.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16891.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16891.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16891.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16891.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f7140]
>[ 16891.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f7140] width 1600 pitch 6400 (/4 1600)
>[ 16891.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16891.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16891.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2519660]
>[ 16891.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2519660] width 1600 pitch 6400 (/4 1600)
>[ 16891.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16891.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16891.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2519660]
>[ 16891.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2519660] width 1600 pitch 6400 (/4 1600)
>[ 16892.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2519660]
>[ 16892.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2519660] width 1600 pitch 6400 (/4 1600)
>[ 16896.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16896.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16896.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f7140]
>[ 16896.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f7140] width 1600 pitch 6400 (/4 1600)
>[ 16896.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16896.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16896.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2519660]
>[ 16896.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2519660] width 1600 pitch 6400 (/4 1600)
>[ 16896.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16896.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16896.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2519660]
>[ 16896.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2519660] width 1600 pitch 6400 (/4 1600)
>[ 16896.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16896.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16896.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2519660]
>[ 16896.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2519660] width 1600 pitch 6400 (/4 1600)
>[ 16896.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16896.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16896.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2519660]
>[ 16896.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2519660] width 1600 pitch 6400 (/4 1600)
>[ 16896.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517490]
>[ 16896.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517490] width 1600 pitch 6400 (/4 1600)
>[ 16898.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24c9e40]
>[ 16898.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24c9e40] width 1600 pitch 6400 (/4 1600)
>[ 16898.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251c040]
>[ 16898.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251c040] width 1600 pitch 6400 (/4 1600)
>[ 16939.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251f910]
>[ 16939.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251f910] width 1600 pitch 6400 (/4 1600)
>[ 16939.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2573120]
>[ 16939.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2573120] width 1600 pitch 6400 (/4 1600)
>[ 17028.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2515a40]
>[ 17028.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2515a40] width 1600 pitch 6400 (/4 1600)
>[ 17028.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fbf90]
>[ 17028.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fbf90] width 1600 pitch 6400 (/4 1600)
>[ 17182.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fbf90]
>[ 17182.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fbf90] width 1600 pitch 6400 (/4 1600)
>[ 17182.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25039b0]
>[ 17182.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25039b0] width 1600 pitch 6400 (/4 1600)
>[ 17183.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2505230]
>[ 17183.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2505230] width 1600 pitch 6400 (/4 1600)
>[ 17183.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fbf90]
>[ 17183.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fbf90] width 1600 pitch 6400 (/4 1600)
>[ 17183.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24be2e0]
>[ 17183.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24be2e0] width 1600 pitch 6400 (/4 1600)
>[ 17183.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25039b0]
>[ 17183.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25039b0] width 1600 pitch 6400 (/4 1600)
>[ 17183.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fbf90]
>[ 17183.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fbf90] width 1600 pitch 6400 (/4 1600)
>[ 17183.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25039b0]
>[ 17183.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25039b0] width 1600 pitch 6400 (/4 1600)
>[ 17183.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2505230]
>[ 17183.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2505230] width 1600 pitch 6400 (/4 1600)
>[ 17183.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fbf90]
>[ 17183.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fbf90] width 1600 pitch 6400 (/4 1600)
>[ 17186.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25039b0]
>[ 17186.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25039b0] width 1600 pitch 6400 (/4 1600)
>[ 17186.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fbf90]
>[ 17186.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fbf90] width 1600 pitch 6400 (/4 1600)
>[ 17186.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25039b0]
>[ 17186.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25039b0] width 1600 pitch 6400 (/4 1600)
>[ 17186.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24be2e0]
>[ 17186.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24be2e0] width 1600 pitch 6400 (/4 1600)
>[ 17186.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2505230]
>[ 17186.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2505230] width 1600 pitch 6400 (/4 1600)
>[ 17186.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24be2e0]
>[ 17186.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24be2e0] width 1600 pitch 6400 (/4 1600)
>[ 17186.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25039b0]
>[ 17186.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25039b0] width 1600 pitch 6400 (/4 1600)
>[ 17186.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2505230]
>[ 17186.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2505230] width 1600 pitch 6400 (/4 1600)
>[ 17186.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24fbf90]
>[ 17186.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24fbf90] width 1600 pitch 6400 (/4 1600)
>[ 17186.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2505230]
>[ 17186.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2505230] width 1600 pitch 6400 (/4 1600)
>[ 17548.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a4f0]
>[ 17548.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a4f0] width 1600 pitch 6400 (/4 1600)
>[ 17548.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c57920]
>[ 17548.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c57920] width 1600 pitch 6400 (/4 1600)
>[ 17559.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250d920]
>[ 17559.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250d920] width 1600 pitch 6400 (/4 1600)
>[ 17559.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c57920]
>[ 17559.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c57920] width 1600 pitch 6400 (/4 1600)
>[ 17559.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e00e0]
>[ 17559.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e00e0] width 1600 pitch 6400 (/4 1600)
>[ 17559.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x250dc30]
>[ 17559.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x250dc30] width 1600 pitch 6400 (/4 1600)
>[ 17863.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a2c0]
>[ 17863.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a2c0] width 1600 pitch 6400 (/4 1600)
>[ 17864.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5c800]
>[ 17864.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5c800] width 1600 pitch 6400 (/4 1600)
>[ 17907.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a2c0]
>[ 17907.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a2c0] width 1600 pitch 6400 (/4 1600)
>[ 17907.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2500670]
>[ 17907.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2500670] width 1600 pitch 6400 (/4 1600)
>[ 17907.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a2c0]
>[ 17907.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a2c0] width 1600 pitch 6400 (/4 1600)
>[ 17907.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251b440]
>[ 17907.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251b440] width 1600 pitch 6400 (/4 1600)
>[ 17907.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a2c0]
>[ 17907.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a2c0] width 1600 pitch 6400 (/4 1600)
>[ 17907.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c598f0]
>[ 17907.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c598f0] width 1600 pitch 6400 (/4 1600)
>[ 17907.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a2c0]
>[ 17907.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a2c0] width 1600 pitch 6400 (/4 1600)
>[ 17907.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c60250]
>[ 17907.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c60250] width 1600 pitch 6400 (/4 1600)
>[ 17907.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a2c0]
>[ 17907.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a2c0] width 1600 pitch 6400 (/4 1600)
>[ 17907.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c600d0]
>[ 17907.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c600d0] width 1600 pitch 6400 (/4 1600)
>[ 17907.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251b440]
>[ 17907.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251b440] width 1600 pitch 6400 (/4 1600)
>[ 17910.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251b440]
>[ 17910.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251b440] width 1600 pitch 6400 (/4 1600)
>[ 17910.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c598f0]
>[ 17910.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c598f0] width 1600 pitch 6400 (/4 1600)
>[ 17910.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251b440]
>[ 17910.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251b440] width 1600 pitch 6400 (/4 1600)
>[ 17910.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c60250]
>[ 17910.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c60250] width 1600 pitch 6400 (/4 1600)
>[ 17910.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251b440]
>[ 17910.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251b440] width 1600 pitch 6400 (/4 1600)
>[ 17910.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c600d0]
>[ 17910.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c600d0] width 1600 pitch 6400 (/4 1600)
>[ 17910.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a2c0]
>[ 17910.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a2c0] width 1600 pitch 6400 (/4 1600)
>[ 17910.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c598f0]
>[ 17910.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c598f0] width 1600 pitch 6400 (/4 1600)
>[ 17910.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c60250]
>[ 17910.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c60250] width 1600 pitch 6400 (/4 1600)
>[ 17910.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c5a2c0]
>[ 17910.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c5a2c0] width 1600 pitch 6400 (/4 1600)
>[ 17910.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c60250]
>[ 17910.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c60250] width 1600 pitch 6400 (/4 1600)
>[ 18044.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4de00]
>[ 18044.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4de00] width 1600 pitch 6400 (/4 1600)
>[ 18044.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e1670]
>[ 18044.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e1670] width 1600 pitch 6400 (/4 1600)
>[ 18044.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x256f6c0]
>[ 18044.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x256f6c0] width 1600 pitch 6400 (/4 1600)
>[ 18044.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e7280]
>[ 18044.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e7280] width 1600 pitch 6400 (/4 1600)
>[ 18339.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f2a00]
>[ 18339.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f2a00] width 1600 pitch 6400 (/4 1600)
>[ 18339.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x256d650]
>[ 18339.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x256d650] width 1600 pitch 6400 (/4 1600)
>[ 19186.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e7550]
>[ 19186.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e7550] width 1600 pitch 6400 (/4 1600)
>[ 19186.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e15a0]
>[ 19186.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e15a0] width 1600 pitch 6400 (/4 1600)
>[ 19341.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c763f0]
>[ 19341.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c763f0] width 1600 pitch 6400 (/4 1600)
>[ 19341.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c75f30]
>[ 19341.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c75f30] width 1600 pitch 6400 (/4 1600)
>[ 19634.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c782c0]
>[ 19634.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c782c0] width 1600 pitch 6400 (/4 1600)
>[ 19634.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c832f0]
>[ 19634.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c832f0] width 1600 pitch 6400 (/4 1600)
>[ 20683.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc4c0]
>[ 20683.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc4c0] width 1600 pitch 6400 (/4 1600)
>[ 20683.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc9a0]
>[ 20683.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc9a0] width 1600 pitch 6400 (/4 1600)
>[ 20683.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc4c0]
>[ 20683.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc4c0] width 1600 pitch 6400 (/4 1600)
>[ 20684.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc9a0]
>[ 20684.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc9a0] width 1600 pitch 6400 (/4 1600)
>[ 20684.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc4c0]
>[ 20684.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc4c0] width 1600 pitch 6400 (/4 1600)
>[ 20684.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc9a0]
>[ 20684.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc9a0] width 1600 pitch 6400 (/4 1600)
>[ 20684.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc4c0]
>[ 20684.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc4c0] width 1600 pitch 6400 (/4 1600)
>[ 20684.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc9a0]
>[ 20684.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc9a0] width 1600 pitch 6400 (/4 1600)
>[ 20684.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc4c0]
>[ 20684.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc4c0] width 1600 pitch 6400 (/4 1600)
>[ 20684.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc9a0]
>[ 20684.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc9a0] width 1600 pitch 6400 (/4 1600)
>[ 20684.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdc4c0]
>[ 20684.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdc4c0] width 1600 pitch 6400 (/4 1600)
>[ 20685.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf46e0]
>[ 20685.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf46e0] width 1600 pitch 6400 (/4 1600)
>[ 20686.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20686.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20686.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20686.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20686.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf46e0]
>[ 20686.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf46e0] width 1600 pitch 6400 (/4 1600)
>[ 20686.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20686.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20686.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf46e0]
>[ 20686.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf46e0] width 1600 pitch 6400 (/4 1600)
>[ 20686.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20686.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20686.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd9b00]
>[ 20686.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd9b00] width 1600 pitch 6400 (/4 1600)
>[ 20686.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20686.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20686.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd9b00]
>[ 20686.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd9b00] width 1600 pitch 6400 (/4 1600)
>[ 20686.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20686.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20686.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd9b00]
>[ 20686.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd9b00] width 1600 pitch 6400 (/4 1600)
>[ 20686.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20686.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20686.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd9b00]
>[ 20686.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd9b00] width 1600 pitch 6400 (/4 1600)
>[ 20686.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20686.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20686.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd9b00]
>[ 20687.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd9b00] width 1600 pitch 6400 (/4 1600)
>[ 20687.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d185d0]
>[ 20687.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d185d0] width 1600 pitch 6400 (/4 1600)
>[ 20687.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd9b00]
>[ 20687.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd9b00] width 1600 pitch 6400 (/4 1600)
>[ 20687.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ce9000]
>[ 20687.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ce9000] width 1600 pitch 6400 (/4 1600)
>[ 20687.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd9b00]
>[ 20687.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd9b00] width 1600 pitch 6400 (/4 1600)
>[ 20687.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd8da0]
>[ 20687.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd8da0] width 1600 pitch 6400 (/4 1600)
>[ 20687.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd9b00]
>[ 20687.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd9b00] width 1600 pitch 6400 (/4 1600)
>[ 20687.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d38940]
>[ 20687.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d38940] width 1600 pitch 6400 (/4 1600)
>[ 20687.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20687.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20687.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20687.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20687.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20688.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20688.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20688.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20688.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20688.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20688.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20688.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20688.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20688.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20688.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20688.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20688.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20688.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20688.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20688.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20688.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20688.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20688.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20688.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20688.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20688.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20688.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20688.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20688.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20688.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20688.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20688.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20688.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1bf80]
>[ 20689.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1bf80] width 1600 pitch 6400 (/4 1600)
>[ 20689.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1c350]
>[ 20689.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1c350] width 1600 pitch 6400 (/4 1600)
>[ 20690.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd80a0]
>[ 20690.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd80a0] width 1600 pitch 6400 (/4 1600)
>[ 20691.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd80a0]
>[ 20691.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd80a0] width 1600 pitch 6400 (/4 1600)
>[ 20691.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67650]
>[ 20691.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67650] width 1600 pitch 6400 (/4 1600)
>[ 20691.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20691.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20691.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67650]
>[ 20691.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67650] width 1600 pitch 6400 (/4 1600)
>[ 20691.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20691.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20691.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67650]
>[ 20691.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67650] width 1600 pitch 6400 (/4 1600)
>[ 20691.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20691.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20691.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67650]
>[ 20691.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67650] width 1600 pitch 6400 (/4 1600)
>[ 20692.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20692.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20692.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67650]
>[ 20692.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67650] width 1600 pitch 6400 (/4 1600)
>[ 20692.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20692.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20692.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c67650]
>[ 20692.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c67650] width 1600 pitch 6400 (/4 1600)
>[ 20692.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19520]
>[ 20692.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19520] width 1600 pitch 6400 (/4 1600)
>[ 20692.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd0980]
>[ 20692.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd0980] width 1600 pitch 6400 (/4 1600)
>[ 20693.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aac10]
>[ 20693.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aac10] width 1600 pitch 6400 (/4 1600)
>[ 20693.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 20693.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 20697.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227fc80]
>[ 20697.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227fc80] width 1600 pitch 6400 (/4 1600)
>[ 20705.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248dea0]
>[ 20705.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248dea0] width 1600 pitch 6400 (/4 1600)
>[ 20706.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2165bb0]
>[ 20706.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2165bb0] width 1600 pitch 6400 (/4 1600)
>[ 20706.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b4e00]
>[ 20706.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b4e00] width 1600 pitch 6400 (/4 1600)
>[ 20706.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x239e460]
>[ 20706.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x239e460] width 1600 pitch 6400 (/4 1600)
>[ 20706.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c6630]
>[ 20706.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c6630] width 1600 pitch 6400 (/4 1600)
>[ 20728.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d2460]
>[ 20728.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d2460] width 1600 pitch 6400 (/4 1600)
>[ 20732.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdb040]
>[ 20732.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdb040] width 1600 pitch 6400 (/4 1600)
>[ 20738.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2254ed0]
>[ 20738.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2254ed0] width 1600 pitch 6400 (/4 1600)
>[ 20738.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259e0f0]
>[ 20738.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259e0f0] width 1600 pitch 6400 (/4 1600)
>[ 20738.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25952c0]
>[ 20738.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25952c0] width 1600 pitch 6400 (/4 1600)
>[ 20738.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x239e460]
>[ 20738.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x239e460] width 1600 pitch 6400 (/4 1600)
>[ 20738.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227fb00]
>[ 20738.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227fb00] width 1600 pitch 6400 (/4 1600)
>[ 20738.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cab360]
>[ 20738.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cab360] width 1600 pitch 6400 (/4 1600)
>[ 20738.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21d2d90]
>[ 20738.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21d2d90] width 1600 pitch 6400 (/4 1600)
>[ 20738.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fceb0]
>[ 20738.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fceb0] width 1600 pitch 6400 (/4 1600)
>[ 20738.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21d2d90]
>[ 20738.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21d2d90] width 1600 pitch 6400 (/4 1600)
>[ 20738.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fceb0]
>[ 20738.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fceb0] width 1600 pitch 6400 (/4 1600)
>[ 20738.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21d2d90]
>[ 20738.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21d2d90] width 1600 pitch 6400 (/4 1600)
>[ 20738.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fceb0]
>[ 20738.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fceb0] width 1600 pitch 6400 (/4 1600)
>[ 20774.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x227fc80]
>[ 20774.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x227fc80] width 1600 pitch 6400 (/4 1600)
>[ 20777.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2257310]
>[ 20777.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2257310] width 1600 pitch 6400 (/4 1600)
>[ 20777.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d19890]
>[ 20777.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d19890] width 1600 pitch 6400 (/4 1600)
>[ 20777.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2257310]
>[ 20777.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2257310] width 1600 pitch 6400 (/4 1600)
>[ 20779.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f500]
>[ 20779.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f500] width 1600 pitch 6400 (/4 1600)
>[ 20779.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b4e00]
>[ 20779.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b4e00] width 1600 pitch 6400 (/4 1600)
>[ 20779.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cdaaf0]
>[ 20779.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cdaaf0] width 1600 pitch 6400 (/4 1600)
>[ 20779.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ba7a0]
>[ 20779.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ba7a0] width 1600 pitch 6400 (/4 1600)
>[ 20779.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25952c0]
>[ 20779.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25952c0] width 1600 pitch 6400 (/4 1600)
>[ 20779.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2472710]
>[ 20779.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2472710] width 1600 pitch 6400 (/4 1600)
>[ 20779.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226ca80]
>[ 20779.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226ca80] width 1600 pitch 6400 (/4 1600)
>[ 20779.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 20779.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 20779.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226ca80]
>[ 20779.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226ca80] width 1600 pitch 6400 (/4 1600)
>[ 20784.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 20784.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 20784.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d8d60]
>[ 20784.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d8d60] width 1600 pitch 6400 (/4 1600)
>[ 20784.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2395930]
>[ 20784.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2395930] width 1600 pitch 6400 (/4 1600)
>[ 20784.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d8d60]
>[ 20784.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d8d60] width 1600 pitch 6400 (/4 1600)
>[ 20784.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2395930]
>[ 20784.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2395930] width 1600 pitch 6400 (/4 1600)
>[ 20784.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d8d60]
>[ 20784.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d8d60] width 1600 pitch 6400 (/4 1600)
>[ 20784.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2395930]
>[ 20784.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2395930] width 1600 pitch 6400 (/4 1600)
>[ 20784.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d8d60]
>[ 20784.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d8d60] width 1600 pitch 6400 (/4 1600)
>[ 20784.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e02a0]
>[ 20784.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e02a0] width 1600 pitch 6400 (/4 1600)
>[ 20784.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d8d60]
>[ 20784.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d8d60] width 1600 pitch 6400 (/4 1600)
>[ 20784.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e02a0]
>[ 20784.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e02a0] width 1600 pitch 6400 (/4 1600)
>[ 20784.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d8d60]
>[ 20784.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d8d60] width 1600 pitch 6400 (/4 1600)
>[ 20784.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23e02a0]
>[ 20784.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23e02a0] width 1600 pitch 6400 (/4 1600)
>[ 20784.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d8d60]
>[ 20784.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d8d60] width 1600 pitch 6400 (/4 1600)
>[ 20785.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320580]
>[ 20785.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320580] width 1600 pitch 6400 (/4 1600)
>[ 20785.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b62b0]
>[ 20785.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b62b0] width 1600 pitch 6400 (/4 1600)
>[ 20785.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a15e0]
>[ 20785.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a15e0] width 1600 pitch 6400 (/4 1600)
>[ 20785.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 20785.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 20785.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a15e0]
>[ 20786.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a15e0] width 1600 pitch 6400 (/4 1600)
>[ 20786.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 20786.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 20786.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a15e0]
>[ 20786.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a15e0] width 1600 pitch 6400 (/4 1600)
>[ 20786.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 20786.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 20786.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a15e0]
>[ 20786.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a15e0] width 1600 pitch 6400 (/4 1600)
>[ 20786.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 20786.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 20786.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a15e0]
>[ 20786.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a15e0] width 1600 pitch 6400 (/4 1600)
>[ 20786.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 20786.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 20786.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a15e0]
>[ 20786.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a15e0] width 1600 pitch 6400 (/4 1600)
>[ 20793.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20793.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20793.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20793.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20793.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20793.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20793.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20793.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20793.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20793.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20793.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20793.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20793.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20793.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20793.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20793.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20794.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20794.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20794.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20794.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20794.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20794.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20794.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20794.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20795.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20795.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20795.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x238d430]
>[ 20795.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x238d430] width 1600 pitch 6400 (/4 1600)
>[ 20796.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20796.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20796.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20796.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20796.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x238d430]
>[ 20796.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x238d430] width 1600 pitch 6400 (/4 1600)
>[ 20796.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20796.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20796.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20796.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20796.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x238d430]
>[ 20796.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x238d430] width 1600 pitch 6400 (/4 1600)
>[ 20797.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592a80]
>[ 20797.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592a80] width 1600 pitch 6400 (/4 1600)
>[ 20797.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592bc0]
>[ 20797.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592bc0] width 1600 pitch 6400 (/4 1600)
>[ 20797.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x238d430]
>[ 20797.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x238d430] width 1600 pitch 6400 (/4 1600)
>[ 20797.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x238d430]
>[ 20797.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x238d430] width 1600 pitch 6400 (/4 1600)
>[ 20797.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2285400]
>[ 20797.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2285400] width 1600 pitch 6400 (/4 1600)
>[ 20797.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x238d430]
>[ 20797.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x238d430] width 1600 pitch 6400 (/4 1600)
>[ 20797.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2285400]
>[ 20797.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2285400] width 1600 pitch 6400 (/4 1600)
>[ 20797.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x238d430]
>[ 20797.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x238d430] width 1600 pitch 6400 (/4 1600)
>[ 20797.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x228be10]
>[ 20797.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x228be10] width 1600 pitch 6400 (/4 1600)
>[ 20797.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x238d430]
>[ 20797.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x238d430] width 1600 pitch 6400 (/4 1600)
>[ 20797.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x228be10]
>[ 20797.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x228be10] width 1600 pitch 6400 (/4 1600)
>[ 20798.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238560]
>[ 20798.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238560] width 1600 pitch 6400 (/4 1600)
>[ 20798.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2238560]
>[ 20798.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2238560] width 1600 pitch 6400 (/4 1600)
>[ 20798.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258ab90]
>[ 20798.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258ab90] width 1600 pitch 6400 (/4 1600)
>[ 21265.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21265.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21265.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21265.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21265.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21265.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21265.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd3f80]
>[ 21265.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd3f80] width 1600 pitch 6400 (/4 1600)
>[ 21265.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21265.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21265.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd3f80]
>[ 21265.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd3f80] width 1600 pitch 6400 (/4 1600)
>[ 21265.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21265.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21265.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd3f80]
>[ 21265.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd3f80] width 1600 pitch 6400 (/4 1600)
>[ 21265.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21265.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21265.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd3f80]
>[ 21265.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd3f80] width 1600 pitch 6400 (/4 1600)
>[ 21265.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21265.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21265.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd3f80]
>[ 21265.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd3f80] width 1600 pitch 6400 (/4 1600)
>[ 21267.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21267.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21267.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21267.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21267.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21267.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21267.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21267.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21267.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21267.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21267.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21267.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21267.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21267.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21267.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21267.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21268.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21268.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21268.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21268.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21268.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x215af80]
>[ 21268.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x215af80] width 1600 pitch 6400 (/4 1600)
>[ 21268.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21268.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21268.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21268.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21268.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x215af80]
>[ 21269.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x215af80] width 1600 pitch 6400 (/4 1600)
>[ 21269.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21269.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21269.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21269.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21269.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x215af80]
>[ 21269.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x215af80] width 1600 pitch 6400 (/4 1600)
>[ 21269.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21269.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21269.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21269.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21269.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22d3190]
>[ 21269.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22d3190] width 1600 pitch 6400 (/4 1600)
>[ 21269.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x215af80]
>[ 21269.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x215af80] width 1600 pitch 6400 (/4 1600)
>[ 21269.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21269.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21269.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b9fb0]
>[ 21270.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b9fb0] width 1600 pitch 6400 (/4 1600)
>[ 21270.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21270.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21270.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b9fb0]
>[ 21270.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b9fb0] width 1600 pitch 6400 (/4 1600)
>[ 21270.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21270.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21270.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e4950]
>[ 21270.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e4950] width 1600 pitch 6400 (/4 1600)
>[ 21270.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21270.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21270.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e4950]
>[ 21270.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e4950] width 1600 pitch 6400 (/4 1600)
>[ 21270.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8c70]
>[ 21270.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8c70] width 1600 pitch 6400 (/4 1600)
>[ 21288.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230b4b0]
>[ 21288.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230b4b0] width 1600 pitch 6400 (/4 1600)
>[ 21288.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aac80]
>[ 21288.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aac80] width 1600 pitch 6400 (/4 1600)
>[ 21288.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab520]
>[ 21288.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab520] width 1600 pitch 6400 (/4 1600)
>[ 21288.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22aac80]
>[ 21288.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22aac80] width 1600 pitch 6400 (/4 1600)
>[ 21288.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab520]
>[ 21288.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab520] width 1600 pitch 6400 (/4 1600)
>[ 21305.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250450]
>[ 21305.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250450] width 1600 pitch 6400 (/4 1600)
>[ 21305.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ca00]
>[ 21305.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ca00] width 1600 pitch 6400 (/4 1600)
>[ 21305.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250450]
>[ 21306.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250450] width 1600 pitch 6400 (/4 1600)
>[ 21306.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ca00]
>[ 21306.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ca00] width 1600 pitch 6400 (/4 1600)
>[ 21306.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250450]
>[ 21306.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250450] width 1600 pitch 6400 (/4 1600)
>[ 21306.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ca00]
>[ 21306.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ca00] width 1600 pitch 6400 (/4 1600)
>[ 21306.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250450]
>[ 21306.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250450] width 1600 pitch 6400 (/4 1600)
>[ 21306.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ca00]
>[ 21306.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ca00] width 1600 pitch 6400 (/4 1600)
>[ 21306.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250450]
>[ 21306.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250450] width 1600 pitch 6400 (/4 1600)
>[ 21306.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ca00]
>[ 21306.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ca00] width 1600 pitch 6400 (/4 1600)
>[ 21307.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250450]
>[ 21307.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250450] width 1600 pitch 6400 (/4 1600)
>[ 21307.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ca00]
>[ 21307.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ca00] width 1600 pitch 6400 (/4 1600)
>[ 21307.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2250450]
>[ 21307.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2250450] width 1600 pitch 6400 (/4 1600)
>[ 21307.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245f070]
>[ 21307.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245f070] width 1600 pitch 6400 (/4 1600)
>[ 21307.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245eff0]
>[ 21307.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245eff0] width 1600 pitch 6400 (/4 1600)
>[ 21307.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cefad0]
>[ 21308.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cefad0] width 1600 pitch 6400 (/4 1600)
>[ 21308.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cefdc0]
>[ 21308.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cefdc0] width 1600 pitch 6400 (/4 1600)
>[ 21308.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245eff0]
>[ 21308.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245eff0] width 1600 pitch 6400 (/4 1600)
>[ 21308.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cefa70]
>[ 21308.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cefa70] width 1600 pitch 6400 (/4 1600)
>[ 21308.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ec70]
>[ 21308.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ec70] width 1600 pitch 6400 (/4 1600)
>[ 21308.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7bd10]
>[ 21308.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7bd10] width 1600 pitch 6400 (/4 1600)
>[ 21308.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7c710]
>[ 21308.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7c710] width 1600 pitch 6400 (/4 1600)
>[ 21338.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e4d0]
>[ 21338.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e4d0] width 1600 pitch 6400 (/4 1600)
>[ 21338.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cefb50]
>[ 21338.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cefb50] width 1600 pitch 6400 (/4 1600)
>[ 21338.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e3a0]
>[ 21338.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e3a0] width 1600 pitch 6400 (/4 1600)
>[ 21338.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cefb50]
>[ 21338.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cefb50] width 1600 pitch 6400 (/4 1600)
>[ 21338.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a1d80]
>[ 21338.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a1d80] width 1600 pitch 6400 (/4 1600)
>[ 21338.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cefb50]
>[ 21338.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cefb50] width 1600 pitch 6400 (/4 1600)
>[ 21338.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e320]
>[ 21338.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e320] width 1600 pitch 6400 (/4 1600)
>[ 21339.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ec80]
>[ 21339.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ec80] width 1600 pitch 6400 (/4 1600)
>[ 21339.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cefb50]
>[ 21339.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cefb50] width 1600 pitch 6400 (/4 1600)
>[ 21339.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ec80]
>[ 21339.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ec80] width 1600 pitch 6400 (/4 1600)
>[ 21339.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e4b0]
>[ 21339.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e4b0] width 1600 pitch 6400 (/4 1600)
>[ 21339.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e4b0]
>[ 21339.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e4b0] width 1600 pitch 6400 (/4 1600)
>[ 21341.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e4d0]
>[ 21341.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e4d0] width 1600 pitch 6400 (/4 1600)
>[ 21342.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e320]
>[ 21342.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e320] width 1600 pitch 6400 (/4 1600)
>[ 21342.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cef1a0]
>[ 21342.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cef1a0] width 1600 pitch 6400 (/4 1600)
>[ 21342.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06b60]
>[ 21342.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06b60] width 1600 pitch 6400 (/4 1600)
>[ 21342.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06c90]
>[ 21342.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06c90] width 1600 pitch 6400 (/4 1600)
>[ 21342.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06b60]
>[ 21342.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06b60] width 1600 pitch 6400 (/4 1600)
>[ 21342.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7d850]
>[ 21342.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7d850] width 1600 pitch 6400 (/4 1600)
>[ 21342.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06bb0]
>[ 21342.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06bb0] width 1600 pitch 6400 (/4 1600)
>[ 21344.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d71df0]
>[ 21344.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d71df0] width 1600 pitch 6400 (/4 1600)
>[ 21344.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x230a940]
>[ 21344.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x230a940] width 1600 pitch 6400 (/4 1600)
>[ 21344.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cf60]
>[ 21344.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cf60] width 1600 pitch 6400 (/4 1600)
>[ 21344.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab3f0]
>[ 21344.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab3f0] width 1600 pitch 6400 (/4 1600)
>[ 21344.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cf60]
>[ 21344.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cf60] width 1600 pitch 6400 (/4 1600)
>[ 21344.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2299210]
>[ 21344.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2299210] width 1600 pitch 6400 (/4 1600)
>[ 21344.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248cf60]
>[ 21344.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248cf60] width 1600 pitch 6400 (/4 1600)
>[ 21344.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a9fe0]
>[ 21344.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a9fe0] width 1600 pitch 6400 (/4 1600)
>[ 21345.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d76170]
>[ 21345.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d76170] width 1600 pitch 6400 (/4 1600)
>[ 21345.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab3f0]
>[ 21345.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab3f0] width 1600 pitch 6400 (/4 1600)
>[ 21345.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7c690]
>[ 21345.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7c690] width 1600 pitch 6400 (/4 1600)
>[ 21345.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ab3f0]
>[ 21345.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ab3f0] width 1600 pitch 6400 (/4 1600)
>[ 21345.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cee900]
>[ 21345.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cee900] width 1600 pitch 6400 (/4 1600)
>[ 21345.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d786e0]
>[ 21345.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d786e0] width 1600 pitch 6400 (/4 1600)
>[ 21347.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ba030]
>[ 21347.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ba030] width 1600 pitch 6400 (/4 1600)
>[ 21347.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ede0]
>[ 21347.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ede0] width 1600 pitch 6400 (/4 1600)
>[ 21347.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c07d00]
>[ 21347.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c07d00] width 1600 pitch 6400 (/4 1600)
>[ 21347.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ede0]
>[ 21347.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ede0] width 1600 pitch 6400 (/4 1600)
>[ 21347.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c07d00]
>[ 21347.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c07d00] width 1600 pitch 6400 (/4 1600)
>[ 21347.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229ede0]
>[ 21347.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229ede0] width 1600 pitch 6400 (/4 1600)
>[ 21347.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c07d00]
>[ 21347.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c07d00] width 1600 pitch 6400 (/4 1600)
>[ 21347.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c07d60]
>[ 21347.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c07d60] width 1600 pitch 6400 (/4 1600)
>[ 21347.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3a610]
>[ 21347.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3a610] width 1600 pitch 6400 (/4 1600)
>[ 21347.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7e310]
>[ 21347.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7e310] width 1600 pitch 6400 (/4 1600)
>[ 21347.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b9fd0]
>[ 21347.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b9fd0] width 1600 pitch 6400 (/4 1600)
>[ 21348.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c09f50]
>[ 21348.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c09f50] width 1600 pitch 6400 (/4 1600)
>[ 21348.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7df60]
>[ 21348.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7df60] width 1600 pitch 6400 (/4 1600)
>[ 21348.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7e310]
>[ 21348.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7e310] width 1600 pitch 6400 (/4 1600)
>[ 21348.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7df60]
>[ 21348.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7df60] width 1600 pitch 6400 (/4 1600)
>[ 21348.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7e310]
>[ 21348.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7e310] width 1600 pitch 6400 (/4 1600)
>[ 21348.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7df60]
>[ 21348.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7df60] width 1600 pitch 6400 (/4 1600)
>[ 21348.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7df30]
>[ 21348.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7df30] width 1600 pitch 6400 (/4 1600)
>[ 21348.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7e310]
>[ 21348.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7e310] width 1600 pitch 6400 (/4 1600)
>[ 21348.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c07d70]
>[ 21348.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c07d70] width 1600 pitch 6400 (/4 1600)
>[ 21348.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c07d70]
>[ 21348.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c07d70] width 1600 pitch 6400 (/4 1600)
>[ 21388.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a2ea0]
>[ 21388.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a2ea0] width 1600 pitch 6400 (/4 1600)
>[ 21393.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c14bd0]
>[ 21393.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c14bd0] width 1600 pitch 6400 (/4 1600)
>[ 21405.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2298cb0]
>[ 21405.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2298cb0] width 1600 pitch 6400 (/4 1600)
>[ 21431.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3b1a0]
>[ 21431.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3b1a0] width 1600 pitch 6400 (/4 1600)
>[ 21948.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c18c80]
>[ 21948.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c18c80] width 1600 pitch 6400 (/4 1600)
>[ 22003.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a1a90]
>[ 22003.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a1a90] width 1600 pitch 6400 (/4 1600)
>[ 22003.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4ea60]
>[ 22003.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4ea60] width 1600 pitch 6400 (/4 1600)
>[ 22003.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a1a90]
>[ 22003.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a1a90] width 1600 pitch 6400 (/4 1600)
>[ 22003.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214f3c0]
>[ 22003.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214f3c0] width 1600 pitch 6400 (/4 1600)
>[ 22013.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd05f0]
>[ 22013.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd05f0] width 1600 pitch 6400 (/4 1600)
>[ 22034.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c23d10]
>[ 22034.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c23d10] width 1600 pitch 6400 (/4 1600)
>[ 22036.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df0190]
>[ 22036.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df0190] width 1600 pitch 6400 (/4 1600)
>[ 22036.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df0190]
>[ 22036.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df0190] width 1600 pitch 6400 (/4 1600)
>[ 22056.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df0190]
>[ 22056.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df0190] width 1600 pitch 6400 (/4 1600)
>[ 22094.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22094.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22099.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c05d80]
>[ 22099.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c05d80] width 1600 pitch 6400 (/4 1600)
>[ 22099.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22100.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22100.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c212c0]
>[ 22100.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c212c0] width 1600 pitch 6400 (/4 1600)
>[ 22100.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22100.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22100.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214f5b0]
>[ 22100.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214f5b0] width 1600 pitch 6400 (/4 1600)
>[ 22100.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06be0]
>[ 22100.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06be0] width 1600 pitch 6400 (/4 1600)
>[ 22100.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2299450]
>[ 22100.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2299450] width 1600 pitch 6400 (/4 1600)
>[ 22100.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2299450]
>[ 22100.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2299450] width 1600 pitch 6400 (/4 1600)
>[ 22100.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214f5b0]
>[ 22100.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214f5b0] width 1600 pitch 6400 (/4 1600)
>[ 22100.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2299450]
>[ 22100.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2299450] width 1600 pitch 6400 (/4 1600)
>[ 22101.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2299450]
>[ 22101.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2299450] width 1600 pitch 6400 (/4 1600)
>[ 22101.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c05d80]
>[ 22101.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c05d80] width 1600 pitch 6400 (/4 1600)
>[ 22101.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06be0]
>[ 22101.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06be0] width 1600 pitch 6400 (/4 1600)
>[ 22102.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06be0]
>[ 22102.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06be0] width 1600 pitch 6400 (/4 1600)
>[ 22102.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c05d80]
>[ 22102.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c05d80] width 1600 pitch 6400 (/4 1600)
>[ 22103.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22103.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22103.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06be0]
>[ 22103.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06be0] width 1600 pitch 6400 (/4 1600)
>[ 22103.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22103.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22103.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c05d80]
>[ 22103.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c05d80] width 1600 pitch 6400 (/4 1600)
>[ 22103.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22103.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22103.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2299450]
>[ 22103.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2299450] width 1600 pitch 6400 (/4 1600)
>[ 22103.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214f5b0]
>[ 22103.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214f5b0] width 1600 pitch 6400 (/4 1600)
>[ 22103.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c06be0]
>[ 22103.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c06be0] width 1600 pitch 6400 (/4 1600)
>[ 22103.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x214f5b0]
>[ 22103.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x214f5b0] width 1600 pitch 6400 (/4 1600)
>[ 22106.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd9b10]
>[ 22106.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd9b10] width 1600 pitch 6400 (/4 1600)
>[ 22108.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e03410]
>[ 22108.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e03410] width 1600 pitch 6400 (/4 1600)
>[ 22108.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e84810]
>[ 22108.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e84810] width 1600 pitch 6400 (/4 1600)
>[ 22152.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dfd000]
>[ 22152.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dfd000] width 1600 pitch 6400 (/4 1600)
>[ 22152.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e84690]
>[ 22152.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e84690] width 1600 pitch 6400 (/4 1600)
>[ 22152.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5a860]
>[ 22152.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5a860] width 1600 pitch 6400 (/4 1600)
>[ 22152.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e84690]
>[ 22152.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e84690] width 1600 pitch 6400 (/4 1600)
>[ 22152.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5a860]
>[ 22152.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5a860] width 1600 pitch 6400 (/4 1600)
>[ 22153.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e84690]
>[ 22153.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e84690] width 1600 pitch 6400 (/4 1600)
>[ 22153.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e8a720]
>[ 22153.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e8a720] width 1600 pitch 6400 (/4 1600)
>[ 22153.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e59c90]
>[ 22153.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e59c90] width 1600 pitch 6400 (/4 1600)
>[ 22153.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5a860]
>[ 22153.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5a860] width 1600 pitch 6400 (/4 1600)
>[ 22153.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e59c90]
>[ 22153.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e59c90] width 1600 pitch 6400 (/4 1600)
>[ 22153.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5a860]
>[ 22153.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5a860] width 1600 pitch 6400 (/4 1600)
>[ 22153.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e59c90]
>[ 22153.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e59c90] width 1600 pitch 6400 (/4 1600)
>[ 22177.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea6db0]
>[ 22177.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea6db0] width 1600 pitch 6400 (/4 1600)
>[ 22177.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7dae0]
>[ 22178.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7dae0] width 1600 pitch 6400 (/4 1600)
>[ 22192.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22430]
>[ 22192.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22430] width 1600 pitch 6400 (/4 1600)
>[ 22192.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c224a0]
>[ 22192.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c224a0] width 1600 pitch 6400 (/4 1600)
>[ 22193.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c224a0]
>[ 22193.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c224a0] width 1600 pitch 6400 (/4 1600)
>[ 22193.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eaa1f0]
>[ 22193.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eaa1f0] width 1600 pitch 6400 (/4 1600)
>[ 22193.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e80e50]
>[ 22193.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e80e50] width 1600 pitch 6400 (/4 1600)
>[ 22780.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 22780.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 22780.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0db90]
>[ 22780.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0db90] width 1600 pitch 6400 (/4 1600)
>[ 22780.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88b10]
>[ 22780.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88b10] width 1600 pitch 6400 (/4 1600)
>[ 22780.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9e8e0]
>[ 22780.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9e8e0] width 1600 pitch 6400 (/4 1600)
>[ 22780.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0db90]
>[ 22780.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0db90] width 1600 pitch 6400 (/4 1600)
>[ 22780.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9e8e0]
>[ 22780.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9e8e0] width 1600 pitch 6400 (/4 1600)
>[ 22780.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88b10]
>[ 22780.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88b10] width 1600 pitch 6400 (/4 1600)
>[ 22781.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0db90]
>[ 22781.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0db90] width 1600 pitch 6400 (/4 1600)
>[ 22781.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dfad60]
>[ 22781.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dfad60] width 1600 pitch 6400 (/4 1600)
>[ 22781.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88b10]
>[ 22781.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88b10] width 1600 pitch 6400 (/4 1600)
>[ 22781.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 22781.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 22781.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 22781.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 22782.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88b10]
>[ 22782.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88b10] width 1600 pitch 6400 (/4 1600)
>[ 22782.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22782.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22782.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88b10]
>[ 22782.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88b10] width 1600 pitch 6400 (/4 1600)
>[ 22782.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22782.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22782.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88b10]
>[ 22782.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88b10] width 1600 pitch 6400 (/4 1600)
>[ 22782.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 22782.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 22786.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229d880]
>[ 22786.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229d880] width 1600 pitch 6400 (/4 1600)
>[ 23800.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229d880]
>[ 23800.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229d880] width 1600 pitch 6400 (/4 1600)
>[ 23814.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23814.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23817.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 23817.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 23817.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23817.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23817.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23817.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23817.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f19310]
>[ 23817.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f19310] width 1600 pitch 6400 (/4 1600)
>[ 23817.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23817.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23817.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f19310]
>[ 23817.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f19310] width 1600 pitch 6400 (/4 1600)
>[ 23817.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23817.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23817.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebb260]
>[ 23817.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebb260] width 1600 pitch 6400 (/4 1600)
>[ 23817.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eeb340]
>[ 23817.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eeb340] width 1600 pitch 6400 (/4 1600)
>[ 23817.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebb260]
>[ 23817.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebb260] width 1600 pitch 6400 (/4 1600)
>[ 23817.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eeb340]
>[ 23817.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eeb340] width 1600 pitch 6400 (/4 1600)
>[ 23817.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebb260]
>[ 23817.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebb260] width 1600 pitch 6400 (/4 1600)
>[ 23817.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eeb340]
>[ 23817.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eeb340] width 1600 pitch 6400 (/4 1600)
>[ 23817.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229cdb0]
>[ 23817.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229cdb0] width 1600 pitch 6400 (/4 1600)
>[ 23817.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23817.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23824.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23824.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23824.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23824.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23824.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23824.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23824.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23824.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23824.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23824.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23824.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23824.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23824.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23824.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23824.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23824.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23824.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23824.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23824.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23824.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23824.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23824.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23824.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23824.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23824.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23824.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23824.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23824.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23824.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 23824.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 23824.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ee1290]
>[ 23824.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ee1290] width 1600 pitch 6400 (/4 1600)
>[ 23825.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2295eb0]
>[ 23825.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2295eb0] width 1600 pitch 6400 (/4 1600)
>[ 23825.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2295dc0]
>[ 23825.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2295dc0] width 1600 pitch 6400 (/4 1600)
>[ 23826.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2295eb0]
>[ 23826.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2295eb0] width 1600 pitch 6400 (/4 1600)
>[ 23826.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22d80]
>[ 23826.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22d80] width 1600 pitch 6400 (/4 1600)
>[ 23842.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef7160]
>[ 23842.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef7160] width 1600 pitch 6400 (/4 1600)
>[ 24118.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3a40]
>[ 24118.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3a40] width 1600 pitch 6400 (/4 1600)
>[ 24119.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3350]
>[ 24119.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3350] width 1600 pitch 6400 (/4 1600)
>[ 24119.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3350]
>[ 24119.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3350] width 1600 pitch 6400 (/4 1600)
>[ 24119.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 24119.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 24119.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3450]
>[ 24119.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3450] width 1600 pitch 6400 (/4 1600)
>[ 24119.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3450]
>[ 24119.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3450] width 1600 pitch 6400 (/4 1600)
>[ 24119.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd2e40]
>[ 24119.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd2e40] width 1600 pitch 6400 (/4 1600)
>[ 24120.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3a40]
>[ 24120.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3a40] width 1600 pitch 6400 (/4 1600)
>[ 24120.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3450]
>[ 24120.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3450] width 1600 pitch 6400 (/4 1600)
>[ 24120.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3a40]
>[ 24120.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3a40] width 1600 pitch 6400 (/4 1600)
>[ 24120.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3350]
>[ 24120.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3350] width 1600 pitch 6400 (/4 1600)
>[ 24120.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3450]
>[ 24120.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3450] width 1600 pitch 6400 (/4 1600)
>[ 24121.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 24121.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 24121.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3450]
>[ 24121.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3450] width 1600 pitch 6400 (/4 1600)
>[ 24121.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 24121.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 24122.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3350]
>[ 24122.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3350] width 1600 pitch 6400 (/4 1600)
>[ 24122.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3350]
>[ 24122.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3350] width 1600 pitch 6400 (/4 1600)
>[ 24122.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be8840]
>[ 24122.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be8840] width 1600 pitch 6400 (/4 1600)
>[ 24122.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3a40]
>[ 24122.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3a40] width 1600 pitch 6400 (/4 1600)
>[ 24122.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd2e40]
>[ 24122.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd2e40] width 1600 pitch 6400 (/4 1600)
>[ 24122.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 24123.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 24123.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3450]
>[ 24123.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3450] width 1600 pitch 6400 (/4 1600)
>[ 24123.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3450]
>[ 24123.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3450] width 1600 pitch 6400 (/4 1600)
>[ 24123.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef9360]
>[ 24123.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef9360] width 1600 pitch 6400 (/4 1600)
>[ 24123.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3dff0]
>[ 24123.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3dff0] width 1600 pitch 6400 (/4 1600)
>[ 24123.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd2e40]
>[ 24123.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd2e40] width 1600 pitch 6400 (/4 1600)
>[ 24123.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88210]
>[ 24123.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88210] width 1600 pitch 6400 (/4 1600)
>[ 24123.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 24124.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 24124.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef9360]
>[ 24124.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef9360] width 1600 pitch 6400 (/4 1600)
>[ 24124.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef9360]
>[ 24124.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef9360] width 1600 pitch 6400 (/4 1600)
>[ 24124.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3350]
>[ 24124.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3350] width 1600 pitch 6400 (/4 1600)
>[ 24124.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6530]
>[ 24124.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6530] width 1600 pitch 6400 (/4 1600)
>[ 24124.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd2e40]
>[ 24124.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd2e40] width 1600 pitch 6400 (/4 1600)
>[ 24124.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 24124.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 24124.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6530]
>[ 24124.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6530] width 1600 pitch 6400 (/4 1600)
>[ 24124.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3350]
>[ 24124.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3350] width 1600 pitch 6400 (/4 1600)
>[ 24125.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd2e40]
>[ 24125.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd2e40] width 1600 pitch 6400 (/4 1600)
>[ 24125.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6530]
>[ 24125.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6530] width 1600 pitch 6400 (/4 1600)
>[ 24125.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 24125.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 24125.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88210]
>[ 24125.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88210] width 1600 pitch 6400 (/4 1600)
>[ 24125.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6530]
>[ 24125.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6530] width 1600 pitch 6400 (/4 1600)
>[ 24126.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 24126.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 24126.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6530]
>[ 24126.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6530] width 1600 pitch 6400 (/4 1600)
>[ 24127.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c220]
>[ 24127.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c220] width 1600 pitch 6400 (/4 1600)
>[ 24127.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88210]
>[ 24127.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88210] width 1600 pitch 6400 (/4 1600)
>[ 24127.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6530]
>[ 24127.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6530] width 1600 pitch 6400 (/4 1600)
>[ 24127.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88210]
>[ 24127.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88210] width 1600 pitch 6400 (/4 1600)
>[ 24127.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3dff0]
>[ 24127.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3dff0] width 1600 pitch 6400 (/4 1600)
>[ 24127.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e88210]
>[ 24127.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e88210] width 1600 pitch 6400 (/4 1600)
>[ 24127.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef3350]
>[ 24127.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef3350] width 1600 pitch 6400 (/4 1600)
>[ 24127.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6000]
>[ 24127.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6000] width 1600 pitch 6400 (/4 1600)
>[ 24130.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4eae0]
>[ 24130.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4eae0] width 1600 pitch 6400 (/4 1600)
>[ 24130.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7df50]
>[ 24130.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7df50] width 1600 pitch 6400 (/4 1600)
>[ 24130.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef38a0]
>[ 24130.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef38a0] width 1600 pitch 6400 (/4 1600)
>[ 24130.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e66620]
>[ 24130.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e66620] width 1600 pitch 6400 (/4 1600)
>[ 24130.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd64f0]
>[ 24130.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd64f0] width 1600 pitch 6400 (/4 1600)
>[ 24130.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4eae0]
>[ 24130.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4eae0] width 1600 pitch 6400 (/4 1600)
>[ 24130.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7df50]
>[ 24131.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7df50] width 1600 pitch 6400 (/4 1600)
>[ 24131.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd64f0]
>[ 24131.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd64f0] width 1600 pitch 6400 (/4 1600)
>[ 24131.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef38a0]
>[ 24131.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef38a0] width 1600 pitch 6400 (/4 1600)
>[ 24131.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd64f0]
>[ 24131.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd64f0] width 1600 pitch 6400 (/4 1600)
>[ 24131.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef38a0]
>[ 24131.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef38a0] width 1600 pitch 6400 (/4 1600)
>[ 24131.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd2e40]
>[ 24131.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd2e40] width 1600 pitch 6400 (/4 1600)
>[ 24131.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7df50]
>[ 24131.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7df50] width 1600 pitch 6400 (/4 1600)
>[ 24131.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3dff0]
>[ 24131.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3dff0] width 1600 pitch 6400 (/4 1600)
>[ 24132.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd64f0]
>[ 24132.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd64f0] width 1600 pitch 6400 (/4 1600)
>[ 24132.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4eae0]
>[ 24132.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4eae0] width 1600 pitch 6400 (/4 1600)
>[ 24132.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd64f0]
>[ 24132.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd64f0] width 1600 pitch 6400 (/4 1600)
>[ 24132.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4eae0]
>[ 24132.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4eae0] width 1600 pitch 6400 (/4 1600)
>[ 24133.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e66620]
>[ 24133.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e66620] width 1600 pitch 6400 (/4 1600)
>[ 24133.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4eae0]
>[ 24133.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4eae0] width 1600 pitch 6400 (/4 1600)
>[ 24133.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e66620]
>[ 24133.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e66620] width 1600 pitch 6400 (/4 1600)
>[ 24133.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4eae0]
>[ 24133.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4eae0] width 1600 pitch 6400 (/4 1600)
>[ 24133.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e66620]
>[ 24133.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e66620] width 1600 pitch 6400 (/4 1600)
>[ 24134.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4eae0]
>[ 24134.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4eae0] width 1600 pitch 6400 (/4 1600)
>[ 24134.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e66620]
>[ 24134.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e66620] width 1600 pitch 6400 (/4 1600)
>[ 24134.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd2e40]
>[ 24134.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd2e40] width 1600 pitch 6400 (/4 1600)
>[ 24137.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23ba7a0]
>[ 24137.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23ba7a0] width 1600 pitch 6400 (/4 1600)
>[ 24187.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2377710]
>[ 24187.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2377710] width 1600 pitch 6400 (/4 1600)
>[ 24350.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22320b0]
>[ 24350.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22320b0] width 1600 pitch 6400 (/4 1600)
>[ 24351.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d73d80]
>[ 24351.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d73d80] width 1600 pitch 6400 (/4 1600)
>[ 24352.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d70950]
>[ 24352.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d70950] width 1600 pitch 6400 (/4 1600)
>[ 24352.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244f4d0]
>[ 24352.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244f4d0] width 1600 pitch 6400 (/4 1600)
>[ 24352.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef1fb0]
>[ 24352.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef1fb0] width 1600 pitch 6400 (/4 1600)
>[ 24352.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480030]
>[ 24352.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480030] width 1600 pitch 6400 (/4 1600)
>[ 24352.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef1fb0]
>[ 24352.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef1fb0] width 1600 pitch 6400 (/4 1600)
>[ 24352.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480030]
>[ 24352.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480030] width 1600 pitch 6400 (/4 1600)
>[ 24352.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef1fb0]
>[ 24352.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef1fb0] width 1600 pitch 6400 (/4 1600)
>[ 24352.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480030]
>[ 24352.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480030] width 1600 pitch 6400 (/4 1600)
>[ 24353.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef1fb0]
>[ 24353.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef1fb0] width 1600 pitch 6400 (/4 1600)
>[ 24353.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de7270]
>[ 24353.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de7270] width 1600 pitch 6400 (/4 1600)
>[ 24353.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef1fb0]
>[ 24353.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef1fb0] width 1600 pitch 6400 (/4 1600)
>[ 24353.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de7270]
>[ 24353.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de7270] width 1600 pitch 6400 (/4 1600)
>[ 24353.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef1fb0]
>[ 24353.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef1fb0] width 1600 pitch 6400 (/4 1600)
>[ 24353.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de7270]
>[ 24353.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de7270] width 1600 pitch 6400 (/4 1600)
>[ 24353.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244f4d0]
>[ 24354.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244f4d0] width 1600 pitch 6400 (/4 1600)
>[ 24354.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de7270]
>[ 24354.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de7270] width 1600 pitch 6400 (/4 1600)
>[ 24354.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efa2e0]
>[ 24354.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efa2e0] width 1600 pitch 6400 (/4 1600)
>[ 24365.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c4dc30]
>[ 24365.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c4dc30] width 1600 pitch 6400 (/4 1600)
>[ 24366.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24366.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24366.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c19280]
>[ 24366.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c19280] width 1600 pitch 6400 (/4 1600)
>[ 24366.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24366.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24366.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c19280]
>[ 24366.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c19280] width 1600 pitch 6400 (/4 1600)
>[ 24366.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24366.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24366.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c19280]
>[ 24366.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c19280] width 1600 pitch 6400 (/4 1600)
>[ 24366.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24366.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24366.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c19280]
>[ 24366.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c19280] width 1600 pitch 6400 (/4 1600)
>[ 24366.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24367.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24367.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ea00d0]
>[ 24367.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ea00d0] width 1600 pitch 6400 (/4 1600)
>[ 24367.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24367.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24367.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218fb30]
>[ 24367.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218fb30] width 1600 pitch 6400 (/4 1600)
>[ 24367.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be9b90]
>[ 24367.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be9b90] width 1600 pitch 6400 (/4 1600)
>[ 24367.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x218fb30]
>[ 24367.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x218fb30] width 1600 pitch 6400 (/4 1600)
>[ 24367.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be9b90]
>[ 24367.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be9b90] width 1600 pitch 6400 (/4 1600)
>[ 24367.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24367.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24367.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c19280]
>[ 24367.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c19280] width 1600 pitch 6400 (/4 1600)
>[ 24367.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c19280]
>[ 24367.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c19280] width 1600 pitch 6400 (/4 1600)
>[ 24379.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24379.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24379.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a4a50]
>[ 24379.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a4a50] width 1600 pitch 6400 (/4 1600)
>[ 24379.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24379.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24380.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24380.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24380.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d73c60]
>[ 24380.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d73c60] width 1600 pitch 6400 (/4 1600)
>[ 24380.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24380.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24380.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d73c60]
>[ 24380.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d73c60] width 1600 pitch 6400 (/4 1600)
>[ 24380.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a4a50]
>[ 24380.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a4a50] width 1600 pitch 6400 (/4 1600)
>[ 24381.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24381.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24381.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24381.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24381.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d73c60]
>[ 24381.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d73c60] width 1600 pitch 6400 (/4 1600)
>[ 24381.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de59a0]
>[ 24381.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de59a0] width 1600 pitch 6400 (/4 1600)
>[ 24381.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d73c60]
>[ 24381.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d73c60] width 1600 pitch 6400 (/4 1600)
>[ 24487.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2151020]
>[ 24487.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2151020] width 1600 pitch 6400 (/4 1600)
>[ 24487.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2151020]
>[ 24487.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2151020] width 1600 pitch 6400 (/4 1600)
>[ 24488.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6e300]
>[ 24488.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6e300] width 1600 pitch 6400 (/4 1600)
>[ 24488.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b6b0]
>[ 24488.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b6b0] width 1600 pitch 6400 (/4 1600)
>[ 24488.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6e300]
>[ 24488.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6e300] width 1600 pitch 6400 (/4 1600)
>[ 24488.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b6b0]
>[ 24488.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b6b0] width 1600 pitch 6400 (/4 1600)
>[ 24488.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6e300]
>[ 24488.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6e300] width 1600 pitch 6400 (/4 1600)
>[ 24488.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b6b0]
>[ 24488.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b6b0] width 1600 pitch 6400 (/4 1600)
>[ 24488.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6e300]
>[ 24488.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6e300] width 1600 pitch 6400 (/4 1600)
>[ 24489.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b6b0]
>[ 24489.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b6b0] width 1600 pitch 6400 (/4 1600)
>[ 24489.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24489.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24489.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2151020]
>[ 24489.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2151020] width 1600 pitch 6400 (/4 1600)
>[ 24489.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2151020]
>[ 24489.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2151020] width 1600 pitch 6400 (/4 1600)
>[ 24489.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6e300]
>[ 24489.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6e300] width 1600 pitch 6400 (/4 1600)
>[ 24490.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78680]
>[ 24490.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78680] width 1600 pitch 6400 (/4 1600)
>[ 24490.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6e300]
>[ 24490.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6e300] width 1600 pitch 6400 (/4 1600)
>[ 24490.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d78680]
>[ 24490.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d78680] width 1600 pitch 6400 (/4 1600)
>[ 24490.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6e300]
>[ 24490.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6e300] width 1600 pitch 6400 (/4 1600)
>[ 24490.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24490.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24513.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89a80]
>[ 24513.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89a80] width 1600 pitch 6400 (/4 1600)
>[ 24513.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7b930]
>[ 24513.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7b930] width 1600 pitch 6400 (/4 1600)
>[ 24513.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89a80]
>[ 24513.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89a80] width 1600 pitch 6400 (/4 1600)
>[ 24513.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7b930]
>[ 24514.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7b930] width 1600 pitch 6400 (/4 1600)
>[ 24514.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89a80]
>[ 24514.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89a80] width 1600 pitch 6400 (/4 1600)
>[ 24514.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d7b930]
>[ 24514.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d7b930] width 1600 pitch 6400 (/4 1600)
>[ 24514.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89a80]
>[ 24514.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89a80] width 1600 pitch 6400 (/4 1600)
>[ 24514.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6af10]
>[ 24514.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6af10] width 1600 pitch 6400 (/4 1600)
>[ 24514.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89a80]
>[ 24514.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89a80] width 1600 pitch 6400 (/4 1600)
>[ 24514.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6af10]
>[ 24514.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6af10] width 1600 pitch 6400 (/4 1600)
>[ 24514.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2150780]
>[ 24514.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2150780] width 1600 pitch 6400 (/4 1600)
>[ 24515.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2282f30]
>[ 24515.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2282f30] width 1600 pitch 6400 (/4 1600)
>[ 24515.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89a80]
>[ 24515.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89a80] width 1600 pitch 6400 (/4 1600)
>[ 24515.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2282f30]
>[ 24515.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2282f30] width 1600 pitch 6400 (/4 1600)
>[ 24515.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89a80]
>[ 24515.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89a80] width 1600 pitch 6400 (/4 1600)
>[ 24515.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2282f30]
>[ 24515.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2282f30] width 1600 pitch 6400 (/4 1600)
>[ 24515.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89a80]
>[ 24515.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89a80] width 1600 pitch 6400 (/4 1600)
>[ 24632.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24779c0]
>[ 24632.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24779c0] width 1600 pitch 6400 (/4 1600)
>[ 24632.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcfbc0]
>[ 24632.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcfbc0] width 1600 pitch 6400 (/4 1600)
>[ 24669.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4dd20]
>[ 24669.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4dd20] width 1600 pitch 6400 (/4 1600)
>[ 24669.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x249e280]
>[ 24669.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x249e280] width 1600 pitch 6400 (/4 1600)
>[ 24669.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4dd20]
>[ 24669.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4dd20] width 1600 pitch 6400 (/4 1600)
>[ 24669.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x249e280]
>[ 24669.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x249e280] width 1600 pitch 6400 (/4 1600)
>[ 24669.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23bf280]
>[ 24669.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23bf280] width 1600 pitch 6400 (/4 1600)
>[ 24669.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c216a0]
>[ 24669.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c216a0] width 1600 pitch 6400 (/4 1600)
>[ 24669.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23bf280]
>[ 24669.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23bf280] width 1600 pitch 6400 (/4 1600)
>[ 24669.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c216a0]
>[ 24669.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c216a0] width 1600 pitch 6400 (/4 1600)
>[ 24670.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23bf280]
>[ 24670.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23bf280] width 1600 pitch 6400 (/4 1600)
>[ 24670.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c216a0]
>[ 24670.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c216a0] width 1600 pitch 6400 (/4 1600)
>[ 24670.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efb340]
>[ 24670.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efb340] width 1600 pitch 6400 (/4 1600)
>[ 24670.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efb340]
>[ 24670.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efb340] width 1600 pitch 6400 (/4 1600)
>[ 24670.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efb340]
>[ 24670.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efb340] width 1600 pitch 6400 (/4 1600)
>[ 24670.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f181d0]
>[ 24670.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f181d0] width 1600 pitch 6400 (/4 1600)
>[ 24670.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efb340]
>[ 24670.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efb340] width 1600 pitch 6400 (/4 1600)
>[ 24671.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f181d0]
>[ 24671.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f181d0] width 1600 pitch 6400 (/4 1600)
>[ 24671.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bede60]
>[ 24671.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bede60] width 1600 pitch 6400 (/4 1600)
>[ 24671.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1b470]
>[ 24671.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1b470] width 1600 pitch 6400 (/4 1600)
>[ 24671.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2150780]
>[ 24671.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2150780] width 1600 pitch 6400 (/4 1600)
>[ 24671.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efb340]
>[ 24671.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efb340] width 1600 pitch 6400 (/4 1600)
>[ 24671.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2150780]
>[ 24671.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2150780] width 1600 pitch 6400 (/4 1600)
>[ 24671.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efb340]
>[ 24671.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efb340] width 1600 pitch 6400 (/4 1600)
>[ 24671.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2150780]
>[ 24671.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2150780] width 1600 pitch 6400 (/4 1600)
>[ 24671.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efb340]
>[ 24672.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efb340] width 1600 pitch 6400 (/4 1600)
>[ 24672.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2150780]
>[ 24672.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2150780] width 1600 pitch 6400 (/4 1600)
>[ 24672.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c216a0]
>[ 24672.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c216a0] width 1600 pitch 6400 (/4 1600)
>[ 24672.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f181d0]
>[ 24672.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f181d0] width 1600 pitch 6400 (/4 1600)
>[ 24672.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c216a0]
>[ 24672.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c216a0] width 1600 pitch 6400 (/4 1600)
>[ 24672.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244a760]
>[ 24672.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244a760] width 1600 pitch 6400 (/4 1600)
>[ 24672.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1b470]
>[ 24672.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1b470] width 1600 pitch 6400 (/4 1600)
>[ 24672.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244a760]
>[ 24672.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244a760] width 1600 pitch 6400 (/4 1600)
>[ 24672.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1b470]
>[ 24672.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1b470] width 1600 pitch 6400 (/4 1600)
>[ 24672.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244a760]
>[ 24672.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244a760] width 1600 pitch 6400 (/4 1600)
>[ 24672.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c1b470]
>[ 24672.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c1b470] width 1600 pitch 6400 (/4 1600)
>[ 24676.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebc660]
>[ 24676.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebc660] width 1600 pitch 6400 (/4 1600)
>[ 24685.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f500]
>[ 24685.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f500] width 1600 pitch 6400 (/4 1600)
>[ 24705.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24705.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24705.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 24705.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 24705.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24705.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24705.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 24705.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 24705.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24705.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24705.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24705.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24705.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24705.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24705.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24705.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24706.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24706.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24706.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24706.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24706.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24706.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24706.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24706.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24706.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24706.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24706.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24707.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24707.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24707.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24707.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24707.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24707.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6dd0]
>[ 24707.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6dd0] width 1600 pitch 6400 (/4 1600)
>[ 24707.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x235a950]
>[ 24707.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x235a950] width 1600 pitch 6400 (/4 1600)
>[ 24707.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24707.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24707.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6dd0]
>[ 24707.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6dd0] width 1600 pitch 6400 (/4 1600)
>[ 24778.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6af10]
>[ 24778.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6af10] width 1600 pitch 6400 (/4 1600)
>[ 24779.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef51b0]
>[ 24779.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef51b0] width 1600 pitch 6400 (/4 1600)
>[ 24779.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c10a80]
>[ 24779.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c10a80] width 1600 pitch 6400 (/4 1600)
>[ 24779.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24779.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24779.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c10a80]
>[ 24779.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c10a80] width 1600 pitch 6400 (/4 1600)
>[ 24779.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24779.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24779.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24779.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24779.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6dd0]
>[ 24779.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6dd0] width 1600 pitch 6400 (/4 1600)
>[ 24779.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24779.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24779.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef6dd0]
>[ 24780.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef6dd0] width 1600 pitch 6400 (/4 1600)
>[ 24780.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24780.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24780.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef51b0]
>[ 24780.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef51b0] width 1600 pitch 6400 (/4 1600)
>[ 24780.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b820]
>[ 24780.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b820] width 1600 pitch 6400 (/4 1600)
>[ 24780.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255f380]
>[ 24780.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255f380] width 1600 pitch 6400 (/4 1600)
>[ 24780.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21487a0]
>[ 24780.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21487a0] width 1600 pitch 6400 (/4 1600)
>[ 24780.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255f380]
>[ 24780.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255f380] width 1600 pitch 6400 (/4 1600)
>[ 24780.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c48fe0]
>[ 24780.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c48fe0] width 1600 pitch 6400 (/4 1600)
>[ 24895.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c62c10]
>[ 24895.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c62c10] width 1600 pitch 6400 (/4 1600)
>[ 24895.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258700]
>[ 24895.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258700] width 1600 pitch 6400 (/4 1600)
>[ 24895.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258700]
>[ 24895.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258700] width 1600 pitch 6400 (/4 1600)
>[ 24895.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229fa30]
>[ 24895.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229fa30] width 1600 pitch 6400 (/4 1600)
>[ 24895.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258700]
>[ 24895.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258700] width 1600 pitch 6400 (/4 1600)
>[ 24896.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c62c10]
>[ 24896.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c62c10] width 1600 pitch 6400 (/4 1600)
>[ 24896.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a1e50]
>[ 24896.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a1e50] width 1600 pitch 6400 (/4 1600)
>[ 24896.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258700]
>[ 24896.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258700] width 1600 pitch 6400 (/4 1600)
>[ 24896.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a1e50]
>[ 24896.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a1e50] width 1600 pitch 6400 (/4 1600)
>[ 24897.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258700]
>[ 24897.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258700] width 1600 pitch 6400 (/4 1600)
>[ 24897.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a1e50]
>[ 24897.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a1e50] width 1600 pitch 6400 (/4 1600)
>[ 24898.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229fa30]
>[ 24898.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229fa30] width 1600 pitch 6400 (/4 1600)
>[ 24898.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c62c10]
>[ 24898.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c62c10] width 1600 pitch 6400 (/4 1600)
>[ 24898.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229fa30]
>[ 24898.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229fa30] width 1600 pitch 6400 (/4 1600)
>[ 24898.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c62c10]
>[ 24898.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c62c10] width 1600 pitch 6400 (/4 1600)
>[ 24898.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229fa30]
>[ 24898.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229fa30] width 1600 pitch 6400 (/4 1600)
>[ 24898.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c62c10]
>[ 24898.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c62c10] width 1600 pitch 6400 (/4 1600)
>[ 24898.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229fa30]
>[ 24898.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229fa30] width 1600 pitch 6400 (/4 1600)
>[ 24898.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2258700]
>[ 24898.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2258700] width 1600 pitch 6400 (/4 1600)
>[ 24902.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e69170]
>[ 24902.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e69170] width 1600 pitch 6400 (/4 1600)
>[ 24976.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4eae0]
>[ 24976.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4eae0] width 1600 pitch 6400 (/4 1600)
>[ 25008.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2177b10]
>[ 25008.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2177b10] width 1600 pitch 6400 (/4 1600)
>[ 25009.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eabbd0]
>[ 25010.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eabbd0] width 1600 pitch 6400 (/4 1600)
>[ 25023.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226a0d0]
>[ 25023.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226a0d0] width 1600 pitch 6400 (/4 1600)
>[ 25522.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c167b0]
>[ 25522.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c167b0] width 1600 pitch 6400 (/4 1600)
>[ 25557.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d75ce0]
>[ 25557.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d75ce0] width 1600 pitch 6400 (/4 1600)
>[ 26151.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244c720]
>[ 26151.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244c720] width 1600 pitch 6400 (/4 1600)
>[ 26155.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x249b580]
>[ 26155.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x249b580] width 1600 pitch 6400 (/4 1600)
>[ 26193.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2305690]
>[ 26193.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2305690] width 1600 pitch 6400 (/4 1600)
>[ 26199.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d58b30]
>[ 26199.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d58b30] width 1600 pitch 6400 (/4 1600)
>[ 26201.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d58b30]
>[ 26201.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d58b30] width 1600 pitch 6400 (/4 1600)
>[ 26201.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d59d80]
>[ 26201.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d59d80] width 1600 pitch 6400 (/4 1600)
>[ 26201.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d58b30]
>[ 26201.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d58b30] width 1600 pitch 6400 (/4 1600)
>[ 26201.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d59d80]
>[ 26201.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d59d80] width 1600 pitch 6400 (/4 1600)
>[ 26356.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc1e70]
>[ 26356.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc1e70] width 1600 pitch 6400 (/4 1600)
>[ 26811.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e94c70]
>[ 26811.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e94c70] width 1600 pitch 6400 (/4 1600)
>[ 26813.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2262160]
>[ 26813.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2262160] width 1600 pitch 6400 (/4 1600)
>[ 26867.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8950]
>[ 26867.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8950] width 1600 pitch 6400 (/4 1600)
>[ 26868.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89b30]
>[ 26868.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89b30] width 1600 pitch 6400 (/4 1600)
>[ 26869.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b75080]
>[ 26869.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b75080] width 1600 pitch 6400 (/4 1600)
>[ 26869.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89b30]
>[ 26869.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89b30] width 1600 pitch 6400 (/4 1600)
>[ 26869.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b75080]
>[ 26869.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b75080] width 1600 pitch 6400 (/4 1600)
>[ 26869.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89b30]
>[ 26869.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89b30] width 1600 pitch 6400 (/4 1600)
>[ 26869.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b75080]
>[ 26869.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b75080] width 1600 pitch 6400 (/4 1600)
>[ 26869.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b38e0]
>[ 26869.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b38e0] width 1600 pitch 6400 (/4 1600)
>[ 26870.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8950]
>[ 26870.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8950] width 1600 pitch 6400 (/4 1600)
>[ 26870.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b38e0]
>[ 26870.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b38e0] width 1600 pitch 6400 (/4 1600)
>[ 26870.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b75080]
>[ 26870.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b75080] width 1600 pitch 6400 (/4 1600)
>[ 26870.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b38e0]
>[ 26870.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b38e0] width 1600 pitch 6400 (/4 1600)
>[ 26870.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b75080]
>[ 26870.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b75080] width 1600 pitch 6400 (/4 1600)
>[ 26870.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21f8950]
>[ 26870.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21f8950] width 1600 pitch 6400 (/4 1600)
>[ 26872.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f133e0]
>[ 26872.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f133e0] width 1600 pitch 6400 (/4 1600)
>[ 26872.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bdf0d0]
>[ 26872.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bdf0d0] width 1600 pitch 6400 (/4 1600)
>[ 26876.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef1000]
>[ 26876.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef1000] width 1600 pitch 6400 (/4 1600)
>[ 26878.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d6fc60]
>[ 26878.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d6fc60] width 1600 pitch 6400 (/4 1600)
>[ 26878.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5c210]
>[ 26878.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5c210] width 1600 pitch 6400 (/4 1600)
>[ 26886.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0e610]
>[ 26886.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0e610] width 1600 pitch 6400 (/4 1600)
>[ 26886.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x219d9b0]
>[ 26886.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x219d9b0] width 1600 pitch 6400 (/4 1600)
>[ 26886.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0e610]
>[ 26886.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0e610] width 1600 pitch 6400 (/4 1600)
>[ 26886.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e89b30]
>[ 26886.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e89b30] width 1600 pitch 6400 (/4 1600)
>[ 26886.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0e610]
>[ 26886.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0e610] width 1600 pitch 6400 (/4 1600)
>[ 26890.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2299790]
>[ 26890.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2299790] width 1600 pitch 6400 (/4 1600)
>[ 26890.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2299790]
>[ 26890.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2299790] width 1600 pitch 6400 (/4 1600)
>[ 27395.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5d360]
>[ 27395.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5d360] width 1600 pitch 6400 (/4 1600)
>[ 27465.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bdc940]
>[ 27465.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bdc940] width 1600 pitch 6400 (/4 1600)
>[ 27465.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0fea0]
>[ 27465.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0fea0] width 1600 pitch 6400 (/4 1600)
>[ 27465.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d524c0]
>[ 27465.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d524c0] width 1600 pitch 6400 (/4 1600)
>[ 27465.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bde240]
>[ 27465.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bde240] width 1600 pitch 6400 (/4 1600)
>[ 27465.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d524c0]
>[ 27465.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d524c0] width 1600 pitch 6400 (/4 1600)
>[ 27465.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bde240]
>[ 27465.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bde240] width 1600 pitch 6400 (/4 1600)
>[ 27466.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bdce60]
>[ 27466.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bdce60] width 1600 pitch 6400 (/4 1600)
>[ 27466.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bdc950]
>[ 27466.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bdc950] width 1600 pitch 6400 (/4 1600)
>[ 27466.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0eb80]
>[ 27466.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0eb80] width 1600 pitch 6400 (/4 1600)
>[ 27466.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 27466.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 27467.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de82c0]
>[ 27467.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de82c0] width 1600 pitch 6400 (/4 1600)
>[ 27467.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0b090]
>[ 27467.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0b090] width 1600 pitch 6400 (/4 1600)
>[ 27467.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f0f7f0]
>[ 27467.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f0f7f0] width 1600 pitch 6400 (/4 1600)
>[ 27467.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf1630]
>[ 27467.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf1630] width 1600 pitch 6400 (/4 1600)
>[ 27467.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf16c0]
>[ 27467.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf16c0] width 1600 pitch 6400 (/4 1600)
>[ 27467.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f074d0]
>[ 27467.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f074d0] width 1600 pitch 6400 (/4 1600)
>[ 27468.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f07fe0]
>[ 27468.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f07fe0] width 1600 pitch 6400 (/4 1600)
>[ 27469.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3d360]
>[ 27469.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3d360] width 1600 pitch 6400 (/4 1600)
>[ 27470.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f07250]
>[ 27470.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f07250] width 1600 pitch 6400 (/4 1600)
>[ 27470.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f07250]
>[ 27470.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f07250] width 1600 pitch 6400 (/4 1600)
>[ 27470.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c20610]
>[ 27470.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c20610] width 1600 pitch 6400 (/4 1600)
>[ 27470.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f07250]
>[ 27470.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f07250] width 1600 pitch 6400 (/4 1600)
>[ 27470.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c20560]
>[ 27470.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c20560] width 1600 pitch 6400 (/4 1600)
>[ 27470.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c20610]
>[ 27470.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c20610] width 1600 pitch 6400 (/4 1600)
>[ 27582.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f09d90]
>[ 27582.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f09d90] width 1600 pitch 6400 (/4 1600)
>[ 27582.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de82c0]
>[ 27582.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de82c0] width 1600 pitch 6400 (/4 1600)
>[ 27582.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f09d90]
>[ 27582.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f09d90] width 1600 pitch 6400 (/4 1600)
>[ 27582.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de82c0]
>[ 27582.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de82c0] width 1600 pitch 6400 (/4 1600)
>[ 27582.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ed6530]
>[ 27582.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ed6530] width 1600 pitch 6400 (/4 1600)
>[ 27583.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de82c0]
>[ 27583.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de82c0] width 1600 pitch 6400 (/4 1600)
>[ 27583.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ed6530]
>[ 27583.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ed6530] width 1600 pitch 6400 (/4 1600)
>[ 27583.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de82c0]
>[ 27583.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de82c0] width 1600 pitch 6400 (/4 1600)
>[ 27583.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f09d90]
>[ 27583.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f09d90] width 1600 pitch 6400 (/4 1600)
>[ 27584.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de82c0]
>[ 27584.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de82c0] width 1600 pitch 6400 (/4 1600)
>[ 27584.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de82c0]
>[ 27584.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de82c0] width 1600 pitch 6400 (/4 1600)
>[ 27584.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c2d0]
>[ 27584.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c2d0] width 1600 pitch 6400 (/4 1600)
>[ 27584.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f09d90]
>[ 27584.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f09d90] width 1600 pitch 6400 (/4 1600)
>[ 27584.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c2d0]
>[ 27584.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c2d0] width 1600 pitch 6400 (/4 1600)
>[ 27584.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f09d90]
>[ 27585.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f09d90] width 1600 pitch 6400 (/4 1600)
>[ 27585.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c2d0]
>[ 27585.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c2d0] width 1600 pitch 6400 (/4 1600)
>[ 27605.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2285400]
>[ 27605.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2285400] width 1600 pitch 6400 (/4 1600)
>[ 27605.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eca220]
>[ 27605.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eca220] width 1600 pitch 6400 (/4 1600)
>[ 27605.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf0670]
>[ 27605.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf0670] width 1600 pitch 6400 (/4 1600)
>[ 27605.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x231f590]
>[ 27605.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x231f590] width 1600 pitch 6400 (/4 1600)
>[ 27605.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3d7a0]
>[ 27605.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3d7a0] width 1600 pitch 6400 (/4 1600)
>[ 27605.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22443f0]
>[ 27605.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22443f0] width 1600 pitch 6400 (/4 1600)
>[ 27605.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c00]
>[ 27605.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c00] width 1600 pitch 6400 (/4 1600)
>[ 27605.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a8070]
>[ 27605.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a8070] width 1600 pitch 6400 (/4 1600)
>[ 27605.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c00]
>[ 27605.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c00] width 1600 pitch 6400 (/4 1600)
>[ 27605.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a8070]
>[ 27605.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a8070] width 1600 pitch 6400 (/4 1600)
>[ 27605.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c00]
>[ 27605.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c00] width 1600 pitch 6400 (/4 1600)
>[ 27605.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a8070]
>[ 27605.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a8070] width 1600 pitch 6400 (/4 1600)
>[ 27605.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372c00]
>[ 27605.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372c00] width 1600 pitch 6400 (/4 1600)
>[ 27605.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a8070]
>[ 27605.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a8070] width 1600 pitch 6400 (/4 1600)
>[ 27605.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a1930]
>[ 27605.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a1930] width 1600 pitch 6400 (/4 1600)
>[ 27607.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x245b8b0]
>[ 27607.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x245b8b0] width 1600 pitch 6400 (/4 1600)
>[ 27607.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd32d0]
>[ 27607.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd32d0] width 1600 pitch 6400 (/4 1600)
>[ 27607.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c230]
>[ 27607.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c230] width 1600 pitch 6400 (/4 1600)
>[ 27607.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd32d0]
>[ 27607.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd32d0] width 1600 pitch 6400 (/4 1600)
>[ 27607.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3d7a0]
>[ 27608.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3d7a0] width 1600 pitch 6400 (/4 1600)
>[ 27608.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de5840]
>[ 27608.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de5840] width 1600 pitch 6400 (/4 1600)
>[ 27609.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be1810]
>[ 27609.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be1810] width 1600 pitch 6400 (/4 1600)
>[ 27609.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244e530]
>[ 27609.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244e530] width 1600 pitch 6400 (/4 1600)
>[ 27609.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc9ce0]
>[ 27609.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc9ce0] width 1600 pitch 6400 (/4 1600)
>[ 27610.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ed89d0]
>[ 27610.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ed89d0] width 1600 pitch 6400 (/4 1600)
>[ 27611.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc8350]
>[ 27611.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc8350] width 1600 pitch 6400 (/4 1600)
>[ 27612.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9f1d0]
>[ 27612.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9f1d0] width 1600 pitch 6400 (/4 1600)
>[ 27612.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c230]
>[ 27612.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c230] width 1600 pitch 6400 (/4 1600)
>[ 27612.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9f1d0]
>[ 27612.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9f1d0] width 1600 pitch 6400 (/4 1600)
>[ 27612.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c230]
>[ 27612.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c230] width 1600 pitch 6400 (/4 1600)
>[ 27612.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9f1d0]
>[ 27612.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9f1d0] width 1600 pitch 6400 (/4 1600)
>[ 27612.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c230]
>[ 27612.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c230] width 1600 pitch 6400 (/4 1600)
>[ 27612.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9f1d0]
>[ 27612.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9f1d0] width 1600 pitch 6400 (/4 1600)
>[ 27612.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c230]
>[ 27612.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c230] width 1600 pitch 6400 (/4 1600)
>[ 27612.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5fa00]
>[ 27612.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5fa00] width 1600 pitch 6400 (/4 1600)
>[ 27612.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d72840]
>[ 27612.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d72840] width 1600 pitch 6400 (/4 1600)
>[ 27612.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2456dd0]
>[ 27612.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2456dd0] width 1600 pitch 6400 (/4 1600)
>[ 27613.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d72840]
>[ 27613.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d72840] width 1600 pitch 6400 (/4 1600)
>[ 27613.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2456dd0]
>[ 27613.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2456dd0] width 1600 pitch 6400 (/4 1600)
>[ 27614.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de82c0]
>[ 27614.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de82c0] width 1600 pitch 6400 (/4 1600)
>[ 27614.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e56790]
>[ 27614.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e56790] width 1600 pitch 6400 (/4 1600)
>[ 27615.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259c2d0]
>[ 27615.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259c2d0] width 1600 pitch 6400 (/4 1600)
>[ 27616.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de5840]
>[ 27616.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de5840] width 1600 pitch 6400 (/4 1600)
>[ 27617.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x226ca80]
>[ 27617.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x226ca80] width 1600 pitch 6400 (/4 1600)
>[ 27617.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ed8db0]
>[ 27617.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ed8db0] width 1600 pitch 6400 (/4 1600)
>[ 27617.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ed6530]
>[ 27617.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ed6530] width 1600 pitch 6400 (/4 1600)
>[ 27618.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aa00]
>[ 27618.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aa00] width 1600 pitch 6400 (/4 1600)
>[ 27619.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2567d80]
>[ 27619.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2567d80] width 1600 pitch 6400 (/4 1600)
>[ 27619.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aa00]
>[ 27619.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aa00] width 1600 pitch 6400 (/4 1600)
>[ 27619.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2567d80]
>[ 27619.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2567d80] width 1600 pitch 6400 (/4 1600)
>[ 27619.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de0f50]
>[ 27619.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de0f50] width 1600 pitch 6400 (/4 1600)
>[ 27619.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de0f50]
>[ 27619.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de0f50] width 1600 pitch 6400 (/4 1600)
>[ 27619.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aa00]
>[ 27619.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aa00] width 1600 pitch 6400 (/4 1600)
>[ 27619.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de0f50]
>[ 27619.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de0f50] width 1600 pitch 6400 (/4 1600)
>[ 27619.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aa00]
>[ 27619.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aa00] width 1600 pitch 6400 (/4 1600)
>[ 27619.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229d550]
>[ 27619.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229d550] width 1600 pitch 6400 (/4 1600)
>[ 27620.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aa00]
>[ 27620.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aa00] width 1600 pitch 6400 (/4 1600)
>[ 27620.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de0f50]
>[ 27620.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de0f50] width 1600 pitch 6400 (/4 1600)
>[ 27620.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c3af0]
>[ 27620.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c3af0] width 1600 pitch 6400 (/4 1600)
>[ 27620.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c367c0]
>[ 27620.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c367c0] width 1600 pitch 6400 (/4 1600)
>[ 27620.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c3af0]
>[ 27620.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c3af0] width 1600 pitch 6400 (/4 1600)
>[ 27620.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c367c0]
>[ 27620.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c367c0] width 1600 pitch 6400 (/4 1600)
>[ 27620.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c3af0]
>[ 27620.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c3af0] width 1600 pitch 6400 (/4 1600)
>[ 27620.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c367c0]
>[ 27620.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c367c0] width 1600 pitch 6400 (/4 1600)
>[ 27620.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e3e0]
>[ 27620.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e3e0] width 1600 pitch 6400 (/4 1600)
>[ 27620.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c367c0]
>[ 27620.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c367c0] width 1600 pitch 6400 (/4 1600)
>[ 27620.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229e3e0]
>[ 27620.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229e3e0] width 1600 pitch 6400 (/4 1600)
>[ 27622.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e5e770]
>[ 27622.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e5e770] width 1600 pitch 6400 (/4 1600)
>[ 27622.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ef9440]
>[ 27622.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ef9440] width 1600 pitch 6400 (/4 1600)
>[ 27622.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d3cd20]
>[ 27622.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d3cd20] width 1600 pitch 6400 (/4 1600)
>[ 27656.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7bc20]
>[ 27656.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7bc20] width 1600 pitch 6400 (/4 1600)
>[ 27656.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c24770]
>[ 27656.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c24770] width 1600 pitch 6400 (/4 1600)
>[ 27656.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2241ce0]
>[ 27656.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2241ce0] width 1600 pitch 6400 (/4 1600)
>[ 27656.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c24770]
>[ 27656.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c24770] width 1600 pitch 6400 (/4 1600)
>[ 27656.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2241ce0]
>[ 27656.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2241ce0] width 1600 pitch 6400 (/4 1600)
>[ 27656.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c24770]
>[ 27656.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c24770] width 1600 pitch 6400 (/4 1600)
>[ 27656.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2241ce0]
>[ 27656.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2241ce0] width 1600 pitch 6400 (/4 1600)
>[ 27656.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c24770]
>[ 27656.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c24770] width 1600 pitch 6400 (/4 1600)
>[ 27656.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2241ce0]
>[ 27656.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2241ce0] width 1600 pitch 6400 (/4 1600)
>[ 27656.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c24770]
>[ 27656.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c24770] width 1600 pitch 6400 (/4 1600)
>[ 27656.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2241ce0]
>[ 27656.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2241ce0] width 1600 pitch 6400 (/4 1600)
>[ 27656.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c24770]
>[ 27656.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c24770] width 1600 pitch 6400 (/4 1600)
>[ 27656.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244e780]
>[ 27656.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244e780] width 1600 pitch 6400 (/4 1600)
>[ 27656.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f06d40]
>[ 27656.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f06d40] width 1600 pitch 6400 (/4 1600)
>[ 28763.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x237ab70]
>[ 28763.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x237ab70] width 1600 pitch 6400 (/4 1600)
>[ 28763.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eaea60]
>[ 28763.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eaea60] width 1600 pitch 6400 (/4 1600)
>[ 28763.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x237ab70]
>[ 28763.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x237ab70] width 1600 pitch 6400 (/4 1600)
>[ 28763.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eaea60]
>[ 28763.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eaea60] width 1600 pitch 6400 (/4 1600)
>[ 28763.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x237ab70]
>[ 28763.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x237ab70] width 1600 pitch 6400 (/4 1600)
>[ 28763.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eaea60]
>[ 28763.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eaea60] width 1600 pitch 6400 (/4 1600)
>[ 28763.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x237ab70]
>[ 28763.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x237ab70] width 1600 pitch 6400 (/4 1600)
>[ 28763.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eaea60]
>[ 28763.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eaea60] width 1600 pitch 6400 (/4 1600)
>[ 28763.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229d550]
>[ 28763.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229d550] width 1600 pitch 6400 (/4 1600)
>[ 28764.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5aa00]
>[ 28764.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5aa00] width 1600 pitch 6400 (/4 1600)
>[ 28764.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229d550]
>[ 28764.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229d550] width 1600 pitch 6400 (/4 1600)
>[ 28764.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb92b0]
>[ 28764.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb92b0] width 1600 pitch 6400 (/4 1600)
>[ 28764.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480e60]
>[ 28764.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480e60] width 1600 pitch 6400 (/4 1600)
>[ 28764.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb92b0]
>[ 28764.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb92b0] width 1600 pitch 6400 (/4 1600)
>[ 28764.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480e60]
>[ 28764.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480e60] width 1600 pitch 6400 (/4 1600)
>[ 28764.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244dd10]
>[ 28764.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244dd10] width 1600 pitch 6400 (/4 1600)
>[ 28764.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2480e60]
>[ 28764.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2480e60] width 1600 pitch 6400 (/4 1600)
>[ 28764.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244dd10]
>[ 28764.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244dd10] width 1600 pitch 6400 (/4 1600)
>[ 28764.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddf890]
>[ 28764.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddf890] width 1600 pitch 6400 (/4 1600)
>[ 28764.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9f1d0]
>[ 28764.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9f1d0] width 1600 pitch 6400 (/4 1600)
>[ 29014.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c36820]
>[ 29014.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c36820] width 1600 pitch 6400 (/4 1600)
>[ 29021.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 29021.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 29021.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c102b0]
>[ 29021.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c102b0] width 1600 pitch 6400 (/4 1600)
>[ 29021.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 29021.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 29021.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c102b0]
>[ 29021.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c102b0] width 1600 pitch 6400 (/4 1600)
>[ 29021.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 29021.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 29021.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c102b0]
>[ 29021.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c102b0] width 1600 pitch 6400 (/4 1600)
>[ 29021.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 29021.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 29021.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c102b0]
>[ 29021.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c102b0] width 1600 pitch 6400 (/4 1600)
>[ 29021.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 29021.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 29021.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c102b0]
>[ 29021.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c102b0] width 1600 pitch 6400 (/4 1600)
>[ 29021.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 29021.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 29021.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c102b0]
>[ 29021.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c102b0] width 1600 pitch 6400 (/4 1600)
>[ 29021.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 29021.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 29021.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x239def0]
>[ 29021.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x239def0] width 1600 pitch 6400 (/4 1600)
>[ 29021.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0f1e0]
>[ 29021.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0f1e0] width 1600 pitch 6400 (/4 1600)
>[ 29021.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x239def0]
>[ 29021.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x239def0] width 1600 pitch 6400 (/4 1600)
>[ 29021.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebf1f0]
>[ 29021.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebf1f0] width 1600 pitch 6400 (/4 1600)
>[ 29022.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x239def0]
>[ 29022.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x239def0] width 1600 pitch 6400 (/4 1600)
>[ 29022.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ebf1f0]
>[ 29022.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ebf1f0] width 1600 pitch 6400 (/4 1600)
>[ 29022.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x239def0]
>[ 29022.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x239def0] width 1600 pitch 6400 (/4 1600)
>[ 29022.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9b870]
>[ 29022.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9b870] width 1600 pitch 6400 (/4 1600)
>[ 29022.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2298c00]
>[ 29023.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2298c00] width 1600 pitch 6400 (/4 1600)
>[ 29023.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21743c0]
>[ 29023.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21743c0] width 1600 pitch 6400 (/4 1600)
>[ 29024.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d56020]
>[ 29024.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d56020] width 1600 pitch 6400 (/4 1600)
>[ 29024.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21743c0]
>[ 29024.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21743c0] width 1600 pitch 6400 (/4 1600)
>[ 29024.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d56020]
>[ 29024.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d56020] width 1600 pitch 6400 (/4 1600)
>[ 29024.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc1db0]
>[ 29024.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc1db0] width 1600 pitch 6400 (/4 1600)
>[ 29024.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d56020]
>[ 29024.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d56020] width 1600 pitch 6400 (/4 1600)
>[ 29024.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc1db0]
>[ 29024.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc1db0] width 1600 pitch 6400 (/4 1600)
>[ 29024.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d56020]
>[ 29024.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d56020] width 1600 pitch 6400 (/4 1600)
>[ 29024.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bc1db0]
>[ 29024.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bc1db0] width 1600 pitch 6400 (/4 1600)
>[ 29025.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ca1bf0]
>[ 29025.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ca1bf0] width 1600 pitch 6400 (/4 1600)
>[ 29026.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x224e690]
>[ 29026.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x224e690] width 1600 pitch 6400 (/4 1600)
>[ 29032.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1720]
>[ 29032.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1720] width 1600 pitch 6400 (/4 1600)
>[ 29032.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3750]
>[ 29032.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3750] width 1600 pitch 6400 (/4 1600)
>[ 29032.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1720]
>[ 29032.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1720] width 1600 pitch 6400 (/4 1600)
>[ 29032.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3750]
>[ 29032.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3750] width 1600 pitch 6400 (/4 1600)
>[ 29032.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1720]
>[ 29032.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1720] width 1600 pitch 6400 (/4 1600)
>[ 29032.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3750]
>[ 29032.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3750] width 1600 pitch 6400 (/4 1600)
>[ 29032.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1720]
>[ 29032.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1720] width 1600 pitch 6400 (/4 1600)
>[ 29032.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3750]
>[ 29032.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3750] width 1600 pitch 6400 (/4 1600)
>[ 29032.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1720]
>[ 29032.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1720] width 1600 pitch 6400 (/4 1600)
>[ 29032.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3750]
>[ 29032.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3750] width 1600 pitch 6400 (/4 1600)
>[ 29032.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1720]
>[ 29032.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1720] width 1600 pitch 6400 (/4 1600)
>[ 29032.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3750]
>[ 29032.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3750] width 1600 pitch 6400 (/4 1600)
>[ 29032.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1720]
>[ 29032.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1720] width 1600 pitch 6400 (/4 1600)
>[ 29032.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3750]
>[ 29032.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3750] width 1600 pitch 6400 (/4 1600)
>[ 29032.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c1720]
>[ 29032.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c1720] width 1600 pitch 6400 (/4 1600)
>[ 29032.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3750]
>[ 29032.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3750] width 1600 pitch 6400 (/4 1600)
>[ 29049.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2454aa0]
>[ 29049.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2454aa0] width 1600 pitch 6400 (/4 1600)
>[ 29049.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1a7d0]
>[ 29049.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1a7d0] width 1600 pitch 6400 (/4 1600)
>[ 29063.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24493f0]
>[ 29063.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24493f0] width 1600 pitch 6400 (/4 1600)
>[ 29063.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e49150]
>[ 29063.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e49150] width 1600 pitch 6400 (/4 1600)
>[ 29142.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a3bc0]
>[ 29142.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a3bc0] width 1600 pitch 6400 (/4 1600)
>[ 29142.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229f060]
>[ 29142.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229f060] width 1600 pitch 6400 (/4 1600)
>[ 29142.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23cb610]
>[ 29142.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23cb610] width 1600 pitch 6400 (/4 1600)
>[ 29142.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eabb20]
>[ 29142.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eabb20] width 1600 pitch 6400 (/4 1600)
>[ 29142.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23cb610]
>[ 29142.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23cb610] width 1600 pitch 6400 (/4 1600)
>[ 29142.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d55f80]
>[ 29142.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d55f80] width 1600 pitch 6400 (/4 1600)
>[ 29142.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bb58c0]
>[ 29143.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bb58c0] width 1600 pitch 6400 (/4 1600)
>[ 29143.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a47f0]
>[ 29143.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a47f0] width 1600 pitch 6400 (/4 1600)
>[ 29143.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23cb610]
>[ 29143.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23cb610] width 1600 pitch 6400 (/4 1600)
>[ 29143.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22509b0]
>[ 29143.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22509b0] width 1600 pitch 6400 (/4 1600)
>[ 29143.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23cb610]
>[ 29143.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23cb610] width 1600 pitch 6400 (/4 1600)
>[ 29143.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229f060]
>[ 29143.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229f060] width 1600 pitch 6400 (/4 1600)
>[ 29143.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a47f0]
>[ 29143.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a47f0] width 1600 pitch 6400 (/4 1600)
>[ 29163.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e842f0]
>[ 29163.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e842f0] width 1600 pitch 6400 (/4 1600)
>[ 29163.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ea820]
>[ 29163.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ea820] width 1600 pitch 6400 (/4 1600)
>[ 29183.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320200]
>[ 29183.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320200] width 1600 pitch 6400 (/4 1600)
>[ 29183.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a5390]
>[ 29183.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a5390] width 1600 pitch 6400 (/4 1600)
>[ 29183.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b769c0]
>[ 29183.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b769c0] width 1600 pitch 6400 (/4 1600)
>[ 29202.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0e7e0]
>[ 29202.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0e7e0] width 1600 pitch 6400 (/4 1600)
>[ 29202.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22190]
>[ 29202.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22190] width 1600 pitch 6400 (/4 1600)
>[ 29202.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b750a0]
>[ 29202.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b750a0] width 1600 pitch 6400 (/4 1600)
>[ 29202.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320200]
>[ 29202.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320200] width 1600 pitch 6400 (/4 1600)
>[ 29202.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0e7e0]
>[ 29202.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0e7e0] width 1600 pitch 6400 (/4 1600)
>[ 29202.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c22190]
>[ 29202.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c22190] width 1600 pitch 6400 (/4 1600)
>[ 29203.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320200]
>[ 29203.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320200] width 1600 pitch 6400 (/4 1600)
>[ 29203.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0e7e0]
>[ 29203.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0e7e0] width 1600 pitch 6400 (/4 1600)
>[ 29203.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320200]
>[ 29203.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320200] width 1600 pitch 6400 (/4 1600)
>[ 29203.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0e7e0]
>[ 29203.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0e7e0] width 1600 pitch 6400 (/4 1600)
>[ 29203.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320200]
>[ 29203.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320200] width 1600 pitch 6400 (/4 1600)
>[ 29203.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0e7e0]
>[ 29203.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0e7e0] width 1600 pitch 6400 (/4 1600)
>[ 29203.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320200]
>[ 29203.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320200] width 1600 pitch 6400 (/4 1600)
>[ 29203.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1b750a0]
>[ 29203.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1b750a0] width 1600 pitch 6400 (/4 1600)
>[ 29882.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c3a800]
>[ 29882.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c3a800] width 1600 pitch 6400 (/4 1600)
>[ 29882.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb90e0]
>[ 29882.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb90e0] width 1600 pitch 6400 (/4 1600)
>[ 29901.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2482510]
>[ 29901.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2482510] width 1600 pitch 6400 (/4 1600)
>[ 29901.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22500b0]
>[ 29901.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22500b0] width 1600 pitch 6400 (/4 1600)
>[ 30003.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e9d840]
>[ 30003.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e9d840] width 1600 pitch 6400 (/4 1600)
>[ 30003.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x249bde0]
>[ 30003.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x249bde0] width 1600 pitch 6400 (/4 1600)
>[ 30122.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248f190]
>[ 30122.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248f190] width 1600 pitch 6400 (/4 1600)
>[ 30122.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2228c40]
>[ 30122.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2228c40] width 1600 pitch 6400 (/4 1600)
>[ 30122.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df78b0]
>[ 30122.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df78b0] width 1600 pitch 6400 (/4 1600)
>[ 30122.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be68b0]
>[ 30122.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be68b0] width 1600 pitch 6400 (/4 1600)
>[ 30122.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248f190]
>[ 30122.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248f190] width 1600 pitch 6400 (/4 1600)
>[ 30122.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320240]
>[ 30122.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320240] width 1600 pitch 6400 (/4 1600)
>[ 30122.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a5590]
>[ 30122.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a5590] width 1600 pitch 6400 (/4 1600)
>[ 30122.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320240]
>[ 30122.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320240] width 1600 pitch 6400 (/4 1600)
>[ 30122.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a5590]
>[ 30122.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a5590] width 1600 pitch 6400 (/4 1600)
>[ 30122.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320240]
>[ 30122.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320240] width 1600 pitch 6400 (/4 1600)
>[ 30122.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a5590]
>[ 30122.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a5590] width 1600 pitch 6400 (/4 1600)
>[ 30122.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320240]
>[ 30122.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320240] width 1600 pitch 6400 (/4 1600)
>[ 30123.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d79060]
>[ 30123.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d79060] width 1600 pitch 6400 (/4 1600)
>[ 30123.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2497fa0]
>[ 30123.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2497fa0] width 1600 pitch 6400 (/4 1600)
>[ 30123.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d48870]
>[ 30123.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d48870] width 1600 pitch 6400 (/4 1600)
>[ 30123.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2497fa0]
>[ 30123.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2497fa0] width 1600 pitch 6400 (/4 1600)
>[ 30123.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d48870]
>[ 30123.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d48870] width 1600 pitch 6400 (/4 1600)
>[ 30123.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2497fa0]
>[ 30123.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2497fa0] width 1600 pitch 6400 (/4 1600)
>[ 30123.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d48870]
>[ 30123.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d48870] width 1600 pitch 6400 (/4 1600)
>[ 30123.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2497fa0]
>[ 30123.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2497fa0] width 1600 pitch 6400 (/4 1600)
>[ 30123.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d48870]
>[ 30123.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d48870] width 1600 pitch 6400 (/4 1600)
>[ 30123.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2497fa0]
>[ 30123.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2497fa0] width 1600 pitch 6400 (/4 1600)
>[ 30123.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d48870]
>[ 30123.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d48870] width 1600 pitch 6400 (/4 1600)
>[ 30123.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2497fa0]
>[ 30123.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2497fa0] width 1600 pitch 6400 (/4 1600)
>[ 30124.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d48870]
>[ 30124.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d48870] width 1600 pitch 6400 (/4 1600)
>[ 30124.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e65f80]
>[ 30124.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e65f80] width 1600 pitch 6400 (/4 1600)
>[ 30124.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df78b0]
>[ 30124.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df78b0] width 1600 pitch 6400 (/4 1600)
>[ 30124.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be68b0]
>[ 30124.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be68b0] width 1600 pitch 6400 (/4 1600)
>[ 30124.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248f190]
>[ 30124.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248f190] width 1600 pitch 6400 (/4 1600)
>[ 30124.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2320240]
>[ 30124.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2320240] width 1600 pitch 6400 (/4 1600)
>[ 30124.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22a5590]
>[ 30124.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22a5590] width 1600 pitch 6400 (/4 1600)
>[ 30124.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c291e0]
>[ 30124.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c291e0] width 1600 pitch 6400 (/4 1600)
>[ 30124.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a3300]
>[ 30124.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a3300] width 1600 pitch 6400 (/4 1600)
>[ 30648.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd0ba0]
>[ 30648.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd0ba0] width 1600 pitch 6400 (/4 1600)
>[ 30648.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30648.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30648.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd0ba0]
>[ 30648.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd0ba0] width 1600 pitch 6400 (/4 1600)
>[ 30648.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30648.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30648.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd0ba0]
>[ 30648.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd0ba0] width 1600 pitch 6400 (/4 1600)
>[ 30648.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30648.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30648.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd0ba0]
>[ 30648.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd0ba0] width 1600 pitch 6400 (/4 1600)
>[ 30648.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30648.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30648.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30648.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30648.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30648.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30648.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30648.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30648.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30648.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30648.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30648.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30648.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30648.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30648.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30648.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30648.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30648.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30648.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30648.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30649.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30649.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30649.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30649.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30649.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30649.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30649.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30649.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30649.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30649.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30649.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30649.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30649.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30649.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30649.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30649.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30649.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30649.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30649.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30649.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30649.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30649.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30649.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30649.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30649.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30649.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30649.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30649.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30650.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30650.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30650.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30650.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30650.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cd0ba0]
>[ 30650.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cd0ba0] width 1600 pitch 6400 (/4 1600)
>[ 30650.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30650.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30650.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30650.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30650.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30650.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30650.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30650.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30650.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30650.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30650.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2450960]
>[ 30650.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2450960] width 1600 pitch 6400 (/4 1600)
>[ 30650.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23b6490]
>[ 30650.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23b6490] width 1600 pitch 6400 (/4 1600)
>[ 30650.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e10fb0]
>[ 30650.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e10fb0] width 1600 pitch 6400 (/4 1600)
>[ 30650.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e97ca0]
>[ 30650.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e97ca0] width 1600 pitch 6400 (/4 1600)
>[ 30650.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ebbe0]
>[ 30650.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ebbe0] width 1600 pitch 6400 (/4 1600)
>[ 30912.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30912.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30912.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30912.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30951.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30951.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30951.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30951.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30951.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30951.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30951.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30951.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30951.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30951.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30951.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30951.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30951.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30951.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30951.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30951.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30951.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30951.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30951.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30951.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30951.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30951.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30951.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30951.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30951.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30951.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30951.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30951.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30951.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30951.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30952.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30952.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30952.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247d2e0]
>[ 30952.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247d2e0] width 1600 pitch 6400 (/4 1600)
>[ 30952.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30952.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 30952.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247e5c0]
>[ 30952.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247e5c0] width 1600 pitch 6400 (/4 1600)
>[ 30953.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e841f0]
>[ 30953.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e841f0] width 1600 pitch 6400 (/4 1600)
>[ 31001.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24469e0]
>[ 31001.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24469e0] width 1600 pitch 6400 (/4 1600)
>[ 31001.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2446ea0]
>[ 31001.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2446ea0] width 1600 pitch 6400 (/4 1600)
>[ 31011.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24469e0]
>[ 31011.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24469e0] width 1600 pitch 6400 (/4 1600)
>[ 31050.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254bcc0]
>[ 31050.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254bcc0] width 1600 pitch 6400 (/4 1600)
>[ 31050.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d08a40]
>[ 31050.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d08a40] width 1600 pitch 6400 (/4 1600)
>[ 31050.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254bcc0]
>[ 31050.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254bcc0] width 1600 pitch 6400 (/4 1600)
>[ 31050.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d08a40]
>[ 31050.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d08a40] width 1600 pitch 6400 (/4 1600)
>[ 31050.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254bcc0]
>[ 31050.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254bcc0] width 1600 pitch 6400 (/4 1600)
>[ 31050.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d08a40]
>[ 31050.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d08a40] width 1600 pitch 6400 (/4 1600)
>[ 31050.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254bcc0]
>[ 31050.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254bcc0] width 1600 pitch 6400 (/4 1600)
>[ 31050.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d08a40]
>[ 31050.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d08a40] width 1600 pitch 6400 (/4 1600)
>[ 31050.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254bcc0]
>[ 31050.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254bcc0] width 1600 pitch 6400 (/4 1600)
>[ 31050.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31050.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31051.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31051.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31051.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2499b20]
>[ 31051.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2499b20] width 1600 pitch 6400 (/4 1600)
>[ 31051.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31051.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31051.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254bcc0]
>[ 31051.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254bcc0] width 1600 pitch 6400 (/4 1600)
>[ 31051.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31051.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31051.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254bcc0]
>[ 31051.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254bcc0] width 1600 pitch 6400 (/4 1600)
>[ 31051.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31051.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31051.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254bcc0]
>[ 31051.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254bcc0] width 1600 pitch 6400 (/4 1600)
>[ 31063.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2448b60]
>[ 31063.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2448b60] width 1600 pitch 6400 (/4 1600)
>[ 31065.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0fdc0]
>[ 31065.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0fdc0] width 1600 pitch 6400 (/4 1600)
>[ 31065.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d50ce0]
>[ 31065.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d50ce0] width 1600 pitch 6400 (/4 1600)
>[ 31065.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0fdc0]
>[ 31065.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0fdc0] width 1600 pitch 6400 (/4 1600)
>[ 31065.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31065.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31065.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d50ce0]
>[ 31065.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d50ce0] width 1600 pitch 6400 (/4 1600)
>[ 31065.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31065.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31065.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0fdc0]
>[ 31065.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0fdc0] width 1600 pitch 6400 (/4 1600)
>[ 31065.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0fdc0]
>[ 31065.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0fdc0] width 1600 pitch 6400 (/4 1600)
>[ 31065.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d50ce0]
>[ 31065.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d50ce0] width 1600 pitch 6400 (/4 1600)
>[ 31066.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d50ce0]
>[ 31066.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d50ce0] width 1600 pitch 6400 (/4 1600)
>[ 31066.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31066.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31066.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31066.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31066.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31066.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31066.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0fdc0]
>[ 31066.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0fdc0] width 1600 pitch 6400 (/4 1600)
>[ 31067.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31067.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31067.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0fdc0]
>[ 31067.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0fdc0] width 1600 pitch 6400 (/4 1600)
>[ 31067.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31067.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31067.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0fdc0]
>[ 31067.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0fdc0] width 1600 pitch 6400 (/4 1600)
>[ 31067.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x247b2b0]
>[ 31067.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x247b2b0] width 1600 pitch 6400 (/4 1600)
>[ 31067.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0fdc0]
>[ 31067.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0fdc0] width 1600 pitch 6400 (/4 1600)
>[ 31067.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f124b0]
>[ 31067.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f124b0] width 1600 pitch 6400 (/4 1600)
>[ 31067.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d50ce0]
>[ 31067.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d50ce0] width 1600 pitch 6400 (/4 1600)
>[ 31080.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f2a030]
>[ 31080.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f2a030] width 1600 pitch 6400 (/4 1600)
>[ 31084.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f12440]
>[ 31084.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f12440] width 1600 pitch 6400 (/4 1600)
>[ 31115.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31115.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31115.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31115.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31115.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31115.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31115.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31115.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31115.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31115.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31115.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31115.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31115.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31115.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31116.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31116.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31116.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31116.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31116.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31116.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31116.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31116.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31116.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31116.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31116.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31116.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31116.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31116.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31116.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31116.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31116.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31116.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31116.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31117.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31193.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31193.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31194.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31194.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31194.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31194.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31194.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31194.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31194.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31194.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31194.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31194.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31194.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31194.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31194.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31194.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31194.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31194.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31194.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31194.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31194.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31194.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31194.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31194.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31194.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31194.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31195.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31195.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31196.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31196.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31196.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31196.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31196.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31196.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31196.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31197.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31197.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31197.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31197.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31197.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31197.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31197.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31197.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31197.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31197.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31197.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31197.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31197.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31197.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31197.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31215.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31215.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31215.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31215.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31215.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31215.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31215.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31215.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31215.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31215.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31215.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31215.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31216.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31216.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31216.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31216.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31216.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31216.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31216.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31216.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31216.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31216.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31216.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31216.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31217.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31217.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31217.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e2830]
>[ 31217.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e2830] width 1600 pitch 6400 (/4 1600)
>[ 31217.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31217.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31217.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31218.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31218.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e62bc0]
>[ 31218.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e62bc0] width 1600 pitch 6400 (/4 1600)
>[ 31218.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31218.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31218.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31218.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31218.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31218.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31218.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e62bc0]
>[ 31218.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e62bc0] width 1600 pitch 6400 (/4 1600)
>[ 31218.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31218.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31218.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31218.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31218.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31218.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31218.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31218.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31218.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31218.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31218.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31218.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31218.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31219.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31219.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31219.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31219.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e62bc0]
>[ 31219.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e62bc0] width 1600 pitch 6400 (/4 1600)
>[ 31219.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31219.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31220.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1def640]
>[ 31220.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1def640] width 1600 pitch 6400 (/4 1600)
>[ 31220.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31220.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31220.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e0d670]
>[ 31220.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e0d670] width 1600 pitch 6400 (/4 1600)
>[ 31220.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f2bc0]
>[ 31220.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f2bc0] width 1600 pitch 6400 (/4 1600)
>[ 31220.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9c80]
>[ 31220.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9c80] width 1600 pitch 6400 (/4 1600)
>[ 31220.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e62bc0]
>[ 31220.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e62bc0] width 1600 pitch 6400 (/4 1600)
>[ 31220.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31220.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31228.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31228.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31228.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31228.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31228.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31228.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31228.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31228.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31228.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31228.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31228.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31228.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31228.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31228.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31228.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31228.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31229.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31229.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31229.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31229.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31229.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ef600]
>[ 31229.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ef600] width 1600 pitch 6400 (/4 1600)
>[ 31229.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31229.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31230.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31230.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31230.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31230.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31230.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31230.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31230.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31230.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31230.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31230.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31230.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31230.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31230.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31230.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31244.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31244.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31244.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31244.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31244.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31244.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31244.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31244.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31244.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31244.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31244.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31244.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31244.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31244.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31244.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31245.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31245.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31245.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31245.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31245.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31245.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31245.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31245.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31245.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31245.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31245.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31246.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31246.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31246.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31246.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31246.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31246.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31246.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31246.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31246.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd53f0]
>[ 31246.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd53f0] width 1600 pitch 6400 (/4 1600)
>[ 31246.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 31246.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 31246.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f29900]
>[ 31246.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f29900] width 1600 pitch 6400 (/4 1600)
>[ 31339.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbe050]
>[ 31339.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbe050] width 1600 pitch 6400 (/4 1600)
>[ 31339.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31339.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31339.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31339.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31339.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbe050]
>[ 31339.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbe050] width 1600 pitch 6400 (/4 1600)
>[ 31339.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31339.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31339.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbe050]
>[ 31339.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbe050] width 1600 pitch 6400 (/4 1600)
>[ 31339.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31339.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31339.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbe050]
>[ 31339.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbe050] width 1600 pitch 6400 (/4 1600)
>[ 31339.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31339.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31340.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbe050]
>[ 31340.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbe050] width 1600 pitch 6400 (/4 1600)
>[ 31340.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31340.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31340.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbe050]
>[ 31340.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbe050] width 1600 pitch 6400 (/4 1600)
>[ 31340.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31340.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31340.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc640]
>[ 31340.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc640] width 1600 pitch 6400 (/4 1600)
>[ 31340.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31340.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31341.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31341.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31341.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31341.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31341.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ec930]
>[ 31341.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ec930] width 1600 pitch 6400 (/4 1600)
>[ 31341.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31341.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31341.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ec930]
>[ 31341.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ec930] width 1600 pitch 6400 (/4 1600)
>[ 31341.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31341.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31341.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31341.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31341.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ec930]
>[ 31341.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ec930] width 1600 pitch 6400 (/4 1600)
>[ 31341.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31341.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31341.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ec930]
>[ 31341.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ec930] width 1600 pitch 6400 (/4 1600)
>[ 31341.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31341.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31341.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ec930]
>[ 31341.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ec930] width 1600 pitch 6400 (/4 1600)
>[ 31342.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31342.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31342.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ec930]
>[ 31342.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ec930] width 1600 pitch 6400 (/4 1600)
>[ 31342.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31342.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31342.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc640]
>[ 31342.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc640] width 1600 pitch 6400 (/4 1600)
>[ 31342.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31342.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31342.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc640]
>[ 31342.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc640] width 1600 pitch 6400 (/4 1600)
>[ 31342.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31342.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31342.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcc640]
>[ 31342.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcc640] width 1600 pitch 6400 (/4 1600)
>[ 31343.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31343.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31343.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ebb30]
>[ 31343.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ebb30] width 1600 pitch 6400 (/4 1600)
>[ 31416.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dba100]
>[ 31416.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dba100] width 1600 pitch 6400 (/4 1600)
>[ 31416.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c9c60]
>[ 31416.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c9c60] width 1600 pitch 6400 (/4 1600)
>[ 31421.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1000]
>[ 31421.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1000] width 1600 pitch 6400 (/4 1600)
>[ 31421.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbe050]
>[ 31421.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbe050] width 1600 pitch 6400 (/4 1600)
>[ 31421.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ebb30]
>[ 31421.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ebb30] width 1600 pitch 6400 (/4 1600)
>[ 31421.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c9c60]
>[ 31421.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c9c60] width 1600 pitch 6400 (/4 1600)
>[ 31421.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f15d0]
>[ 31421.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f15d0] width 1600 pitch 6400 (/4 1600)
>[ 31421.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc4bf0]
>[ 31421.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc4bf0] width 1600 pitch 6400 (/4 1600)
>[ 31421.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d80c70]
>[ 31421.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d80c70] width 1600 pitch 6400 (/4 1600)
>[ 31421.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be43c0]
>[ 31421.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be43c0] width 1600 pitch 6400 (/4 1600)
>[ 31421.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fa4d0]
>[ 31421.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fa4d0] width 1600 pitch 6400 (/4 1600)
>[ 31422.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbe050]
>[ 31422.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbe050] width 1600 pitch 6400 (/4 1600)
>[ 31422.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ebb30]
>[ 31422.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ebb30] width 1600 pitch 6400 (/4 1600)
>[ 31422.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc0660]
>[ 31422.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc0660] width 1600 pitch 6400 (/4 1600)
>[ 31422.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dba100]
>[ 31422.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dba100] width 1600 pitch 6400 (/4 1600)
>[ 31422.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f5520]
>[ 31422.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f5520] width 1600 pitch 6400 (/4 1600)
>[ 31422.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460]
>[ 31422.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1600 pitch 6400 (/4 1600)
>[ 31422.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f47a90]
>[ 31422.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f47a90] width 1600 pitch 6400 (/4 1600)
>[ 31422.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dba100]
>[ 31422.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dba100] width 1600 pitch 6400 (/4 1600)
>[ 31422.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d80c70]
>[ 31422.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d80c70] width 1600 pitch 6400 (/4 1600)
>[ 31430.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc9860]
>[ 31430.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc9860] width 1600 pitch 6400 (/4 1600)
>[ 31430.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460]
>[ 31430.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1600 pitch 6400 (/4 1600)
>[ 31430.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d80c70]
>[ 31430.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d80c70] width 1600 pitch 6400 (/4 1600)
>[ 31430.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f7170]
>[ 31430.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f7170] width 1600 pitch 6400 (/4 1600)
>[ 31430.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c11250]
>[ 31430.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c11250] width 1600 pitch 6400 (/4 1600)
>[ 31430.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fa4d0]
>[ 31430.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fa4d0] width 1600 pitch 6400 (/4 1600)
>[ 31430.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31430.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31430.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ca2c0]
>[ 31430.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ca2c0] width 1600 pitch 6400 (/4 1600)
>[ 31430.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460]
>[ 31431.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1600 pitch 6400 (/4 1600)
>[ 31431.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fa4d0]
>[ 31431.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fa4d0] width 1600 pitch 6400 (/4 1600)
>[ 31431.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f49240]
>[ 31431.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f49240] width 1600 pitch 6400 (/4 1600)
>[ 31431.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22ca2c0]
>[ 31431.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22ca2c0] width 1600 pitch 6400 (/4 1600)
>[ 31431.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc0660]
>[ 31431.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc0660] width 1600 pitch 6400 (/4 1600)
>[ 31431.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460]
>[ 31431.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1600 pitch 6400 (/4 1600)
>[ 31431.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f5520]
>[ 31431.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f5520] width 1600 pitch 6400 (/4 1600)
>[ 31431.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc0660]
>[ 31432.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc0660] width 1600 pitch 6400 (/4 1600)
>[ 31432.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1000]
>[ 31432.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1000] width 1600 pitch 6400 (/4 1600)
>[ 31432.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db7460]
>[ 31432.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db7460] width 1600 pitch 6400 (/4 1600)
>[ 31432.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dc9860]
>[ 31432.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dc9860] width 1600 pitch 6400 (/4 1600)
>[ 31432.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dba100]
>[ 31432.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dba100] width 1600 pitch 6400 (/4 1600)
>[ 31432.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20f5520]
>[ 31432.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20f5520] width 1600 pitch 6400 (/4 1600)
>[ 31677.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d89ce0]
>[ 31677.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d89ce0] width 1600 pitch 6400 (/4 1600)
>[ 31677.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d89ce0]
>[ 31677.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d89ce0] width 1600 pitch 6400 (/4 1600)
>[ 31678.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d95650]
>[ 31678.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d95650] width 1600 pitch 6400 (/4 1600)
>[ 31678.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fa4d0]
>[ 31678.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fa4d0] width 1600 pitch 6400 (/4 1600)
>[ 31696.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fc2a0]
>[ 31696.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fc2a0] width 1600 pitch 6400 (/4 1600)
>[ 31696.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20fc2a0]
>[ 31696.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20fc2a0] width 1600 pitch 6400 (/4 1600)
>[ 31748.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d420]
>[ 31748.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d420] width 1600 pitch 6400 (/4 1600)
>[ 31748.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d98640]
>[ 31748.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d98640] width 1600 pitch 6400 (/4 1600)
>[ 31765.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f4d420]
>[ 31765.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f4d420] width 1600 pitch 6400 (/4 1600)
>[ 31765.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d98640]
>[ 31765.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d98640] width 1600 pitch 6400 (/4 1600)
>[ 31854.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f51c20]
>[ 31854.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f51c20] width 1600 pitch 6400 (/4 1600)
>[ 31856.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f56ca0]
>[ 31856.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f56ca0] width 1600 pitch 6400 (/4 1600)
>[ 32028.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0a980]
>[ 32028.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0a980] width 1600 pitch 6400 (/4 1600)
>[ 32028.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d82490]
>[ 32028.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d82490] width 1600 pitch 6400 (/4 1600)
>[ 32108.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f8cd20]
>[ 32108.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f8cd20] width 1600 pitch 6400 (/4 1600)
>[ 32108.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f60690]
>[ 32108.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f60690] width 1600 pitch 6400 (/4 1600)
>[ 32121.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db0030]
>[ 32122.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db0030] width 1600 pitch 6400 (/4 1600)
>[ 32122.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f89a60]
>[ 32122.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f89a60] width 1600 pitch 6400 (/4 1600)
>[ 32287.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb9360]
>[ 32287.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb9360] width 1600 pitch 6400 (/4 1600)
>[ 32287.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fbaf40]
>[ 32287.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fbaf40] width 1600 pitch 6400 (/4 1600)
>[ 32288.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fb95c0]
>[ 32288.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fb95c0] width 1600 pitch 6400 (/4 1600)
>[ 32526.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fcbb50]
>[ 32526.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fcbb50] width 1600 pitch 6400 (/4 1600)
>[ 32526.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd7100]
>[ 32526.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd7100] width 1600 pitch 6400 (/4 1600)
>[ 32780.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32780.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32784.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2010d30]
>[ 32784.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2010d30] width 1600 pitch 6400 (/4 1600)
>[ 32792.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32792.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32792.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32792.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32796.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2010250]
>[ 32796.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2010250] width 1600 pitch 6400 (/4 1600)
>[ 32796.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32796.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32796.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32796.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32796.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2010250]
>[ 32796.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2010250] width 1600 pitch 6400 (/4 1600)
>[ 32796.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32796.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32796.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2010250]
>[ 32796.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2010250] width 1600 pitch 6400 (/4 1600)
>[ 32796.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32796.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32796.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2010250]
>[ 32796.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2010250] width 1600 pitch 6400 (/4 1600)
>[ 32796.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32796.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32796.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2010250]
>[ 32796.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2010250] width 1600 pitch 6400 (/4 1600)
>[ 32798.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32798.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32798.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32798.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32798.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32798.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32798.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331f2a0]
>[ 32798.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331f2a0] width 1600 pitch 6400 (/4 1600)
>[ 32798.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32798.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32798.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331f2a0]
>[ 32798.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331f2a0] width 1600 pitch 6400 (/4 1600)
>[ 32798.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32798.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32798.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331f2a0]
>[ 32798.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331f2a0] width 1600 pitch 6400 (/4 1600)
>[ 32798.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32798.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32798.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331f2a0]
>[ 32798.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331f2a0] width 1600 pitch 6400 (/4 1600)
>[ 32798.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32798.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32798.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32798.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32798.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32798.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32798.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32798.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32798.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32798.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32798.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32798.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32798.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331f2a0]
>[ 32798.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331f2a0] width 1600 pitch 6400 (/4 1600)
>[ 32798.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32798.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32798.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331f2a0]
>[ 32798.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331f2a0] width 1600 pitch 6400 (/4 1600)
>[ 32798.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32798.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32798.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32798.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32798.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32798.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32798.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32798.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32800.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32800.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32800.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32800.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32800.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32800.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32800.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32800.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32800.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32800.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32800.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32800.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32800.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32800.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32800.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff42a0]
>[ 32800.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff42a0] width 1600 pitch 6400 (/4 1600)
>[ 32800.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32800.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32800.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32801.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32801.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32801.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32801.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32801.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32801.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32801.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32801.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff42a0]
>[ 32802.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff42a0] width 1600 pitch 6400 (/4 1600)
>[ 32802.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32802.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32802.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32802.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32802.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32802.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32804.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32804.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32804.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32804.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32804.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32804.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32804.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da8160]
>[ 32804.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da8160] width 1600 pitch 6400 (/4 1600)
>[ 32804.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff42a0]
>[ 32804.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff42a0] width 1600 pitch 6400 (/4 1600)
>[ 32804.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32804.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32804.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32804.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32804.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32804.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32811.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff42a0]
>[ 32811.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff42a0] width 1600 pitch 6400 (/4 1600)
>[ 32811.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32811.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32811.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32811.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32811.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32811.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32811.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da8160]
>[ 32811.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da8160] width 1600 pitch 6400 (/4 1600)
>[ 32811.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32811.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32811.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32812.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32812.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32812.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32812.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da8160]
>[ 32812.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da8160] width 1600 pitch 6400 (/4 1600)
>[ 32812.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2001980]
>[ 32812.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2001980] width 1600 pitch 6400 (/4 1600)
>[ 32812.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32812.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32812.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fd2390]
>[ 32812.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fd2390] width 1600 pitch 6400 (/4 1600)
>[ 32812.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32812.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32812.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ff42a0]
>[ 32812.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ff42a0] width 1600 pitch 6400 (/4 1600)
>[ 32812.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2b90]
>[ 32812.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2b90] width 1600 pitch 6400 (/4 1600)
>[ 32812.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1da8160]
>[ 32812.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1da8160] width 1600 pitch 6400 (/4 1600)
>[ 32813.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fe7f00]
>[ 32813.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fe7f00] width 1600 pitch 6400 (/4 1600)
>[ 32817.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c0cee0]
>[ 32817.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c0cee0] width 1600 pitch 6400 (/4 1600)
>[ 32818.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcb950]
>[ 32818.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcb950] width 1600 pitch 6400 (/4 1600)
>[ 32818.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76510]
>[ 32818.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76510] width 1600 pitch 6400 (/4 1600)
>[ 32819.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24eb540]
>[ 32819.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24eb540] width 1600 pitch 6400 (/4 1600)
>[ 32819.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76510]
>[ 32819.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76510] width 1600 pitch 6400 (/4 1600)
>[ 32819.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2372dc0]
>[ 32819.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2372dc0] width 1600 pitch 6400 (/4 1600)
>[ 32819.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1efbbe0]
>[ 32819.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1efbbe0] width 1600 pitch 6400 (/4 1600)
>[ 32819.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76510]
>[ 32819.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76510] width 1600 pitch 6400 (/4 1600)
>[ 32819.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcb950]
>[ 32819.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcb950] width 1600 pitch 6400 (/4 1600)
>[ 32819.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e76510]
>[ 32819.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e76510] width 1600 pitch 6400 (/4 1600)
>[ 32819.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1df9310]
>[ 32819.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1df9310] width 1600 pitch 6400 (/4 1600)
>[ 32819.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0ef30]
>[ 32819.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0ef30] width 1600 pitch 6400 (/4 1600)
>[ 32820.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0ef30]
>[ 32820.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0ef30] width 1600 pitch 6400 (/4 1600)
>[ 32820.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcb950]
>[ 32820.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcb950] width 1600 pitch 6400 (/4 1600)
>[ 32820.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2265960]
>[ 32820.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2265960] width 1600 pitch 6400 (/4 1600)
>[ 32820.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ffb790]
>[ 32820.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ffb790] width 1600 pitch 6400 (/4 1600)
>[ 32820.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcb950]
>[ 32820.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcb950] width 1600 pitch 6400 (/4 1600)
>[ 32820.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fec510]
>[ 32820.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fec510] width 1600 pitch 6400 (/4 1600)
>[ 32820.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32381a0]
>[ 32820.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32381a0] width 1600 pitch 6400 (/4 1600)
>[ 32820.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fec510]
>[ 32820.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fec510] width 1600 pitch 6400 (/4 1600)
>[ 33028.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5b30]
>[ 33028.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5b30] width 1600 pitch 6400 (/4 1600)
>[ 33028.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e741c0]
>[ 33028.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e741c0] width 1600 pitch 6400 (/4 1600)
>[ 33053.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f2180]
>[ 33053.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f2180] width 1600 pitch 6400 (/4 1600)
>[ 33054.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71f00]
>[ 33054.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71f00] width 1600 pitch 6400 (/4 1600)
>[ 33054.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20037e0]
>[ 33054.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20037e0] width 1600 pitch 6400 (/4 1600)
>[ 33054.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6fcd0]
>[ 33054.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6fcd0] width 1600 pitch 6400 (/4 1600)
>[ 33054.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71f00]
>[ 33054.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71f00] width 1600 pitch 6400 (/4 1600)
>[ 33054.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20037e0]
>[ 33054.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20037e0] width 1600 pitch 6400 (/4 1600)
>[ 33054.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e6fcd0]
>[ 33054.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e6fcd0] width 1600 pitch 6400 (/4 1600)
>[ 33054.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71f00]
>[ 33054.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71f00] width 1600 pitch 6400 (/4 1600)
>[ 33055.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e71f00]
>[ 33055.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e71f00] width 1600 pitch 6400 (/4 1600)
>[ 33055.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f480]
>[ 33055.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f480] width 1600 pitch 6400 (/4 1600)
>[ 33055.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c2f480]
>[ 33055.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c2f480] width 1600 pitch 6400 (/4 1600)
>[ 33059.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20037e0]
>[ 33059.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20037e0] width 1600 pitch 6400 (/4 1600)
>[ 33060.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eed770]
>[ 33060.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eed770] width 1600 pitch 6400 (/4 1600)
>[ 33060.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eeedf0]
>[ 33060.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eeedf0] width 1600 pitch 6400 (/4 1600)
>[ 33071.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eef260]
>[ 33071.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eef260] width 1600 pitch 6400 (/4 1600)
>[ 33071.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ee360]
>[ 33071.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ee360] width 1600 pitch 6400 (/4 1600)
>[ 33071.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dc5f0]
>[ 33071.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dc5f0] width 1600 pitch 6400 (/4 1600)
>[ 33071.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ee360]
>[ 33071.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ee360] width 1600 pitch 6400 (/4 1600)
>[ 33071.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dc5f0]
>[ 33071.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dc5f0] width 1600 pitch 6400 (/4 1600)
>[ 33071.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e73df0]
>[ 33071.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e73df0] width 1600 pitch 6400 (/4 1600)
>[ 33071.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dc5f0]
>[ 33071.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dc5f0] width 1600 pitch 6400 (/4 1600)
>[ 33071.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e73df0]
>[ 33071.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e73df0] width 1600 pitch 6400 (/4 1600)
>[ 33071.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eeee30]
>[ 33071.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eeee30] width 1600 pitch 6400 (/4 1600)
>[ 33071.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e73df0]
>[ 33071.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e73df0] width 1600 pitch 6400 (/4 1600)
>[ 33071.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eef260]
>[ 33071.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eef260] width 1600 pitch 6400 (/4 1600)
>[ 33071.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e73df0]
>[ 33071.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e73df0] width 1600 pitch 6400 (/4 1600)
>[ 33071.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eef260]
>[ 33071.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eef260] width 1600 pitch 6400 (/4 1600)
>[ 33071.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dc5f0]
>[ 33071.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dc5f0] width 1600 pitch 6400 (/4 1600)
>[ 33071.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3356120]
>[ 33071.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3356120] width 1600 pitch 6400 (/4 1600)
>[ 33072.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eed270]
>[ 33072.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eed270] width 1600 pitch 6400 (/4 1600)
>[ 33072.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587af0]
>[ 33072.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587af0] width 1600 pitch 6400 (/4 1600)
>[ 33072.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eeee90]
>[ 33072.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eeee90] width 1600 pitch 6400 (/4 1600)
>[ 33072.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587a90]
>[ 33072.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587a90] width 1600 pitch 6400 (/4 1600)
>[ 33072.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eed2a0]
>[ 33072.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eed2a0] width 1600 pitch 6400 (/4 1600)
>[ 33072.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587a90]
>[ 33072.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587a90] width 1600 pitch 6400 (/4 1600)
>[ 33072.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587af0]
>[ 33072.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587af0] width 1600 pitch 6400 (/4 1600)
>[ 33072.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eed2d0]
>[ 33072.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eed2d0] width 1600 pitch 6400 (/4 1600)
>[ 33072.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eeeec0]
>[ 33072.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eeeec0] width 1600 pitch 6400 (/4 1600)
>[ 33072.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587a90]
>[ 33072.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587a90] width 1600 pitch 6400 (/4 1600)
>[ 33072.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d3f0]
>[ 33072.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d3f0] width 1600 pitch 6400 (/4 1600)
>[ 33072.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587a90]
>[ 33072.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587a90] width 1600 pitch 6400 (/4 1600)
>[ 33072.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d60b0]
>[ 33072.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d60b0] width 1600 pitch 6400 (/4 1600)
>[ 33079.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dc5f0]
>[ 33079.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dc5f0] width 1600 pitch 6400 (/4 1600)
>[ 33099.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ddff0]
>[ 33100.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ddff0] width 1600 pitch 6400 (/4 1600)
>[ 33100.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7010]
>[ 33100.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7010] width 1600 pitch 6400 (/4 1600)
>[ 33100.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ddff0]
>[ 33100.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ddff0] width 1600 pitch 6400 (/4 1600)
>[ 33100.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ddff0]
>[ 33100.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ddff0] width 1600 pitch 6400 (/4 1600)
>[ 33100.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ee960]
>[ 33100.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ee960] width 1600 pitch 6400 (/4 1600)
>[ 33100.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dc5f0]
>[ 33100.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dc5f0] width 1600 pitch 6400 (/4 1600)
>[ 33100.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20ee960]
>[ 33100.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20ee960] width 1600 pitch 6400 (/4 1600)
>[ 33100.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33100.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33100.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c33b0]
>[ 33100.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c33b0] width 1600 pitch 6400 (/4 1600)
>[ 33100.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f3e60]
>[ 33100.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f3e60] width 1600 pitch 6400 (/4 1600)
>[ 33100.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c33b0]
>[ 33100.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c33b0] width 1600 pitch 6400 (/4 1600)
>[ 33100.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33100.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33100.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dc5f0]
>[ 33100.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dc5f0] width 1600 pitch 6400 (/4 1600)
>[ 33100.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33100.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33100.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3332a50]
>[ 33100.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3332a50] width 1600 pitch 6400 (/4 1600)
>[ 33101.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332d500]
>[ 33101.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332d500] width 1600 pitch 6400 (/4 1600)
>[ 33101.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332cfe0]
>[ 33101.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332cfe0] width 1600 pitch 6400 (/4 1600)
>[ 33101.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33101.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33101.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332d500]
>[ 33101.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332d500] width 1600 pitch 6400 (/4 1600)
>[ 33101.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c33b0]
>[ 33101.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c33b0] width 1600 pitch 6400 (/4 1600)
>[ 33101.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332d500]
>[ 33101.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332d500] width 1600 pitch 6400 (/4 1600)
>[ 33101.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c33b0]
>[ 33101.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c33b0] width 1600 pitch 6400 (/4 1600)
>[ 33101.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dc5f0]
>[ 33101.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dc5f0] width 1600 pitch 6400 (/4 1600)
>[ 33102.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3355be0]
>[ 33102.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3355be0] width 1600 pitch 6400 (/4 1600)
>[ 33102.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3355c40]
>[ 33102.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3355c40] width 1600 pitch 6400 (/4 1600)
>[ 33102.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33538a0]
>[ 33102.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33538a0] width 1600 pitch 6400 (/4 1600)
>[ 33102.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3355c40]
>[ 33102.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3355c40] width 1600 pitch 6400 (/4 1600)
>[ 33102.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3355c40]
>[ 33102.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3355c40] width 1600 pitch 6400 (/4 1600)
>[ 33102.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33102.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33102.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3355c40]
>[ 33102.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3355c40] width 1600 pitch 6400 (/4 1600)
>[ 33102.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33102.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33102.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332cfe0]
>[ 33102.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332cfe0] width 1600 pitch 6400 (/4 1600)
>[ 33102.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33102.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33102.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332cfe0]
>[ 33102.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332cfe0] width 1600 pitch 6400 (/4 1600)
>[ 33102.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33102.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33102.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332cfe0]
>[ 33102.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332cfe0] width 1600 pitch 6400 (/4 1600)
>[ 33102.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200d870]
>[ 33102.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200d870] width 1600 pitch 6400 (/4 1600)
>[ 33102.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f3e60]
>[ 33102.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f3e60] width 1600 pitch 6400 (/4 1600)
>[ 33102.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3343ca0]
>[ 33102.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3343ca0] width 1600 pitch 6400 (/4 1600)
>[ 33103.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33490a0]
>[ 33103.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33490a0] width 1600 pitch 6400 (/4 1600)
>[ 33103.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a280]
>[ 33103.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a280] width 1600 pitch 6400 (/4 1600)
>[ 33103.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33490a0]
>[ 33103.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33490a0] width 1600 pitch 6400 (/4 1600)
>[ 33103.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a280]
>[ 33103.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a280] width 1600 pitch 6400 (/4 1600)
>[ 33103.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33490a0]
>[ 33103.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33490a0] width 1600 pitch 6400 (/4 1600)
>[ 33103.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a280]
>[ 33103.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a280] width 1600 pitch 6400 (/4 1600)
>[ 33103.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33490a0]
>[ 33103.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33490a0] width 1600 pitch 6400 (/4 1600)
>[ 33103.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a280]
>[ 33103.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a280] width 1600 pitch 6400 (/4 1600)
>[ 33103.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a280]
>[ 33103.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a280] width 1600 pitch 6400 (/4 1600)
>[ 33103.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3343ca0]
>[ 33103.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3343ca0] width 1600 pitch 6400 (/4 1600)
>[ 33103.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a280]
>[ 33103.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a280] width 1600 pitch 6400 (/4 1600)
>[ 33103.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3343ca0]
>[ 33103.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3343ca0] width 1600 pitch 6400 (/4 1600)
>[ 33121.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2590e90]
>[ 33121.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2590e90] width 1600 pitch 6400 (/4 1600)
>[ 33122.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2590e10]
>[ 33122.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2590e10] width 1600 pitch 6400 (/4 1600)
>[ 33123.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0560]
>[ 33123.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0560] width 1600 pitch 6400 (/4 1600)
>[ 33123.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c04e0]
>[ 33123.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c04e0] width 1600 pitch 6400 (/4 1600)
>[ 33141.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3295360]
>[ 33141.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3295360] width 1600 pitch 6400 (/4 1600)
>[ 33551.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335ca70]
>[ 33551.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335ca70] width 1600 pitch 6400 (/4 1600)
>[ 33551.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a710]
>[ 33551.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a710] width 1600 pitch 6400 (/4 1600)
>[ 33551.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3375050]
>[ 33551.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3375050] width 1600 pitch 6400 (/4 1600)
>[ 33552.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a170]
>[ 33552.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a170] width 1600 pitch 6400 (/4 1600)
>[ 33552.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332cfe0]
>[ 33552.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332cfe0] width 1600 pitch 6400 (/4 1600)
>[ 33552.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33541a0]
>[ 33552.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33541a0] width 1600 pitch 6400 (/4 1600)
>[ 33552.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357aa0]
>[ 33552.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357aa0] width 1600 pitch 6400 (/4 1600)
>[ 33553.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336cd40]
>[ 33553.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336cd40] width 1600 pitch 6400 (/4 1600)
>[ 33553.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341ab90]
>[ 33554.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341ab90] width 1600 pitch 6400 (/4 1600)
>[ 33554.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34080b0]
>[ 33554.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34080b0] width 1600 pitch 6400 (/4 1600)
>[ 33554.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357aa0]
>[ 33554.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357aa0] width 1600 pitch 6400 (/4 1600)
>[ 33554.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3418690]
>[ 33554.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3418690] width 1600 pitch 6400 (/4 1600)
>[ 33554.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a820]
>[ 33554.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a820] width 1600 pitch 6400 (/4 1600)
>[ 33555.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33490a0]
>[ 33555.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33490a0] width 1600 pitch 6400 (/4 1600)
>[ 33555.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334a170]
>[ 33555.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334a170] width 1600 pitch 6400 (/4 1600)
>[ 33555.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374d40]
>[ 33555.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374d40] width 1600 pitch 6400 (/4 1600)
>[ 33555.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ffffc0]
>[ 33555.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ffffc0] width 1600 pitch 6400 (/4 1600)
>[ 33555.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336da20]
>[ 33555.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336da20] width 1600 pitch 6400 (/4 1600)
>[ 33555.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eee720]
>[ 33555.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eee720] width 1600 pitch 6400 (/4 1600)
>[ 33563.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f35a0]
>[ 33563.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f35a0] width 1600 pitch 6400 (/4 1600)
>[ 33563.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3375370]
>[ 33563.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3375370] width 1600 pitch 6400 (/4 1600)
>[ 33571.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33571.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33571.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3375370]
>[ 33571.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3375370] width 1600 pitch 6400 (/4 1600)
>[ 33571.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e810]
>[ 33571.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e810] width 1600 pitch 6400 (/4 1600)
>[ 33571.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34237c0]
>[ 33571.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34237c0] width 1600 pitch 6400 (/4 1600)
>[ 33571.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e810]
>[ 33571.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e810] width 1600 pitch 6400 (/4 1600)
>[ 33571.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33571.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33571.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e810]
>[ 33571.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e810] width 1600 pitch 6400 (/4 1600)
>[ 33571.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33571.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33571.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34237c0]
>[ 33571.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34237c0] width 1600 pitch 6400 (/4 1600)
>[ 33571.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e810]
>[ 33571.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e810] width 1600 pitch 6400 (/4 1600)
>[ 33572.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3375370]
>[ 33572.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3375370] width 1600 pitch 6400 (/4 1600)
>[ 33572.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e810]
>[ 33572.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e810] width 1600 pitch 6400 (/4 1600)
>[ 33572.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33572.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33572.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e810]
>[ 33572.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e810] width 1600 pitch 6400 (/4 1600)
>[ 33572.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33572.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33572.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33754c0]
>[ 33572.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33754c0] width 1600 pitch 6400 (/4 1600)
>[ 33572.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33572.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33572.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33754c0]
>[ 33572.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33754c0] width 1600 pitch 6400 (/4 1600)
>[ 33572.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33572.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33572.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3375370]
>[ 33572.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3375370] width 1600 pitch 6400 (/4 1600)
>[ 33572.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e810]
>[ 33572.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e810] width 1600 pitch 6400 (/4 1600)
>[ 33572.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33572.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33572.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33572.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33572.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33754c0]
>[ 33572.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33754c0] width 1600 pitch 6400 (/4 1600)
>[ 33572.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33572.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33572.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33754c0]
>[ 33572.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33754c0] width 1600 pitch 6400 (/4 1600)
>[ 33572.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33572.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33572.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3375370]
>[ 33572.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3375370] width 1600 pitch 6400 (/4 1600)
>[ 33572.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33572.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33572.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34237c0]
>[ 33572.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34237c0] width 1600 pitch 6400 (/4 1600)
>[ 33572.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33572.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33572.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33572.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33573.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33573.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33575.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c33b0]
>[ 33575.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c33b0] width 1600 pitch 6400 (/4 1600)
>[ 33576.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357aa0]
>[ 33576.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357aa0] width 1600 pitch 6400 (/4 1600)
>[ 33576.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33576.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33576.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335ca70]
>[ 33576.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335ca70] width 1600 pitch 6400 (/4 1600)
>[ 33576.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33577.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33577.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335ca70]
>[ 33577.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335ca70] width 1600 pitch 6400 (/4 1600)
>[ 33577.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33577.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33577.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3354000]
>[ 33577.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3354000] width 1600 pitch 6400 (/4 1600)
>[ 33577.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337adb0]
>[ 33577.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337adb0] width 1600 pitch 6400 (/4 1600)
>[ 33577.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337a320]
>[ 33577.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337a320] width 1600 pitch 6400 (/4 1600)
>[ 33577.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b710]
>[ 33577.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b710] width 1600 pitch 6400 (/4 1600)
>[ 33577.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33577.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 33577.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b710]
>[ 33577.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b710] width 1600 pitch 6400 (/4 1600)
>[ 33577.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d7d0]
>[ 33577.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d7d0] width 1600 pitch 6400 (/4 1600)
>[ 34623.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f340]
>[ 34623.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f340] width 1600 pitch 6400 (/4 1600)
>[ 34623.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea770]
>[ 34623.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea770] width 1600 pitch 6400 (/4 1600)
>[ 34623.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f340]
>[ 34623.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f340] width 1600 pitch 6400 (/4 1600)
>[ 34623.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea770]
>[ 34623.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea770] width 1600 pitch 6400 (/4 1600)
>[ 34623.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f340]
>[ 34623.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f340] width 1600 pitch 6400 (/4 1600)
>[ 34623.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3290920]
>[ 34623.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3290920] width 1600 pitch 6400 (/4 1600)
>[ 34623.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea770]
>[ 34623.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea770] width 1600 pitch 6400 (/4 1600)
>[ 34624.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323cd00]
>[ 34624.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323cd00] width 1600 pitch 6400 (/4 1600)
>[ 34624.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dee120]
>[ 34624.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dee120] width 1600 pitch 6400 (/4 1600)
>[ 34625.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326390]
>[ 34625.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326390] width 1600 pitch 6400 (/4 1600)
>[ 34625.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3331800]
>[ 34625.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3331800] width 1600 pitch 6400 (/4 1600)
>[ 34625.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f8c0]
>[ 34625.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f8c0] width 1600 pitch 6400 (/4 1600)
>[ 34625.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f7f0]
>[ 34625.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f7f0] width 1600 pitch 6400 (/4 1600)
>[ 34625.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f8c0]
>[ 34625.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f8c0] width 1600 pitch 6400 (/4 1600)
>[ 34625.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f7f0]
>[ 34625.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f7f0] width 1600 pitch 6400 (/4 1600)
>[ 34625.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f8c0]
>[ 34625.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f8c0] width 1600 pitch 6400 (/4 1600)
>[ 34625.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328f7f0]
>[ 34625.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328f7f0] width 1600 pitch 6400 (/4 1600)
>[ 34635.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333b960]
>[ 34635.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333b960] width 1600 pitch 6400 (/4 1600)
>[ 34635.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ee420]
>[ 34635.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ee420] width 1600 pitch 6400 (/4 1600)
>[ 34635.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ee3c0]
>[ 34635.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ee3c0] width 1600 pitch 6400 (/4 1600)
>[ 34635.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ee420]
>[ 34635.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ee420] width 1600 pitch 6400 (/4 1600)
>[ 34635.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ee3c0]
>[ 34635.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ee3c0] width 1600 pitch 6400 (/4 1600)
>[ 34635.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ee420]
>[ 34635.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ee420] width 1600 pitch 6400 (/4 1600)
>[ 34635.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348280]
>[ 34635.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348280] width 1600 pitch 6400 (/4 1600)
>[ 34635.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da810]
>[ 34635.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da810] width 1600 pitch 6400 (/4 1600)
>[ 34635.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348280]
>[ 34635.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348280] width 1600 pitch 6400 (/4 1600)
>[ 34635.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da810]
>[ 34635.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da810] width 1600 pitch 6400 (/4 1600)
>[ 34636.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339f3f0]
>[ 34636.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339f3f0] width 1600 pitch 6400 (/4 1600)
>[ 34637.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aff50]
>[ 34637.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aff50] width 1600 pitch 6400 (/4 1600)
>[ 34637.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339b4a0]
>[ 34637.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339b4a0] width 1600 pitch 6400 (/4 1600)
>[ 34637.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aff50]
>[ 34637.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aff50] width 1600 pitch 6400 (/4 1600)
>[ 34638.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348570]
>[ 34638.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348570] width 1600 pitch 6400 (/4 1600)
>[ 34638.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a6520]
>[ 34638.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a6520] width 1600 pitch 6400 (/4 1600)
>[ 34639.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aff50]
>[ 34639.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aff50] width 1600 pitch 6400 (/4 1600)
>[ 34639.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bbbf0]
>[ 34639.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bbbf0] width 1600 pitch 6400 (/4 1600)
>[ 34639.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2488fe0]
>[ 34639.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2488fe0] width 1600 pitch 6400 (/4 1600)
>[ 34639.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aff50]
>[ 34639.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aff50] width 1600 pitch 6400 (/4 1600)
>[ 34640.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aff50]
>[ 34640.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aff50] width 1600 pitch 6400 (/4 1600)
>[ 34640.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7340]
>[ 34640.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7340] width 1600 pitch 6400 (/4 1600)
>[ 34675.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 34675.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 34675.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2006970]
>[ 34675.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2006970] width 1600 pitch 6400 (/4 1600)
>[ 34675.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3354120]
>[ 34675.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3354120] width 1600 pitch 6400 (/4 1600)
>[ 34675.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2006970]
>[ 34675.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2006970] width 1600 pitch 6400 (/4 1600)
>[ 34675.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3354120]
>[ 34675.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3354120] width 1600 pitch 6400 (/4 1600)
>[ 34676.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2006970]
>[ 34676.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2006970] width 1600 pitch 6400 (/4 1600)
>[ 34676.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3354120]
>[ 34676.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3354120] width 1600 pitch 6400 (/4 1600)
>[ 34676.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2006970]
>[ 34676.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2006970] width 1600 pitch 6400 (/4 1600)
>[ 34676.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0a10]
>[ 34676.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0a10] width 1600 pitch 6400 (/4 1600)
>[ 34676.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2006970]
>[ 34676.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2006970] width 1600 pitch 6400 (/4 1600)
>[ 34677.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 34677.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 34677.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3354120]
>[ 34677.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3354120] width 1600 pitch 6400 (/4 1600)
>[ 34677.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336df10]
>[ 34677.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336df10] width 1600 pitch 6400 (/4 1600)
>[ 34677.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3354120]
>[ 34677.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3354120] width 1600 pitch 6400 (/4 1600)
>[ 34686.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 34687.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 34722.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 34722.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 34722.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e65e0]
>[ 34722.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e65e0] width 1600 pitch 6400 (/4 1600)
>[ 34722.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b040]
>[ 34722.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b040] width 1600 pitch 6400 (/4 1600)
>[ 34722.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 34722.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 34722.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b040]
>[ 34722.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b040] width 1600 pitch 6400 (/4 1600)
>[ 34722.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e65e0]
>[ 34723.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e65e0] width 1600 pitch 6400 (/4 1600)
>[ 34723.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 34723.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 34723.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b040]
>[ 34723.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b040] width 1600 pitch 6400 (/4 1600)
>[ 34723.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 34723.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 34723.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e65e0]
>[ 34723.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e65e0] width 1600 pitch 6400 (/4 1600)
>[ 34723.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b040]
>[ 34723.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b040] width 1600 pitch 6400 (/4 1600)
>[ 34723.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b040]
>[ 34724.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b040] width 1600 pitch 6400 (/4 1600)
>[ 34724.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200fea0]
>[ 34724.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200fea0] width 1600 pitch 6400 (/4 1600)
>[ 34724.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 34724.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 34727.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2557ae0]
>[ 34727.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2557ae0] width 1600 pitch 6400 (/4 1600)
>[ 34896.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7340]
>[ 34896.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7340] width 1600 pitch 6400 (/4 1600)
>[ 34896.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7340]
>[ 34896.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7340] width 1600 pitch 6400 (/4 1600)
>[ 34896.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e8080]
>[ 34896.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e8080] width 1600 pitch 6400 (/4 1600)
>[ 34896.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7340]
>[ 34897.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7340] width 1600 pitch 6400 (/4 1600)
>[ 34897.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbee90]
>[ 34897.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbee90] width 1600 pitch 6400 (/4 1600)
>[ 34897.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7340]
>[ 34897.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7340] width 1600 pitch 6400 (/4 1600)
>[ 34897.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e8080]
>[ 34897.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e8080] width 1600 pitch 6400 (/4 1600)
>[ 34898.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbee90]
>[ 34898.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbee90] width 1600 pitch 6400 (/4 1600)
>[ 34898.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e8080]
>[ 34898.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e8080] width 1600 pitch 6400 (/4 1600)
>[ 34898.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7340]
>[ 34899.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7340] width 1600 pitch 6400 (/4 1600)
>[ 34899.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbee90]
>[ 34899.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbee90] width 1600 pitch 6400 (/4 1600)
>[ 34899.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7340]
>[ 34899.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7340] width 1600 pitch 6400 (/4 1600)
>[ 34899.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dbee90]
>[ 34899.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dbee90] width 1600 pitch 6400 (/4 1600)
>[ 34899.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e8080]
>[ 34899.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e8080] width 1600 pitch 6400 (/4 1600)
>[ 34899.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7340]
>[ 34899.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7340] width 1600 pitch 6400 (/4 1600)
>[ 34920.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e8080]
>[ 34920.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e8080] width 1600 pitch 6400 (/4 1600)
>[ 34920.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ed770]
>[ 34920.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ed770] width 1600 pitch 6400 (/4 1600)
>[ 34971.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee530]
>[ 34971.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee530] width 1600 pitch 6400 (/4 1600)
>[ 34971.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee530]
>[ 34971.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee530] width 1600 pitch 6400 (/4 1600)
>[ 35207.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0420]
>[ 35207.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0420] width 1600 pitch 6400 (/4 1600)
>[ 35216.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0420]
>[ 35216.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0420] width 1600 pitch 6400 (/4 1600)
>[ 35216.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ee300]
>[ 35216.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ee300] width 1600 pitch 6400 (/4 1600)
>[ 35407.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ee300]
>[ 35407.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ee300] width 1600 pitch 6400 (/4 1600)
>[ 35491.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35491.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35491.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26816e0]
>[ 35491.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26816e0] width 1600 pitch 6400 (/4 1600)
>[ 35491.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35491.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35491.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35491.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35492.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684c10]
>[ 35492.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684c10] width 1600 pitch 6400 (/4 1600)
>[ 35492.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35492.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35492.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26816e0]
>[ 35492.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26816e0] width 1600 pitch 6400 (/4 1600)
>[ 35493.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684c10]
>[ 35493.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684c10] width 1600 pitch 6400 (/4 1600)
>[ 35493.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684c10]
>[ 35493.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684c10] width 1600 pitch 6400 (/4 1600)
>[ 35493.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26816e0]
>[ 35493.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26816e0] width 1600 pitch 6400 (/4 1600)
>[ 35493.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26816e0]
>[ 35493.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26816e0] width 1600 pitch 6400 (/4 1600)
>[ 35494.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c0c50]
>[ 35494.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c0c50] width 1600 pitch 6400 (/4 1600)
>[ 35495.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c0c50]
>[ 35495.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c0c50] width 1600 pitch 6400 (/4 1600)
>[ 35495.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268b580]
>[ 35495.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268b580] width 1600 pitch 6400 (/4 1600)
>[ 35495.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26816e0]
>[ 35495.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26816e0] width 1600 pitch 6400 (/4 1600)
>[ 35495.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684c10]
>[ 35495.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684c10] width 1600 pitch 6400 (/4 1600)
>[ 35495.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c0c50]
>[ 35495.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c0c50] width 1600 pitch 6400 (/4 1600)
>[ 35495.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684c10]
>[ 35495.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684c10] width 1600 pitch 6400 (/4 1600)
>[ 35587.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25831e0]
>[ 35587.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25831e0] width 1600 pitch 6400 (/4 1600)
>[ 35587.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22b6110]
>[ 35587.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22b6110] width 1600 pitch 6400 (/4 1600)
>[ 35587.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25831e0]
>[ 35587.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25831e0] width 1600 pitch 6400 (/4 1600)
>[ 35587.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e6a60]
>[ 35587.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e6a60] width 1600 pitch 6400 (/4 1600)
>[ 35588.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25831e0]
>[ 35588.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25831e0] width 1600 pitch 6400 (/4 1600)
>[ 35588.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e6a60]
>[ 35588.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e6a60] width 1600 pitch 6400 (/4 1600)
>[ 35588.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25831e0]
>[ 35588.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25831e0] width 1600 pitch 6400 (/4 1600)
>[ 35588.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21e6a60]
>[ 35588.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21e6a60] width 1600 pitch 6400 (/4 1600)
>[ 35588.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1be5e00]
>[ 35588.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1be5e00] width 1600 pitch 6400 (/4 1600)
>[ 35588.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35588.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35588.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d9880]
>[ 35589.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d9880] width 1600 pitch 6400 (/4 1600)
>[ 35589.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35589.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35590.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d9880]
>[ 35590.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d9880] width 1600 pitch 6400 (/4 1600)
>[ 35590.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e832e0]
>[ 35590.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e832e0] width 1600 pitch 6400 (/4 1600)
>[ 35590.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddf3c0]
>[ 35590.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddf3c0] width 1600 pitch 6400 (/4 1600)
>[ 35590.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e832e0]
>[ 35590.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e832e0] width 1600 pitch 6400 (/4 1600)
>[ 35592.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22585d0]
>[ 35592.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22585d0] width 1600 pitch 6400 (/4 1600)
>[ 35596.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22585d0]
>[ 35596.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22585d0] width 1600 pitch 6400 (/4 1600)
>[ 35597.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d9880]
>[ 35597.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d9880] width 1600 pitch 6400 (/4 1600)
>[ 35597.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d05980]
>[ 35597.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d05980] width 1600 pitch 6400 (/4 1600)
>[ 35597.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d9880]
>[ 35597.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d9880] width 1600 pitch 6400 (/4 1600)
>[ 35597.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d05980]
>[ 35597.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d05980] width 1600 pitch 6400 (/4 1600)
>[ 35597.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d9880]
>[ 35597.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d9880] width 1600 pitch 6400 (/4 1600)
>[ 35597.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d05980]
>[ 35597.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d05980] width 1600 pitch 6400 (/4 1600)
>[ 35597.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d9880]
>[ 35597.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d9880] width 1600 pitch 6400 (/4 1600)
>[ 35599.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0420]
>[ 35599.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0420] width 1600 pitch 6400 (/4 1600)
>[ 35599.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35599.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35599.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0420]
>[ 35599.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0420] width 1600 pitch 6400 (/4 1600)
>[ 35599.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35599.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35599.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0420]
>[ 35599.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0420] width 1600 pitch 6400 (/4 1600)
>[ 35599.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35599.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35599.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0420]
>[ 35599.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0420] width 1600 pitch 6400 (/4 1600)
>[ 35600.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2298730]
>[ 35600.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2298730] width 1600 pitch 6400 (/4 1600)
>[ 35692.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2243060]
>[ 35692.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2243060] width 1600 pitch 6400 (/4 1600)
>[ 35695.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1db4000]
>[ 35695.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1db4000] width 1600 pitch 6400 (/4 1600)
>[ 35696.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60a20]
>[ 35696.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60a20] width 1600 pitch 6400 (/4 1600)
>[ 35696.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c9f70]
>[ 35696.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c9f70] width 1600 pitch 6400 (/4 1600)
>[ 35696.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60a20]
>[ 35696.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60a20] width 1600 pitch 6400 (/4 1600)
>[ 35696.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c9f70]
>[ 35696.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c9f70] width 1600 pitch 6400 (/4 1600)
>[ 35696.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60a20]
>[ 35696.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60a20] width 1600 pitch 6400 (/4 1600)
>[ 35696.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22c9f70]
>[ 35696.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22c9f70] width 1600 pitch 6400 (/4 1600)
>[ 35696.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60a20]
>[ 35696.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60a20] width 1600 pitch 6400 (/4 1600)
>[ 35697.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25da670]
>[ 35697.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25da670] width 1600 pitch 6400 (/4 1600)
>[ 35697.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d60a20]
>[ 35697.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d60a20] width 1600 pitch 6400 (/4 1600)
>[ 35697.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25da670]
>[ 35697.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25da670] width 1600 pitch 6400 (/4 1600)
>[ 35698.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20e9540]
>[ 35698.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20e9540] width 1600 pitch 6400 (/4 1600)
>[ 35699.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23cb3b0]
>[ 35699.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23cb3b0] width 1600 pitch 6400 (/4 1600)
>[ 35699.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2104be0]
>[ 35699.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2104be0] width 1600 pitch 6400 (/4 1600)
>[ 35699.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4adb0]
>[ 35699.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4adb0] width 1600 pitch 6400 (/4 1600)
>[ 35699.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2104be0]
>[ 35699.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2104be0] width 1600 pitch 6400 (/4 1600)
>[ 35699.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d4adb0]
>[ 35699.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d4adb0] width 1600 pitch 6400 (/4 1600)
>[ 35699.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2104be0]
>[ 35699.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2104be0] width 1600 pitch 6400 (/4 1600)
>[ 35699.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a47f0]
>[ 35699.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a47f0] width 1600 pitch 6400 (/4 1600)
>[ 35699.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fc57f0]
>[ 35699.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fc57f0] width 1600 pitch 6400 (/4 1600)
>[ 35699.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a47f0]
>[ 35699.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a47f0] width 1600 pitch 6400 (/4 1600)
>[ 35699.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22baa90]
>[ 35699.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22baa90] width 1600 pitch 6400 (/4 1600)
>[ 35699.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f94810]
>[ 35700.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f94810] width 1600 pitch 6400 (/4 1600)
>[ 35700.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22baa90]
>[ 35700.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22baa90] width 1600 pitch 6400 (/4 1600)
>[ 35700.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f94810]
>[ 35700.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f94810] width 1600 pitch 6400 (/4 1600)
>[ 35700.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22baa90]
>[ 35700.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22baa90] width 1600 pitch 6400 (/4 1600)
>[ 35700.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25831e0]
>[ 35700.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25831e0] width 1600 pitch 6400 (/4 1600)
>[ 35701.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c194c0]
>[ 35701.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c194c0] width 1600 pitch 6400 (/4 1600)
>[ 35701.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25831e0]
>[ 35701.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25831e0] width 1600 pitch 6400 (/4 1600)
>[ 35701.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c194c0]
>[ 35701.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c194c0] width 1600 pitch 6400 (/4 1600)
>[ 35701.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x229f830]
>[ 35701.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x229f830] width 1600 pitch 6400 (/4 1600)
>[ 35702.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a1f0]
>[ 35702.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a1f0] width 1600 pitch 6400 (/4 1600)
>[ 35702.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x22585d0]
>[ 35702.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x22585d0] width 1600 pitch 6400 (/4 1600)
>[ 35702.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0420]
>[ 35702.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0420] width 1600 pitch 6400 (/4 1600)
>[ 35702.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1fa0800]
>[ 35702.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1fa0800] width 1600 pitch 6400 (/4 1600)
>[ 35702.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f138b0]
>[ 35702.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f138b0] width 1600 pitch 6400 (/4 1600)
>[ 35702.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e73df0]
>[ 35702.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e73df0] width 1600 pitch 6400 (/4 1600)
>[ 35702.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f138b0]
>[ 35703.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f138b0] width 1600 pitch 6400 (/4 1600)
>[ 35703.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e73df0]
>[ 35703.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e73df0] width 1600 pitch 6400 (/4 1600)
>[ 35703.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f138b0]
>[ 35703.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f138b0] width 1600 pitch 6400 (/4 1600)
>[ 35703.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e73df0]
>[ 35703.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e73df0] width 1600 pitch 6400 (/4 1600)
>[ 35703.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f138b0]
>[ 35703.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f138b0] width 1600 pitch 6400 (/4 1600)
>[ 35703.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddf3c0]
>[ 35703.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddf3c0] width 1600 pitch 6400 (/4 1600)
>[ 35716.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2104be0]
>[ 35716.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2104be0] width 1600 pitch 6400 (/4 1600)
>[ 35797.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e81b40]
>[ 35797.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e81b40] width 1600 pitch 6400 (/4 1600)
>[ 35797.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21722c0]
>[ 35797.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21722c0] width 1600 pitch 6400 (/4 1600)
>[ 35799.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2f580]
>[ 35799.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2f580] width 1600 pitch 6400 (/4 1600)
>[ 35802.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21fc490]
>[ 35802.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21fc490] width 1600 pitch 6400 (/4 1600)
>[ 35802.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cf48d0]
>[ 35802.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cf48d0] width 1600 pitch 6400 (/4 1600)
>[ 35802.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x21040d0]
>[ 35802.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x21040d0] width 1600 pitch 6400 (/4 1600)
>[ 35803.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259e950]
>[ 35803.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259e950] width 1600 pitch 6400 (/4 1600)
>[ 35803.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2453180]
>[ 35803.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2453180] width 1600 pitch 6400 (/4 1600)
>[ 35803.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c3730]
>[ 35803.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c3730] width 1600 pitch 6400 (/4 1600)
>[ 35803.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c24e80]
>[ 35803.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c24e80] width 1600 pitch 6400 (/4 1600)
>[ 35803.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2f580]
>[ 35803.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2f580] width 1600 pitch 6400 (/4 1600)
>[ 35803.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x23c3730]
>[ 35803.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x23c3730] width 1600 pitch 6400 (/4 1600)
>[ 35804.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dcfe00]
>[ 35804.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dcfe00] width 1600 pitch 6400 (/4 1600)
>[ 35804.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cce60]
>[ 35804.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cce60] width 1600 pitch 6400 (/4 1600)
>[ 35804.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35804.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35804.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35804.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35804.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cce60]
>[ 35804.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cce60] width 1600 pitch 6400 (/4 1600)
>[ 35804.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35804.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35850.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c35220]
>[ 35850.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c35220] width 1600 pitch 6400 (/4 1600)
>[ 35850.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7dae0]
>[ 35850.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7dae0] width 1600 pitch 6400 (/4 1600)
>[ 35850.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c600]
>[ 35850.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c600] width 1600 pitch 6400 (/4 1600)
>[ 35850.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5dff0]
>[ 35850.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5dff0] width 1600 pitch 6400 (/4 1600)
>[ 35850.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cce60]
>[ 35850.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cce60] width 1600 pitch 6400 (/4 1600)
>[ 35850.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb2f20]
>[ 35850.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb2f20] width 1600 pitch 6400 (/4 1600)
>[ 35850.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cce60]
>[ 35850.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cce60] width 1600 pitch 6400 (/4 1600)
>[ 35850.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d5dff0]
>[ 35850.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d5dff0] width 1600 pitch 6400 (/4 1600)
>[ 35850.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7dae0]
>[ 35850.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7dae0] width 1600 pitch 6400 (/4 1600)
>[ 35850.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb2f20]
>[ 35850.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb2f20] width 1600 pitch 6400 (/4 1600)
>[ 35851.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd0210]
>[ 35851.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd0210] width 1600 pitch 6400 (/4 1600)
>[ 35852.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35852.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35852.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e62a0]
>[ 35852.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e62a0] width 1600 pitch 6400 (/4 1600)
>[ 35853.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bea800]
>[ 35853.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bea800] width 1600 pitch 6400 (/4 1600)
>[ 35853.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35853.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35853.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b2f0]
>[ 35853.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b2f0] width 1600 pitch 6400 (/4 1600)
>[ 35853.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 35853.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 35853.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd0210]
>[ 35853.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd0210] width 1600 pitch 6400 (/4 1600)
>[ 35853.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cce60]
>[ 35853.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cce60] width 1600 pitch 6400 (/4 1600)
>[ 35854.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7dae0]
>[ 35854.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7dae0] width 1600 pitch 6400 (/4 1600)
>[ 35854.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3290920]
>[ 35854.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3290920] width 1600 pitch 6400 (/4 1600)
>[ 35854.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7dae0]
>[ 35854.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7dae0] width 1600 pitch 6400 (/4 1600)
>[ 35854.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bea800]
>[ 35854.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bea800] width 1600 pitch 6400 (/4 1600)
>[ 35854.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35854.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35854.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3290920]
>[ 35855.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3290920] width 1600 pitch 6400 (/4 1600)
>[ 35855.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b2f0]
>[ 35855.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b2f0] width 1600 pitch 6400 (/4 1600)
>[ 35855.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e62a0]
>[ 35855.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e62a0] width 1600 pitch 6400 (/4 1600)
>[ 35855.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b2f0]
>[ 35855.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b2f0] width 1600 pitch 6400 (/4 1600)
>[ 35855.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 35855.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 35855.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b040]
>[ 35855.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b040] width 1600 pitch 6400 (/4 1600)
>[ 35855.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd0210]
>[ 35856.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd0210] width 1600 pitch 6400 (/4 1600)
>[ 35856.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200fea0]
>[ 35856.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200fea0] width 1600 pitch 6400 (/4 1600)
>[ 35856.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cce60]
>[ 35856.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cce60] width 1600 pitch 6400 (/4 1600)
>[ 35857.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bea800]
>[ 35857.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bea800] width 1600 pitch 6400 (/4 1600)
>[ 35857.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35857.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35857.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e62a0]
>[ 35857.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e62a0] width 1600 pitch 6400 (/4 1600)
>[ 35857.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35857.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35857.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b2f0]
>[ 35857.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b2f0] width 1600 pitch 6400 (/4 1600)
>[ 35857.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35857.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35857.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1eb2f20]
>[ 35857.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1eb2f20] width 1600 pitch 6400 (/4 1600)
>[ 35857.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c361a0]
>[ 35857.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c361a0] width 1600 pitch 6400 (/4 1600)
>[ 35857.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b540]
>[ 35857.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b540] width 1600 pitch 6400 (/4 1600)
>[ 35857.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b040]
>[ 35857.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b040] width 1600 pitch 6400 (/4 1600)
>[ 35857.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bd0210]
>[ 35857.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bd0210] width 1600 pitch 6400 (/4 1600)
>[ 35857.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x200fea0]
>[ 35857.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x200fea0] width 1600 pitch 6400 (/4 1600)
>[ 35857.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cce60]
>[ 35857.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cce60] width 1600 pitch 6400 (/4 1600)
>[ 35857.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b170]
>[ 35857.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b170] width 1600 pitch 6400 (/4 1600)
>[ 35859.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bdd2e0]
>[ 35859.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bdd2e0] width 1600 pitch 6400 (/4 1600)
>[ 35859.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1bdd2e0]
>[ 35859.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1bdd2e0] width 1600 pitch 6400 (/4 1600)
>[ 35877.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259e950]
>[ 35877.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259e950] width 1600 pitch 6400 (/4 1600)
>[ 36014.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1da10]
>[ 36014.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1da10] width 1600 pitch 6400 (/4 1600)
>[ 36014.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd24b0]
>[ 36014.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd24b0] width 1600 pitch 6400 (/4 1600)
>[ 36028.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f26760]
>[ 36028.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f26760] width 1600 pitch 6400 (/4 1600)
>[ 36028.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f26760]
>[ 36028.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f26760] width 1600 pitch 6400 (/4 1600)
>[ 36031.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1caa0]
>[ 36031.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1caa0] width 1600 pitch 6400 (/4 1600)
>[ 36036.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f2e320]
>[ 36036.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f2e320] width 1600 pitch 6400 (/4 1600)
>[ 36036.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f2dd10]
>[ 36036.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f2dd10] width 1600 pitch 6400 (/4 1600)
>[ 36064.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36064.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36067.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1da10]
>[ 36067.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1da10] width 1600 pitch 6400 (/4 1600)
>[ 36067.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36067.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36067.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1da10]
>[ 36067.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1da10] width 1600 pitch 6400 (/4 1600)
>[ 36068.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36068.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36068.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36068.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36068.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348560]
>[ 36068.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348560] width 1600 pitch 6400 (/4 1600)
>[ 36068.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1caa0]
>[ 36068.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1caa0] width 1600 pitch 6400 (/4 1600)
>[ 36068.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348560]
>[ 36068.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348560] width 1600 pitch 6400 (/4 1600)
>[ 36068.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348560]
>[ 36069.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348560] width 1600 pitch 6400 (/4 1600)
>[ 36069.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e1da10]
>[ 36069.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e1da10] width 1600 pitch 6400 (/4 1600)
>[ 36069.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2150550]
>[ 36069.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2150550] width 1600 pitch 6400 (/4 1600)
>[ 36069.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2150550]
>[ 36069.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2150550] width 1600 pitch 6400 (/4 1600)
>[ 36075.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c03e0]
>[ 36075.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c03e0] width 1600 pitch 6400 (/4 1600)
>[ 36084.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ecba20]
>[ 36084.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ecba20] width 1600 pitch 6400 (/4 1600)
>[ 36102.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e800]
>[ 36102.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e800] width 1600 pitch 6400 (/4 1600)
>[ 36102.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x248e800]
>[ 36103.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x248e800] width 1600 pitch 6400 (/4 1600)
>[ 36103.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325b50]
>[ 36103.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325b50] width 1600 pitch 6400 (/4 1600)
>[ 36103.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2457b30]
>[ 36103.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2457b30] width 1600 pitch 6400 (/4 1600)
>[ 36103.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325b50]
>[ 36103.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325b50] width 1600 pitch 6400 (/4 1600)
>[ 36103.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2457b60]
>[ 36103.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2457b60] width 1600 pitch 6400 (/4 1600)
>[ 36103.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325b50]
>[ 36103.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325b50] width 1600 pitch 6400 (/4 1600)
>[ 36103.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325b50]
>[ 36103.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325b50] width 1600 pitch 6400 (/4 1600)
>[ 36103.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2bc40]
>[ 36104.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2bc40] width 1600 pitch 6400 (/4 1600)
>[ 36104.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0380]
>[ 36104.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0380] width 1600 pitch 6400 (/4 1600)
>[ 36104.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325b50]
>[ 36104.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325b50] width 1600 pitch 6400 (/4 1600)
>[ 36104.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325b50]
>[ 36104.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325b50] width 1600 pitch 6400 (/4 1600)
>[ 36104.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2457c60]
>[ 36104.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2457c60] width 1600 pitch 6400 (/4 1600)
>[ 36104.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36104.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36104.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325b50]
>[ 36104.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325b50] width 1600 pitch 6400 (/4 1600)
>[ 36104.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36104.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36109.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36109.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36109.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36109.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36109.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36109.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36109.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36109.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36109.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36109.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36110.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36110.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36110.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36110.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36110.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36110.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36110.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36110.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36110.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36110.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36110.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36110.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36110.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36110.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36110.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36110.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36110.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36110.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36116.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0380]
>[ 36116.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0380] width 1600 pitch 6400 (/4 1600)
>[ 36116.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36116.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36116.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36116.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36116.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36116.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36116.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36116.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36117.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36117.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36117.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36117.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36117.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36117.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36117.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36117.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36117.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36117.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36118.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36118.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36118.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36118.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36118.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f1d8d0]
>[ 36118.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f1d8d0] width 1600 pitch 6400 (/4 1600)
>[ 36118.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36118.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36118.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f1d8d0]
>[ 36118.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f1d8d0] width 1600 pitch 6400 (/4 1600)
>[ 36121.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddaaa0]
>[ 36121.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddaaa0] width 1600 pitch 6400 (/4 1600)
>[ 36121.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444f80]
>[ 36121.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444f80] width 1600 pitch 6400 (/4 1600)
>[ 36121.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348410]
>[ 36121.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348410] width 1600 pitch 6400 (/4 1600)
>[ 36121.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444f80]
>[ 36121.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444f80] width 1600 pitch 6400 (/4 1600)
>[ 36121.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddaaa0]
>[ 36122.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddaaa0] width 1600 pitch 6400 (/4 1600)
>[ 36122.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348410]
>[ 36122.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348410] width 1600 pitch 6400 (/4 1600)
>[ 36122.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36122.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36122.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36123.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36123.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348410]
>[ 36123.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348410] width 1600 pitch 6400 (/4 1600)
>[ 36123.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444f80]
>[ 36123.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444f80] width 1600 pitch 6400 (/4 1600)
>[ 36123.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348410]
>[ 36123.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348410] width 1600 pitch 6400 (/4 1600)
>[ 36123.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33690f0]
>[ 36123.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33690f0] width 1600 pitch 6400 (/4 1600)
>[ 36123.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3348410]
>[ 36123.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3348410] width 1600 pitch 6400 (/4 1600)
>[ 36123.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444f80]
>[ 36123.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444f80] width 1600 pitch 6400 (/4 1600)
>[ 36151.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e40980]
>[ 36151.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e40980] width 1600 pitch 6400 (/4 1600)
>[ 36151.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e40980]
>[ 36151.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e40980] width 1600 pitch 6400 (/4 1600)
>[ 36229.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2444f80]
>[ 36229.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2444f80] width 1600 pitch 6400 (/4 1600)
>[ 36253.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b8460]
>[ 36253.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b8460] width 1600 pitch 6400 (/4 1600)
>[ 36253.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b8c60]
>[ 36253.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b8c60] width 1600 pitch 6400 (/4 1600)
>[ 36287.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592980]
>[ 36287.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592980] width 1600 pitch 6400 (/4 1600)
>[ 36495.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f1f680]
>[ 36495.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f1f680] width 1600 pitch 6400 (/4 1600)
>[ 36495.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b0240]
>[ 36495.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b0240] width 1600 pitch 6400 (/4 1600)
>[ 36495.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e490]
>[ 36495.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e490] width 1600 pitch 6400 (/4 1600)
>[ 36542.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d2390]
>[ 36542.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d2390] width 1600 pitch 6400 (/4 1600)
>[ 36544.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20dae70]
>[ 36544.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20dae70] width 1600 pitch 6400 (/4 1600)
>[ 36544.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2592980]
>[ 36544.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2592980] width 1600 pitch 6400 (/4 1600)
>[ 36544.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d2390]
>[ 36544.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d2390] width 1600 pitch 6400 (/4 1600)
>[ 36544.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36544.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36544.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd25d0]
>[ 36544.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd25d0] width 1600 pitch 6400 (/4 1600)
>[ 36544.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36544.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36545.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd25d0]
>[ 36545.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd25d0] width 1600 pitch 6400 (/4 1600)
>[ 36545.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36545.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36545.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd25d0]
>[ 36545.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd25d0] width 1600 pitch 6400 (/4 1600)
>[ 36545.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36545.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36545.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd25d0]
>[ 36545.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd25d0] width 1600 pitch 6400 (/4 1600)
>[ 36546.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd25d0]
>[ 36546.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd25d0] width 1600 pitch 6400 (/4 1600)
>[ 36546.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0380]
>[ 36546.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0380] width 1600 pitch 6400 (/4 1600)
>[ 36552.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36552.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36552.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd25d0]
>[ 36552.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd25d0] width 1600 pitch 6400 (/4 1600)
>[ 36552.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36552.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36552.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1dd25d0]
>[ 36552.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1dd25d0] width 1600 pitch 6400 (/4 1600)
>[ 36552.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36552.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36553.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36553.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36553.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36553.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36553.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36553.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36553.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36553.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36554.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20da750]
>[ 36554.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20da750] width 1600 pitch 6400 (/4 1600)
>[ 36554.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36554.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36554.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325c80]
>[ 36554.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325c80] width 1600 pitch 6400 (/4 1600)
>[ 36554.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331caf0]
>[ 36554.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331caf0] width 1600 pitch 6400 (/4 1600)
>[ 36554.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331cdc0]
>[ 36554.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331cdc0] width 1600 pitch 6400 (/4 1600)
>[ 36568.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36568.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36568.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36568.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36568.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36569.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36569.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36569.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36569.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36569.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36569.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36569.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36569.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36569.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36569.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36569.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36569.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36569.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36569.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36569.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36569.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36569.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36570.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36570.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36570.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36570.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36571.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36571.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36572.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36572.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36573.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36573.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36574.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36574.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36574.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36574.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36574.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36574.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36574.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36574.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36574.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36574.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36574.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36574.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36592.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x20dae70]
>[ 36592.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x20dae70] width 1600 pitch 6400 (/4 1600)
>[ 36593.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b9c20]
>[ 36593.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b9c20] width 1600 pitch 6400 (/4 1600)
>[ 36593.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b9bd0]
>[ 36593.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b9bd0] width 1600 pitch 6400 (/4 1600)
>[ 36593.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b9c40]
>[ 36593.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b9c40] width 1600 pitch 6400 (/4 1600)
>[ 36596.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da2c0]
>[ 36596.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da2c0] width 1600 pitch 6400 (/4 1600)
>[ 36596.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b9b70]
>[ 36596.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b9b70] width 1600 pitch 6400 (/4 1600)
>[ 36596.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead310]
>[ 36596.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead310] width 1600 pitch 6400 (/4 1600)
>[ 36596.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead310]
>[ 36596.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead310] width 1600 pitch 6400 (/4 1600)
>[ 36596.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1bf0]
>[ 36596.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1bf0] width 1600 pitch 6400 (/4 1600)
>[ 36596.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1bf0]
>[ 36596.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1bf0] width 1600 pitch 6400 (/4 1600)
>[ 36596.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b18f0]
>[ 36596.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b18f0] width 1600 pitch 6400 (/4 1600)
>[ 36596.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ead310]
>[ 36596.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ead310] width 1600 pitch 6400 (/4 1600)
>[ 36596.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b18f0]
>[ 36596.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b18f0] width 1600 pitch 6400 (/4 1600)
>[ 36598.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36598.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36598.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36598.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36598.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36598.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36598.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36598.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36598.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36598.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36598.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36598.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36598.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36599.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36599.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36599.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36599.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36599.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36599.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36599.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36599.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36599.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36599.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36599.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36599.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36599.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36599.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36599.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36606.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36606.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36606.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36606.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36606.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36606.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36606.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36606.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36606.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36606.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36606.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36606.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36607.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36607.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36607.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36607.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36607.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36607.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36607.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36607.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36607.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36607.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36608.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36608.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36609.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36609.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36609.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36609.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36609.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36609.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36609.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339cd10]
>[ 36609.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339cd10] width 1600 pitch 6400 (/4 1600)
>[ 36609.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36609.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36609.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf000]
>[ 36609.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf000] width 1600 pitch 6400 (/4 1600)
>[ 36609.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b7e40]
>[ 36609.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b7e40] width 1600 pitch 6400 (/4 1600)
>[ 36609.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36609.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36613.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8160]
>[ 36613.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8160] width 1600 pitch 6400 (/4 1600)
>[ 36613.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36613.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36639.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36639.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36639.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36639.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36639.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36639.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36639.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36639.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36639.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36639.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36639.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36639.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36639.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36639.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36639.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36639.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36639.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36639.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36639.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36639.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36639.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36639.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36639.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36639.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36639.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36639.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36640.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36640.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36640.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36640.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36640.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36640.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36640.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36640.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36640.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36640.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36640.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36640.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36640.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36640.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36640.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36640.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36640.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36640.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36640.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36640.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36640.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36640.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36640.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c61e0]
>[ 36640.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c61e0] width 1600 pitch 6400 (/4 1600)
>[ 36640.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36640.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36640.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36640.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36640.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36640.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36640.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36640.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36640.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36640.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36640.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331cd30]
>[ 36640.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331cd30] width 1600 pitch 6400 (/4 1600)
>[ 36640.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36640.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36640.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36640.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36640.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d45210]
>[ 36640.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d45210] width 1600 pitch 6400 (/4 1600)
>[ 36640.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36640.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36640.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36640.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36641.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36641.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36641.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36641.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36641.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ccd0]
>[ 36641.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ccd0] width 1600 pitch 6400 (/4 1600)
>[ 36641.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331cd30]
>[ 36641.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331cd30] width 1600 pitch 6400 (/4 1600)
>[ 36641.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ccd0]
>[ 36641.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ccd0] width 1600 pitch 6400 (/4 1600)
>[ 36641.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331cd30]
>[ 36641.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331cd30] width 1600 pitch 6400 (/4 1600)
>[ 36641.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ccd0]
>[ 36641.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ccd0] width 1600 pitch 6400 (/4 1600)
>[ 36641.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36641.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36641.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36641.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36641.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36641.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36641.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36641.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36641.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36641.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36641.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7520]
>[ 36641.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7520] width 1600 pitch 6400 (/4 1600)
>[ 36641.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309560]
>[ 36641.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309560] width 1600 pitch 6400 (/4 1600)
>[ 36641.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36641.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36641.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36641.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36641.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36641.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36641.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268aac0]
>[ 36641.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268aac0] width 1600 pitch 6400 (/4 1600)
>[ 36641.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36641.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36641.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6390]
>[ 36641.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6390] width 1600 pitch 6400 (/4 1600)
>[ 36641.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c6330]
>[ 36641.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c6330] width 1600 pitch 6400 (/4 1600)
>[ 36642.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c7c0]
>[ 36642.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c7c0] width 1600 pitch 6400 (/4 1600)
>[ 36696.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c2920]
>[ 36696.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c2920] width 1600 pitch 6400 (/4 1600)
>[ 36696.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1e590]
>[ 36696.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1e590] width 1600 pitch 6400 (/4 1600)
>[ 36696.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c43b0]
>[ 36696.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c43b0] width 1600 pitch 6400 (/4 1600)
>[ 36696.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d1e590]
>[ 36696.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d1e590] width 1600 pitch 6400 (/4 1600)
>[ 36696.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c43b0]
>[ 36696.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c43b0] width 1600 pitch 6400 (/4 1600)
>[ 36696.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c2920]
>[ 36696.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c2920] width 1600 pitch 6400 (/4 1600)
>[ 36696.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d403a0]
>[ 36696.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d403a0] width 1600 pitch 6400 (/4 1600)
>[ 36696.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c43b0]
>[ 36696.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c43b0] width 1600 pitch 6400 (/4 1600)
>[ 36696.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c2920]
>[ 36696.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c2920] width 1600 pitch 6400 (/4 1600)
>[ 36696.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c43b0]
>[ 36696.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c43b0] width 1600 pitch 6400 (/4 1600)
>[ 36696.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c2920]
>[ 36697.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c2920] width 1600 pitch 6400 (/4 1600)
>[ 36697.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c43b0]
>[ 36697.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c43b0] width 1600 pitch 6400 (/4 1600)
>[ 36697.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c2920]
>[ 36697.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c2920] width 1600 pitch 6400 (/4 1600)
>[ 36697.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c43b0]
>[ 36697.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c43b0] width 1600 pitch 6400 (/4 1600)
>[ 36697.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d403a0]
>[ 36697.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d403a0] width 1600 pitch 6400 (/4 1600)
>[ 36697.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c2920]
>[ 36697.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c2920] width 1600 pitch 6400 (/4 1600)
>[ 36697.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d403a0]
>[ 36697.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d403a0] width 1600 pitch 6400 (/4 1600)
>[ 36697.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c2920]
>[ 36697.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c2920] width 1600 pitch 6400 (/4 1600)
>[ 36698.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d403a0]
>[ 36698.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d403a0] width 1600 pitch 6400 (/4 1600)
>[ 36698.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c2920]
>[ 36698.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c2920] width 1600 pitch 6400 (/4 1600)
>[ 36706.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25af1e0]
>[ 36706.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25af1e0] width 1600 pitch 6400 (/4 1600)
>[ 36706.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d403a0]
>[ 36706.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d403a0] width 1600 pitch 6400 (/4 1600)
>[ 36750.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c9160]
>[ 36750.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c9160] width 1600 pitch 6400 (/4 1600)
>[ 36750.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bdea0]
>[ 36750.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bdea0] width 1600 pitch 6400 (/4 1600)
>[ 36751.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1f2eea0]
>[ 36751.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1f2eea0] width 1600 pitch 6400 (/4 1600)
>[ 36751.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c9160]
>[ 36751.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c9160] width 1600 pitch 6400 (/4 1600)
>[ 36778.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6c40]
>[ 36778.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6c40] width 1600 pitch 6400 (/4 1600)
>[ 36779.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2e880]
>[ 36779.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2e880] width 1600 pitch 6400 (/4 1600)
>[ 36779.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f6f0]
>[ 36779.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f6f0] width 1600 pitch 6400 (/4 1600)
>[ 36779.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c3690]
>[ 36779.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c3690] width 1600 pitch 6400 (/4 1600)
>[ 36779.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329e470]
>[ 36779.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329e470] width 1600 pitch 6400 (/4 1600)
>[ 36779.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a2200]
>[ 36779.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a2200] width 1600 pitch 6400 (/4 1600)
>[ 36779.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3297550]
>[ 36779.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3297550] width 1600 pitch 6400 (/4 1600)
>[ 36779.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a2200]
>[ 36780.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a2200] width 1600 pitch 6400 (/4 1600)
>[ 36780.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a1410]
>[ 36780.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a1410] width 1600 pitch 6400 (/4 1600)
>[ 36780.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a1410]
>[ 36780.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a1410] width 1600 pitch 6400 (/4 1600)
>[ 36781.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6c40]
>[ 36781.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6c40] width 1600 pitch 6400 (/4 1600)
>[ 36781.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f6f0]
>[ 36781.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f6f0] width 1600 pitch 6400 (/4 1600)
>[ 36781.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329e470]
>[ 36781.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329e470] width 1600 pitch 6400 (/4 1600)
>[ 36782.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a1410]
>[ 36782.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a1410] width 1600 pitch 6400 (/4 1600)
>[ 36782.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f6f0]
>[ 36782.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f6f0] width 1600 pitch 6400 (/4 1600)
>[ 36782.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c3690]
>[ 36782.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c3690] width 1600 pitch 6400 (/4 1600)
>[ 36782.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f6f0]
>[ 36782.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f6f0] width 1600 pitch 6400 (/4 1600)
>[ 36782.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36782.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36799.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2e880]
>[ 36799.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2e880] width 1600 pitch 6400 (/4 1600)
>[ 36799.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a2200]
>[ 36799.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a2200] width 1600 pitch 6400 (/4 1600)
>[ 36799.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0380]
>[ 36799.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0380] width 1600 pitch 6400 (/4 1600)
>[ 36799.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f6f0]
>[ 36799.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f6f0] width 1600 pitch 6400 (/4 1600)
>[ 36799.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6c40]
>[ 36799.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6c40] width 1600 pitch 6400 (/4 1600)
>[ 36799.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36799.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36799.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e2e880]
>[ 36799.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e2e880] width 1600 pitch 6400 (/4 1600)
>[ 36800.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36800.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36800.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329e470]
>[ 36800.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329e470] width 1600 pitch 6400 (/4 1600)
>[ 36800.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a1410]
>[ 36800.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a1410] width 1600 pitch 6400 (/4 1600)
>[ 36800.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6c40]
>[ 36800.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6c40] width 1600 pitch 6400 (/4 1600)
>[ 36800.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36800.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36800.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2244cd0]
>[ 36800.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2244cd0] width 1600 pitch 6400 (/4 1600)
>[ 36800.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a2200]
>[ 36800.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a2200] width 1600 pitch 6400 (/4 1600)
>[ 36800.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329e470]
>[ 36800.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329e470] width 1600 pitch 6400 (/4 1600)
>[ 36800.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f6f0]
>[ 36800.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f6f0] width 1600 pitch 6400 (/4 1600)
>[ 36801.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0380]
>[ 36801.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0380] width 1600 pitch 6400 (/4 1600)
>[ 36801.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3297550]
>[ 36801.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3297550] width 1600 pitch 6400 (/4 1600)
>[ 36801.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1e7c360]
>[ 36801.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1e7c360] width 1600 pitch 6400 (/4 1600)
>[ 36801.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a2200]
>[ 36801.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a2200] width 1600 pitch 6400 (/4 1600)
>[ 36801.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329e470]
>[ 36801.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329e470] width 1600 pitch 6400 (/4 1600)
>[ 36801.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6c40]
>[ 36801.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6c40] width 1600 pitch 6400 (/4 1600)
>[ 36801.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6c40]
>[ 36801.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6c40] width 1600 pitch 6400 (/4 1600)
>[ 36801.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329e470]
>[ 36802.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329e470] width 1600 pitch 6400 (/4 1600)
>[ 36802.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0b2b0]
>[ 36802.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0b2b0] width 1600 pitch 6400 (/4 1600)
>[ 36802.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c3690]
>[ 36802.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c3690] width 1600 pitch 6400 (/4 1600)
>[ 36802.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36802.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36802.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0380]
>[ 36802.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0380] width 1600 pitch 6400 (/4 1600)
>[ 36802.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a1410]
>[ 36802.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a1410] width 1600 pitch 6400 (/4 1600)
>[ 36802.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d0b2b0]
>[ 36803.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d0b2b0] width 1600 pitch 6400 (/4 1600)
>[ 36803.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329e470]
>[ 36803.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329e470] width 1600 pitch 6400 (/4 1600)
>[ 36803.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6c40]
>[ 36803.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6c40] width 1600 pitch 6400 (/4 1600)
>[ 36803.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a2200]
>[ 36803.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a2200] width 1600 pitch 6400 (/4 1600)
>[ 36838.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330c8d0]
>[ 36838.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330c8d0] width 1600 pitch 6400 (/4 1600)
>[ 36838.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f6f0]
>[ 36838.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f6f0] width 1600 pitch 6400 (/4 1600)
>[ 36991.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282e30]
>[ 36991.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282e30] width 1600 pitch 6400 (/4 1600)
>[ 37254.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32683d0]
>[ 37254.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32683d0] width 1600 pitch 6400 (/4 1600)
>[ 37255.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32683d0]
>[ 37255.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32683d0] width 1600 pitch 6400 (/4 1600)
>[ 37276.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326db10]
>[ 37276.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326db10] width 1600 pitch 6400 (/4 1600)
>[ 37276.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ae80]
>[ 37276.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ae80] width 1600 pitch 6400 (/4 1600)
>[ 37276.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b050]
>[ 37276.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b050] width 1600 pitch 6400 (/4 1600)
>[ 37276.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ae80]
>[ 37276.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ae80] width 1600 pitch 6400 (/4 1600)
>[ 37276.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326d7d0]
>[ 37276.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326d7d0] width 1600 pitch 6400 (/4 1600)
>[ 37276.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326d7d0]
>[ 37276.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326d7d0] width 1600 pitch 6400 (/4 1600)
>[ 37276.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b050]
>[ 37276.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b050] width 1600 pitch 6400 (/4 1600)
>[ 37277.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32645e0]
>[ 37277.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32645e0] width 1600 pitch 6400 (/4 1600)
>[ 37277.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ae80]
>[ 37277.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ae80] width 1600 pitch 6400 (/4 1600)
>[ 37277.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32645e0]
>[ 37277.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32645e0] width 1600 pitch 6400 (/4 1600)
>[ 37277.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ae80]
>[ 37277.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ae80] width 1600 pitch 6400 (/4 1600)
>[ 37277.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32645e0]
>[ 37277.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32645e0] width 1600 pitch 6400 (/4 1600)
>[ 37277.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ae80]
>[ 37277.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ae80] width 1600 pitch 6400 (/4 1600)
>[ 37333.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326d080]
>[ 37333.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326d080] width 1600 pitch 6400 (/4 1600)
>[ 37333.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326d590]
>[ 37333.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326d590] width 1600 pitch 6400 (/4 1600)
>[ 37457.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264c320]
>[ 37457.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264c320] width 1600 pitch 6400 (/4 1600)
>[ 37457.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2678260]
>[ 37457.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2678260] width 1600 pitch 6400 (/4 1600)
>[ 37536.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2678900]
>[ 37536.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2678900] width 1600 pitch 6400 (/4 1600)
>[ 37536.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c3ab0]
>[ 37536.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c3ab0] width 1600 pitch 6400 (/4 1600)
>[ 37555.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b8bb0]
>[ 37555.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b8bb0] width 1600 pitch 6400 (/4 1600)
>[ 37559.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674010]
>[ 37559.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674010] width 1600 pitch 6400 (/4 1600)
>[ 37559.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265ad30]
>[ 37559.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265ad30] width 1600 pitch 6400 (/4 1600)
>[ 37559.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2674010]
>[ 37559.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2674010] width 1600 pitch 6400 (/4 1600)
>[ 37559.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265ad30]
>[ 37559.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265ad30] width 1600 pitch 6400 (/4 1600)
>[ 37565.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2665d00]
>[ 37565.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2665d00] width 1600 pitch 6400 (/4 1600)
>[ 37857.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2058c50]
>[ 37857.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2058c50] width 1600 pitch 6400 (/4 1600)
>[ 37861.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x202d170]
>[ 37861.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x202d170] width 1600 pitch 6400 (/4 1600)
>[ 37862.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2660400]
>[ 37862.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2660400] width 1600 pitch 6400 (/4 1600)
>[ 37863.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c54c0]
>[ 37863.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c54c0] width 1600 pitch 6400 (/4 1600)
>[ 37863.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2660400]
>[ 37863.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2660400] width 1600 pitch 6400 (/4 1600)
>[ 37864.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c54c0]
>[ 37864.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c54c0] width 1600 pitch 6400 (/4 1600)
>[ 37879.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ad7e0]
>[ 37880.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ad7e0] width 1600 pitch 6400 (/4 1600)
>[ 37882.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2018070]
>[ 37888.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2018070] width 1600 pitch 6400 (/4 1600)
>[ 37889.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a55b0]
>[ 37889.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a55b0] width 1600 pitch 6400 (/4 1600)
>[ 37897.978] [mi] EQ overflowing.  Additional events will be discarded until existing events are processed.
>[ 37897.992] 
>[ 37897.992] Backtrace:
>[ 37899.751] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[ 37899.751] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x55158b]
>[ 37899.751] 2: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22]
>[ 37899.751] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f4cfd380000+0x60e4) [0x7f4cfd3860e4]
>[ 37899.751] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[ 37899.751] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[ 37899.751] 6: /lib64/libpthread.so.0 (0x3fcc600000+0xefe0) [0x3fcc60efe0]
>[ 37899.751] 7: /usr/bin/Xorg (0x400000+0x6ac20) [0x46ac20]
>[ 37899.751] 8: /lib64/libpthread.so.0 (0x3fcc600000+0xefe0) [0x3fcc60efe0]
>[ 37899.751] 9: /lib64/libc.so.6 (cfree+0x1c) [0x3fcc27f99c]
>[ 37899.751] 10: /usr/bin/Xorg (0x400000+0x4e729) [0x44e729]
>[ 37899.752] 11: /usr/bin/Xorg (0x400000+0x4bbf5) [0x44bbf5]
>[ 37899.752] 12: /usr/bin/Xorg (DeletePassiveGrab+0x40) [0x44be30]
>[ 37899.752] 13: /usr/bin/Xorg (0x400000+0x554a2) [0x4554a2]
>[ 37899.752] 14: /usr/bin/Xorg (FreeResource+0xdb) [0x455c5b]
>[ 37899.752] 15: /usr/bin/Xorg (DeletePassiveGrabFromList+0x43b) [0x44c45b]
>[ 37899.752] 16: /usr/bin/Xorg (ProcUngrabKey+0x125) [0x441225]
>[ 37899.752] 17: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[ 37899.752] 18: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[ 37899.752] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3fcc221735]
>[ 37899.752] 20: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[ 37899.752] 
>[ 37899.752] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack.
>[ 37899.752] [mi] mieq is *NOT* the cause.  It is a victim.
>[ 37900.865] [mi] EQ overflow continuing.  100 events have been dropped.
>[ 37900.865] 
>[ 37900.865] Backtrace:
>[ 37900.865] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[ 37900.865] 1: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22]
>[ 37900.865] 2: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f4cfd380000+0x60e4) [0x7f4cfd3860e4]
>[ 37900.865] 3: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[ 37900.865] 4: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[ 37900.865] 5: /lib64/libpthread.so.0 (0x3fcc600000+0xefe0) [0x3fcc60efe0]
>[ 37900.865] 6: /usr/bin/Xorg (0x400000+0x6ac20) [0x46ac20]
>[ 37900.865] 7: /lib64/libpthread.so.0 (0x3fcc600000+0xefe0) [0x3fcc60efe0]
>[ 37900.865] 8: /lib64/libc.so.6 (cfree+0x1c) [0x3fcc27f99c]
>[ 37900.865] 9: /usr/bin/Xorg (0x400000+0x4e729) [0x44e729]
>[ 37900.865] 10: /usr/bin/Xorg (0x400000+0x4bbf5) [0x44bbf5]
>[ 37900.865] 11: /usr/bin/Xorg (DeletePassiveGrab+0x40) [0x44be30]
>[ 37900.865] 12: /usr/bin/Xorg (0x400000+0x554a2) [0x4554a2]
>[ 37900.865] 13: /usr/bin/Xorg (FreeResource+0xdb) [0x455c5b]
>[ 37900.866] 14: /usr/bin/Xorg (DeletePassiveGrabFromList+0x43b) [0x44c45b]
>[ 37900.866] 15: /usr/bin/Xorg (ProcUngrabKey+0x125) [0x441225]
>[ 37900.866] 16: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[ 37900.866] 17: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[ 37900.866] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3fcc221735]
>[ 37900.866] 19: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[ 37900.866] 
>[ 37901.200] [mi] Increasing EQ size to 512 to prevent dropped events.
>[ 37901.234] [mi] EQ processing has resumed after 119 dropped events.
>[ 37901.234] [mi] This may be caused my a misbehaving driver monopolizing the server's resources.

Actions: View

Attachments on bug 912285: 698795 | 698796 | 698797 | 698798 | 698799 | 698800