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Red Hat Bugzilla – Attachment 882843 Details for
Bug 1084576
Nested KVM on AMD doesn't work
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output of cpuid on L1
L1-cpuid.txt (text/plain), 27.17 KB, created by
L.L.Robinson
on 2014-04-04 20:03:02 UTC
(
hide
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Description:
output of cpuid on L1
Filename:
MIME Type:
Creator:
L.L.Robinson
Created:
2014-04-04 20:03:02 UTC
Size:
27.17 KB
patch
obsolete
>CPU 0: > vendor_id = "AuthenticAMD" > version information (1/eax): > processor type = primary processor (0) > family = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15) > model = 0x6 (6) > stepping id = 0x1 (1) > extended family = 0x0 (0) > extended model = 0x0 (0) > (simple synth) = AMD Opteron / Athlon 64 / Athlon 64 FX / Sempron / Turion / Athlon Neo / Dual Core Opteron / Athlon 64 X2 / Athlon 64 FX / mobile Athlon 64 / mobile Sempron / mobile Athlon XP-M (DP) (unknown model) > miscellaneous (1/ebx): > process local APIC physical ID = 0x0 (0) > cpu count = 0x0 (0) > CLFLUSH line size = 0x8 (8) > brand index = 0x0 (0) > brand id = 0x00 (0): unknown > feature information (1/edx): > x87 FPU on chip = true > virtual-8086 mode enhancement = true > debugging extensions = true > page size extensions = true > time stamp counter = true > RDMSR and WRMSR support = true > physical address extensions = true > machine check exception = true > CMPXCHG8B inst. = true > APIC on chip = true > SYSENTER and SYSEXIT = true > memory type range registers = true > PTE global bit = true > machine check architecture = true > conditional move/compare instruction = true > page attribute table = true > page size extension = true > processor serial number = false > CLFLUSH instruction = true > debug store = false > thermal monitor and clock ctrl = false > MMX Technology = true > FXSAVE/FXRSTOR = true > SSE extensions = true > SSE2 extensions = true > self snoop = false > hyper-threading / multi-core supported = false > therm. monitor = false > IA64 = false > pending break event = false > feature information (1/ecx): > PNI/SSE3: Prescott New Instructions = true > PCLMULDQ instruction = false > 64-bit debug store = false > MONITOR/MWAIT = false > CPL-qualified debug store = false > VMX: virtual machine extensions = false > SMX: safer mode extensions = false > Enhanced Intel SpeedStep Technology = false > thermal monitor 2 = false > SSSE3 extensions = false > context ID: adaptive or shared L1 data = false > FMA instruction = false > CMPXCHG16B instruction = true > xTPR disable = false > perfmon and debug = false > process context identifiers = false > direct cache access = false > SSE4.1 extensions = false > SSE4.2 extensions = false > extended xAPIC support = false > MOVBE instruction = false > POPCNT instruction = true > time stamp counter deadline = false > AES instruction = false > XSAVE/XSTOR states = false > OS-enabled XSAVE/XSTOR = false > AVX: advanced vector extensions = false > F16C half-precision convert instruction = false > RDRAND instruction = false > hypervisor guest status = true > cache and TLB information (2): > 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines > 0x30: L1 cache: 32K, 8-way, 64 byte lines > 0x2c: L1 data cache: 32K, 8-way, 64 byte lines > processor serial number: 0000-0F61-0000-0000-0000-0000 > deterministic cache parameters (4): > --- cache 0 --- > cache type = data cache (1) > cache level = 0x1 (1) > self-initializing cache level = true > fully associative cache = false > extra threads sharing this cache = 0x0 (0) > extra processor cores on this die = 0x0 (0) > system coherency line size = 0x3f (63) > physical line partitions = 0x0 (0) > ways of associativity = 0x7 (7) > WBINVD/INVD behavior on lower caches = true > inclusive to lower caches = false > complex cache indexing = false > number of sets - 1 (s) = 63 > --- cache 1 --- > cache type = instruction cache (2) > cache level = 0x1 (1) > self-initializing cache level = true > fully associative cache = false > extra threads sharing this cache = 0x0 (0) > extra processor cores on this die = 0x0 (0) > system coherency line size = 0x3f (63) > physical line partitions = 0x0 (0) > ways of associativity = 0x7 (7) > WBINVD/INVD behavior on lower caches = true > inclusive to lower caches = false > complex cache indexing = false > number of sets - 1 (s) = 63 > --- cache 2 --- > cache type = unified cache (3) > cache level = 0x2 (2) > self-initializing cache level = true > fully associative cache = false > extra threads sharing this cache = 0x0 (0) > extra processor cores on this die = 0x0 (0) > system coherency line size = 0x3f (63) > physical line partitions = 0x0 (0) > ways of associativity = 0xf (15) > WBINVD/INVD behavior on lower caches = true > inclusive to lower caches = false > complex cache indexing = false > number of sets - 1 (s) = 4095 > MONITOR/MWAIT (5): > smallest monitor-line size (bytes) = 0x0 (0) > largest monitor-line size (bytes) = 0x0 (0) > enum of Monitor-MWAIT exts supported = true > supports intrs as break-event for MWAIT = true > number of C0 sub C-states using MWAIT = 0x0 (0) > number of C1 sub C-states using MWAIT = 0x0 (0) > number of C2 sub C-states using MWAIT = 0x0 (0) > number of C3 sub C-states using MWAIT = 0x0 (0) > number of C4 sub C-states using MWAIT = 0x0 (0) > number of C5 sub C-states using MWAIT = 0x0 (0) > number of C6 sub C-states using MWAIT = 0x0 (0) > number of C7 sub C-states using MWAIT = 0x0 (0) > hypervisor_id = "KVMKVMKVM " > hypervisor features (0x40000001/eax): > kvmclock available at MSR 0x11 = true > delays unnecessary for PIO ops = true > mmu_op = false > kvmclock available a MSR 0x4b564d00 = true > async pf enable available by MSR = true > steal clock supported = true > guest EOI optimization enabled = true > stable: no guest per-cpu warps expected = true > extended processor signature (0x80000001/eax): > family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15) > model = 0x6 (6) > stepping id = 0x1 (1) > extended family = 0x0 (0) > extended model = 0x0 (0) > (simple synth) = AMD Opteron / Athlon 64 / Athlon 64 FX / Sempron / Turion / Athlon Neo / Dual Core Opteron / Athlon 64 X2 / Athlon 64 FX / mobile Athlon 64 / mobile Sempron / mobile Athlon XP-M (DP) (unknown model) > extended feature flags (0x80000001/edx): > x87 FPU on chip = true > virtual-8086 mode enhancement = true > debugging extensions = true > page size extensions = true > time stamp counter = true > RDMSR and WRMSR support = true > physical address extensions = true > machine check exception = true > CMPXCHG8B inst. = true > APIC on chip = true > SYSCALL and SYSRET instructions = true > memory type range registers = true > global paging extension = true > machine check architecture = true > conditional move/compare instruction = true > page attribute table = true > page size extension = true > multiprocessing capable = false > no-execute page protection = true > AMD multimedia instruction extensions = true > MMX Technology = true > FXSAVE/FXRSTOR = true > SSE extensions = true > 1-GB large page support = true > RDTSCP = false > long mode (AA-64) = true > 3DNow! instruction extensions = true > 3DNow! instructions = true > extended brand id (0x80000001/ebx): > raw = 0x0 (0) > BrandId = 0x0 (0) > BrandTableIndex = 0x0 (0) > NN = 0x0 (0) > AMD feature flags (0x80000001/ecx): > LAHF/SAHF supported in 64-bit mode = true > CMP Legacy = true > SVM: secure virtual machine = true > extended APIC space = false > AltMovCr8 = true > LZCNT advanced bit manipulation = true > SSE4A support = true > misaligned SSE mode = true > 3DNow! PREFETCH/PREFETCHW instructions = true > OS visible workaround = true > instruction based sampling = false > XOP support = false > SKINIT/STGI support = false > watchdog timer support = false > lightweight profiling support = false > 4-operand FMA instruction = false > NodeId MSR C001100C = false > TBM support = false > topology extensions = false > brand = "AMD Opteron 23xx (Gen 3 Class Opteron)" > L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): > instruction # entries = 0xff (255) > instruction associativity = 0x1 (1) > data # entries = 0xff (255) > data associativity = 0x1 (1) > L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): > instruction # entries = 0xff (255) > instruction associativity = 0x1 (1) > data # entries = 0xff (255) > data associativity = 0x1 (1) > L1 data cache information (0x80000005/ecx): > line size (bytes) = 0x40 (64) > lines per tag = 0x1 (1) > associativity = 0x2 (2) > size (Kb) = 0x40 (64) > L1 instruction cache information (0x80000005/edx): > line size (bytes) = 0x40 (64) > lines per tag = 0x1 (1) > associativity = 0x2 (2) > size (Kb) = 0x40 (64) > L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): > instruction # entries = 0x0 (0) > instruction associativity = L2 off (0) > data # entries = 0x0 (0) > data associativity = L2 off (0) > L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): > instruction # entries = 0x200 (512) > instruction associativity = 4-way (4) > data # entries = 0x200 (512) > data associativity = 4-way (4) > L2 unified cache information (0x80000006/ecx): > line size (bytes) = 0x40 (64) > lines per tag = 0x1 (1) > associativity = 16-way (8) > size (Kb) = 0x200 (512) > L3 cache information (0x80000006/edx): > line size (bytes) = 0x0 (0) > lines per tag = 0x0 (0) > associativity = L2 off (0) > size (in 512Kb units) = 0x0 (0) > Advanced Power Management Features (0x80000007/edx): > temperature sensing diode = false > frequency ID (FID) control = false > voltage ID (VID) control = false > thermal trip (TTP) = false > thermal monitor (TM) = false > software thermal control (STC) = false > 100 MHz multiplier control = false > hardware P-State control = false > TscInvariant = false > Physical Address and Linear Address Size (0x80000008/eax): > maximum physical address bits = 0x28 (40) > maximum linear (virtual) address bits = 0x30 (48) > maximum guest physical address bits = 0x0 (0) > Logical CPU cores (0x80000008/ecx): > number of CPU cores - 1 = 0x0 (0) > ApicIdCoreIdSize = 0x0 (0) > (instruction supported synth): > CMPXCHG8B = true > conditional move/compare = true > PREFETCH/PREFETCHW = true > (multi-processing synth): none > (multi-processing method): AMD > (synth) = AMD Opteron / Athlon 64 / Athlon 64 FX / Sempron / Turion / Athlon Neo / Dual Core Opteron / Athlon 64 X2 / Athlon 64 FX / mobile Athlon 64 / mobile Sempron / mobile Athlon XP-M (DP) (unknown model) >CPU 1: > vendor_id = "AuthenticAMD" > version information (1/eax): > processor type = primary processor (0) > family = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15) > model = 0x6 (6) > stepping id = 0x1 (1) > extended family = 0x0 (0) > extended model = 0x0 (0) > (simple synth) = AMD Opteron / Athlon 64 / Athlon 64 FX / Sempron / Turion / Athlon Neo / Dual Core Opteron / Athlon 64 X2 / Athlon 64 FX / mobile Athlon 64 / mobile Sempron / mobile Athlon XP-M (DP) (unknown model) > miscellaneous (1/ebx): > process local APIC physical ID = 0x1 (1) > cpu count = 0x0 (0) > CLFLUSH line size = 0x8 (8) > brand index = 0x0 (0) > brand id = 0x00 (0): unknown > feature information (1/edx): > x87 FPU on chip = true > virtual-8086 mode enhancement = true > debugging extensions = true > page size extensions = true > time stamp counter = true > RDMSR and WRMSR support = true > physical address extensions = true > machine check exception = true > CMPXCHG8B inst. = true > APIC on chip = true > SYSENTER and SYSEXIT = true > memory type range registers = true > PTE global bit = true > machine check architecture = true > conditional move/compare instruction = true > page attribute table = true > page size extension = true > processor serial number = false > CLFLUSH instruction = true > debug store = false > thermal monitor and clock ctrl = false > MMX Technology = true > FXSAVE/FXRSTOR = true > SSE extensions = true > SSE2 extensions = true > self snoop = false > hyper-threading / multi-core supported = false > therm. monitor = false > IA64 = false > pending break event = false > feature information (1/ecx): > PNI/SSE3: Prescott New Instructions = true > PCLMULDQ instruction = false > 64-bit debug store = false > MONITOR/MWAIT = false > CPL-qualified debug store = false > VMX: virtual machine extensions = false > SMX: safer mode extensions = false > Enhanced Intel SpeedStep Technology = false > thermal monitor 2 = false > SSSE3 extensions = false > context ID: adaptive or shared L1 data = false > FMA instruction = false > CMPXCHG16B instruction = true > xTPR disable = false > perfmon and debug = false > process context identifiers = false > direct cache access = false > SSE4.1 extensions = false > SSE4.2 extensions = false > extended xAPIC support = false > MOVBE instruction = false > POPCNT instruction = true > time stamp counter deadline = false > AES instruction = false > XSAVE/XSTOR states = false > OS-enabled XSAVE/XSTOR = false > AVX: advanced vector extensions = false > F16C half-precision convert instruction = false > RDRAND instruction = false > hypervisor guest status = true > cache and TLB information (2): > 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines > 0x30: L1 cache: 32K, 8-way, 64 byte lines > 0x2c: L1 data cache: 32K, 8-way, 64 byte lines > processor serial number: 0000-0F61-0000-0000-0000-0000 > deterministic cache parameters (4): > --- cache 0 --- > cache type = data cache (1) > cache level = 0x1 (1) > self-initializing cache level = true > fully associative cache = false > extra threads sharing this cache = 0x0 (0) > extra processor cores on this die = 0x0 (0) > system coherency line size = 0x3f (63) > physical line partitions = 0x0 (0) > ways of associativity = 0x7 (7) > WBINVD/INVD behavior on lower caches = true > inclusive to lower caches = false > complex cache indexing = false > number of sets - 1 (s) = 63 > --- cache 1 --- > cache type = instruction cache (2) > cache level = 0x1 (1) > self-initializing cache level = true > fully associative cache = false > extra threads sharing this cache = 0x0 (0) > extra processor cores on this die = 0x0 (0) > system coherency line size = 0x3f (63) > physical line partitions = 0x0 (0) > ways of associativity = 0x7 (7) > WBINVD/INVD behavior on lower caches = true > inclusive to lower caches = false > complex cache indexing = false > number of sets - 1 (s) = 63 > --- cache 2 --- > cache type = unified cache (3) > cache level = 0x2 (2) > self-initializing cache level = true > fully associative cache = false > extra threads sharing this cache = 0x0 (0) > extra processor cores on this die = 0x0 (0) > system coherency line size = 0x3f (63) > physical line partitions = 0x0 (0) > ways of associativity = 0xf (15) > WBINVD/INVD behavior on lower caches = true > inclusive to lower caches = false > complex cache indexing = false > number of sets - 1 (s) = 4095 > MONITOR/MWAIT (5): > smallest monitor-line size (bytes) = 0x0 (0) > largest monitor-line size (bytes) = 0x0 (0) > enum of Monitor-MWAIT exts supported = true > supports intrs as break-event for MWAIT = true > number of C0 sub C-states using MWAIT = 0x0 (0) > number of C1 sub C-states using MWAIT = 0x0 (0) > number of C2 sub C-states using MWAIT = 0x0 (0) > number of C3 sub C-states using MWAIT = 0x0 (0) > number of C4 sub C-states using MWAIT = 0x0 (0) > number of C5 sub C-states using MWAIT = 0x0 (0) > number of C6 sub C-states using MWAIT = 0x0 (0) > number of C7 sub C-states using MWAIT = 0x0 (0) > hypervisor_id = "KVMKVMKVM " > hypervisor features (0x40000001/eax): > kvmclock available at MSR 0x11 = true > delays unnecessary for PIO ops = true > mmu_op = false > kvmclock available a MSR 0x4b564d00 = true > async pf enable available by MSR = true > steal clock supported = true > guest EOI optimization enabled = true > stable: no guest per-cpu warps expected = true > extended processor signature (0x80000001/eax): > family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15) > model = 0x6 (6) > stepping id = 0x1 (1) > extended family = 0x0 (0) > extended model = 0x0 (0) > (simple synth) = AMD Opteron / Athlon 64 / Athlon 64 FX / Sempron / Turion / Athlon Neo / Dual Core Opteron / Athlon 64 X2 / Athlon 64 FX / mobile Athlon 64 / mobile Sempron / mobile Athlon XP-M (DP) (unknown model) > extended feature flags (0x80000001/edx): > x87 FPU on chip = true > virtual-8086 mode enhancement = true > debugging extensions = true > page size extensions = true > time stamp counter = true > RDMSR and WRMSR support = true > physical address extensions = true > machine check exception = true > CMPXCHG8B inst. = true > APIC on chip = true > SYSCALL and SYSRET instructions = true > memory type range registers = true > global paging extension = true > machine check architecture = true > conditional move/compare instruction = true > page attribute table = true > page size extension = true > multiprocessing capable = false > no-execute page protection = true > AMD multimedia instruction extensions = true > MMX Technology = true > FXSAVE/FXRSTOR = true > SSE extensions = true > 1-GB large page support = true > RDTSCP = false > long mode (AA-64) = true > 3DNow! instruction extensions = true > 3DNow! instructions = true > extended brand id (0x80000001/ebx): > raw = 0x0 (0) > BrandId = 0x0 (0) > BrandTableIndex = 0x0 (0) > NN = 0x0 (0) > AMD feature flags (0x80000001/ecx): > LAHF/SAHF supported in 64-bit mode = true > CMP Legacy = true > SVM: secure virtual machine = true > extended APIC space = false > AltMovCr8 = true > LZCNT advanced bit manipulation = true > SSE4A support = true > misaligned SSE mode = true > 3DNow! PREFETCH/PREFETCHW instructions = true > OS visible workaround = true > instruction based sampling = false > XOP support = false > SKINIT/STGI support = false > watchdog timer support = false > lightweight profiling support = false > 4-operand FMA instruction = false > NodeId MSR C001100C = false > TBM support = false > topology extensions = false > brand = "AMD Opteron 23xx (Gen 3 Class Opteron)" > L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): > instruction # entries = 0xff (255) > instruction associativity = 0x1 (1) > data # entries = 0xff (255) > data associativity = 0x1 (1) > L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): > instruction # entries = 0xff (255) > instruction associativity = 0x1 (1) > data # entries = 0xff (255) > data associativity = 0x1 (1) > L1 data cache information (0x80000005/ecx): > line size (bytes) = 0x40 (64) > lines per tag = 0x1 (1) > associativity = 0x2 (2) > size (Kb) = 0x40 (64) > L1 instruction cache information (0x80000005/edx): > line size (bytes) = 0x40 (64) > lines per tag = 0x1 (1) > associativity = 0x2 (2) > size (Kb) = 0x40 (64) > L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): > instruction # entries = 0x0 (0) > instruction associativity = L2 off (0) > data # entries = 0x0 (0) > data associativity = L2 off (0) > L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): > instruction # entries = 0x200 (512) > instruction associativity = 4-way (4) > data # entries = 0x200 (512) > data associativity = 4-way (4) > L2 unified cache information (0x80000006/ecx): > line size (bytes) = 0x40 (64) > lines per tag = 0x1 (1) > associativity = 16-way (8) > size (Kb) = 0x200 (512) > L3 cache information (0x80000006/edx): > line size (bytes) = 0x0 (0) > lines per tag = 0x0 (0) > associativity = L2 off (0) > size (in 512Kb units) = 0x0 (0) > Advanced Power Management Features (0x80000007/edx): > temperature sensing diode = false > frequency ID (FID) control = false > voltage ID (VID) control = false > thermal trip (TTP) = false > thermal monitor (TM) = false > software thermal control (STC) = false > 100 MHz multiplier control = false > hardware P-State control = false > TscInvariant = false > Physical Address and Linear Address Size (0x80000008/eax): > maximum physical address bits = 0x28 (40) > maximum linear (virtual) address bits = 0x30 (48) > maximum guest physical address bits = 0x0 (0) > Logical CPU cores (0x80000008/ecx): > number of CPU cores - 1 = 0x0 (0) > ApicIdCoreIdSize = 0x0 (0) > (instruction supported synth): > CMPXCHG8B = true > conditional move/compare = true > PREFETCH/PREFETCHW = true > (multi-processing synth): none > (multi-processing method): AMD > (synth) = AMD Opteron / Athlon 64 / Athlon 64 FX / Sempron / Turion / Athlon Neo / Dual Core Opteron / Athlon 64 X2 / Athlon 64 FX / mobile Athlon 64 / mobile Sempron / mobile Athlon XP-M (DP) (unknown model)
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