Bug 1480494
Summary: | ivshmem-plain bar0 registers can be written with 'Haswell-noTSX' cpu | ||
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Product: | Red Hat Enterprise Linux 7 | Reporter: | tiama |
Component: | qemu-kvm-rhev | Assignee: | Markus Armbruster <armbru> |
Status: | CLOSED NOTABUG | QA Contact: | Pei Zhang <pezhang> |
Severity: | medium | Docs Contact: | |
Priority: | medium | ||
Version: | 7.5 | CC: | chayang, ehabkost, juzhang, knoel, pezhang, virt-maint |
Target Milestone: | rc | ||
Target Release: | --- | ||
Hardware: | Unspecified | ||
OS: | Linux | ||
Whiteboard: | |||
Fixed In Version: | Doc Type: | If docs needed, set a value | |
Doc Text: | Story Points: | --- | |
Clone Of: | Environment: | ||
Last Closed: | 2017-08-14 16:00:07 UTC | Type: | Bug |
Regression: | --- | Mount Type: | --- |
Documentation: | --- | CRM: | |
Verified Versions: | Category: | --- | |
oVirt Team: | --- | RHEL 7.3 requirements from Atomic Host: | |
Cloudforms Team: | --- | Target Upstream Version: | |
Embargoed: |
Description
tiama
2017-08-11 09:12:07 UTC
Works as designed as far as I can tell. qemu-kvm-rhev-2.9.0 provides a rev 1 device. Quoting the device specification[*] BAR 0 contains the following registers: Offset Size Access On reset Function 0 4 read/write 0 Interrupt Mask bit 0: peer interrupt (rev 0) reserved (rev 1) bit 1..31: reserved 4 4 read/write 0 Interrupt Status bit 0: peer interrupt (rev 0) reserved (rev 1) bit 1..31: reserved 8 4 read-only 0 or ID IVPosition 12 4 write-only N/A Doorbell bit 0..15: vector bit 16..31: peer ID 16 240 none N/A reserved Software should only access the registers as specified in column "Access". Reserved bits should be ignored on read, and preserved on write. [...] IVPosition Register: if the device is not configured for interrupts, this is zero. Else, it is the device's ID (between 0 and 65535). [...] Doorbell Register: writing this register requests to interrupt a peer. The written value's high 16 bits are the ID of the peer to interrupt, and its low 16 bits select an interrupt vector. If the device is not configured for interrupts, the write is ignored. Step 5 writes 16 random bytes to bar#0 offset 0..15, then reads them back. Writing random crap to the first eight bytes (registers Interrupt Mask and Status) isn't nice, but it works. Reading them happens to yield exactly the crap you wrote. The device ignores the write to the the next four bytes (register IVPosition). Reading them yields zero, as the device isn't configured for interrupts. The device ignores the write to the next four bytes (register Doorbell), as it's not configured for interrupts. Reading them happens to yield zero. I'm therefore closing this NOTABUG. If you think it is a bug, please explain why. Thanks! [*] https://git.qemu.org/gitweb.cgi?p=qemu.git;a=blob;f=docs/specs/ivshmem-spec.txt;h=a1f54997962aef16cd2b61f76976dfe811935382;hb=83c3a1f61673ef554facf4d6d29ed56c5a219f9d |