Contemporary Intel processors integrate a piece of logic known as a VR (Voltage Regulator), used to manage the amount of power provided to certain parts of the processor. It is this logic that is responsible for adjusting voltage whenever certain parts of the design are power gated (disabled), or enabled. An example of this is the AVX unit on recent processors, which will be power gated when not recently used. A defect in the design of the FIVR allows erroneous response to so-called 0mv (no adjustment) messages to the FIVR under certain conditions.
A microcode update will disable the FIVR 0mv adjustment logic.
Statement:
Red Hat Product Security is aware of this issue. Updates will be released as they become available. For additional information, please refer to the Red Hat Knowledgebase article: https://access.redhat.com/solutions/2019-microcode-nov