Bug 214202
| Summary: | Intel Core2 has L2 cache, not L3 | ||
|---|---|---|---|
| Product: | Red Hat Enterprise Linux 5 | Reporter: | Jakub Jelinek <jakub> |
| Component: | x86info | Assignee: | Dave Jones <davej> |
| Status: | CLOSED WONTFIX | QA Contact: | |
| Severity: | medium | Docs Contact: | |
| Priority: | medium | ||
| Version: | 5.0 | CC: | drepper, jakub, pfrields |
| Target Milestone: | --- | ||
| Target Release: | --- | ||
| Hardware: | All | ||
| OS: | Linux | ||
| Whiteboard: | |||
| Fixed In Version: | Doc Type: | Bug Fix | |
| Doc Text: | Story Points: | --- | |
| Clone Of: | Environment: | ||
| Last Closed: | 2014-06-02 13:02:28 UTC | Type: | --- |
| Regression: | --- | Mount Type: | --- |
| Documentation: | --- | CRM: | |
| Verified Versions: | Category: | --- | |
| oVirt Team: | --- | RHEL 7.3 requirements from Atomic Host: | |
| Cloudforms Team: | --- | Target Upstream Version: | |
| Embargoed: | |||
sigh, yet more special cases. Not sure of a clean way to do this without significantly rewriting the cache handling. We could be really cheap, and just print out something like "L2/L3 unified cache" or similar, but that feels like a cop-out. This bug/component is not included in scope for RHEL-5.11.0 which is the last RHEL5 minor release. This Bugzilla will soon be CLOSED as WONTFIX (at the end of RHEL5.11 development phase (Apr 22, 2014)). Please contact your account manager or support representative in case you need to escalate this bug. Thank you for submitting this request for inclusion in Red Hat Enterprise Linux 5. We've carefully evaluated the request, but are unable to include it in RHEL5 stream. If the issue is critical for your business, please provide additional business justification through the appropriate support channels (https://access.redhat.com/site/support). The needinfo request[s] on this closed bug have been removed as they have been unresolved for 1000 days |
Family: 6 Model: 15 Stepping: 5 Type: 0 Brand: 0 CPU Model: Core 2 Extreme E6800/X6800 [B1] Original OEM Feature flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh ds acpi mmx fxsr sse sse2 ss ht tm pbe sse3 monitor ds-cpl vmx est tm2 ssse3 cx16 xTPR Extended feature flags: SYSCALL xd em64t lahf_lm Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L3 unified cache: 4MB, 16-way associative. 64 byte line size. TLB info Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4MB pages, 4-way associative, 32 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. 64 byte prefetching. The physical package supports 2 logical processors But this CPU doesn't have L3 cache and no L2, it has 4MB L2 cache. According to Ulrich, current Intel manuals say: 49h 3-level cache: 4 MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family F, Model 6) and 2-level cache: 4 MB, 16-way set associative, 64-byte line size