Bug 2182742

Summary:	[RFE] - lscpu - please add support for Intel Sapphire Rapids HBM Cache mode
Product:	Red Hat Enterprise Linux 9	Reporter:	Jiri Hladky <jhladky>
Component:	util-linux	Assignee:	Karel Zak <kzak>
Status:	ASSIGNED ---	QA Contact:	Radka Brychtova <rskvaril>
Severity:	unspecified	Docs Contact:
Priority:	unspecified
Version:	9.3	CC:	darcari, jhladky
Target Milestone:	rc	Keywords:	FutureFeature
Target Release:	---
Hardware:	Unspecified
OS:	Unspecified
Whiteboard:
Fixed In Version:		Doc Type:	If docs needed, set a value
Doc Text:		Story Points:	---
Clone Of:		Environment:
Last Closed:		Type:	Bug
Regression:	---	Mount Type:	---
Documentation:	---	CRM:
Verified Versions:		Category:	---
oVirt Team:	---	RHEL 7.3 requirements from Atomic Host:
Cloudforms Team:	---	Target Upstream Version:
Embargoed:

Description Jiri Hladky 2023-03-29 14:04:37 UTC

Description of problem:

Hello, 

Intel Sapphire Rapids platform introduces HBM-enabled CPUs. HBM can be operated in Cached Mode - HBM caches DDR.
https://www.intel.ca/content/www/ca/en/products/docs/processors/xeon/xeon-max-series-product-brief.html

lscpu gives information about the CPU caches but does not provide any info about the HBM Cache.

We want to enhance lscpu to close this gap. 

FYI, lstopo from hwloc package shows the HBM Cache (MemCache line below, generated on intel-eaglestream-spr-17.khw3.lab.eng.bos.redhat.com server). 
$lstopo 
Machine (1007GB total)
  Package L#0
    MemCache L#0 (64GB)
      NUMANode L#0 (P#0 503GB)

In Kernel, the Cache is described in sysfs as "memory_side_cache" dir:
/sys/devices/system/node/node0/memory_side_cache/index1

Please also refer to the documentation here:
https://docs.kernel.org/admin-guide/mm/numaperf.html

Thanks a lot
Jirka

Comment 2 Karel Zak 2023-08-09 09:36:23 UTC

This should be implemented upstream, rather than as RHEL specific patch.

Added to the upstream issue tracker: https://github.com/util-linux/util-linux/issues/2426