Bug 2223287

Summary:	glibc: Intel TDX enablement (cache information in particular)
Product:	Red Hat Enterprise Linux 9	Reporter:	Florian Weimer <fweimer>
Component:	glibc	Assignee:	glibc team <glibc-bugzilla>
Status:	CLOSED MIGRATED	QA Contact:	qe-baseos-tools-bugs
Severity:	unspecified	Docs Contact:
Priority:	unspecified
Version:	9.3	CC:	ashankar, codonell, dj, fweimer, pfrankli, sipoyare
Target Milestone:	rc	Keywords:	Bugfix, MigratedToJIRA, Triaged
Target Release:	---
Hardware:	Unspecified
OS:	Unspecified
Whiteboard:
Fixed In Version:		Doc Type:	If docs needed, set a value
Doc Text:		Story Points:	---
Clone Of:		Environment:
Last Closed:	2023-08-11 14:43:46 UTC	Type:	Bug
Regression:	---	Mount Type:	---
Documentation:	---	CRM:
Verified Versions:		Category:	---
oVirt Team:	---	RHEL 7.3 requirements from Atomic Host:
Cloudforms Team:	---	Target Upstream Version:
Embargoed:

Description Florian Weimer 2023-07-17 08:49:03 UTC

Current upstream glibc reports all-zero for cache size information on Intel TDX (at least in Azure TDX implementation; Intel's KVM port reportedly behaves similarly though).

This may need a fix within glibc. I started an upstream discussion:

Missing cache information on x86-64 under Intel TDX (glibc bug 30643)
<https://inbox.sourceware.org/libc-alpha/87mszv7x0l.fsf@oldenburg.str.redhat.com/>

This is related to Red Hat bug 2177705, which contains an incomplete fix attempt.

Comment 1 Florian Weimer 2023-07-17 08:59:09 UTC

Note that this issue (not the crash from bug 2177705) is present in glibc-2.28-225.el8.x86_64 as well.

# getconf -a | grep CACHE
LEVEL1_ICACHE_SIZE                 0
LEVEL1_ICACHE_ASSOC                0
LEVEL1_ICACHE_LINESIZE             0
LEVEL1_DCACHE_SIZE                 0
LEVEL1_DCACHE_ASSOC                0
LEVEL1_DCACHE_LINESIZE             0
LEVEL2_CACHE_SIZE                  0
LEVEL2_CACHE_ASSOC                 0
LEVEL2_CACHE_LINESIZE              0
LEVEL3_CACHE_SIZE                  0
LEVEL3_CACHE_ASSOC                 0
LEVEL3_CACHE_LINESIZE              0
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0

This means if this is fixed on the Intel TDX side, we need to backport this change into RHEL 8 as well. I'm not cloning this bug yet; let's wait for the outcome of the upstream discussion.

Comment 4 RHEL Program Management 2023-08-11 14:43:46 UTC

This BZ has been automatically migrated to the issues.redhat.com Red Hat Issue Tracker. All future work related to this report will be managed there.

To find the migrated issue, look in the "Links" section for a direct link to the new issue location. The issue key will have an icon of 2 footprints next to it, and begin with "RHEL-" followed by an integer.  You can also find this issue by visiting https://issues.redhat.com/issues/?jql= and searching the "Bugzilla Bug" field for this BZ's number, e.g. a search like:

"Bugzilla Bug" = 1234567

In the event you have trouble locating or viewing this issue, you can file an issue by sending mail to rh-issues.