Bug 2495939 (CVE-2026-53354)

Summary: CVE-2026-53354 kernel: arm64: errata: Mitigate TLBI errata on various Arm CPUs
Product: [Other] Security Response Reporter: OSIDB Bzimport <bzimport>
Component: vulnerabilityAssignee: Product Security <prodsec-ir-bot>
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Priority: medium    
Version: unspecifiedCC: rhel-process-autobot, watson-tool-maintainers
Target Milestone: ---Keywords: Security
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Hardware: All   
OS: Linux   
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A flaw was found in the Linux kernel, affecting systems running on certain Arm processors. This vulnerability involves an issue with how the system handles Translation Lookaside Buffer Invalidation (TLBI) operations. Specifically, a sequence of operations intended to invalidate memory translations may complete before all related memory writes are fully observed across the system. This could lead to inconsistencies in memory access, although the TLB entries themselves are correctly invalidated.
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Description OSIDB Bzimport 2026-07-01 14:02:19 UTC 
In the Linux kernel, the following vulnerability has been resolved:

arm64: errata: Mitigate TLBI errata on various Arm CPUs

A number of CPUs developed by Arm suffer from errata whereby a broadcast
TLBI;DSB sequence may complete before the global observation of writes
which are translated by an affected TLB entry.

These errata ONLY affect the completion of memory accesses which have
been translated by an invalidated TLB entry, and these errata DO NOT
affect the actual invalidation of TLB entries. TLB entries are removed
correctly.

This issue has been assigned CVE ID CVE-2025-10263.

To mitigate this issue, Arm recommends that software follows any
affected TLBI;DSB sequence with an additional TLBI;DSB, which will
ensure that all memory write effects affected by the first TLBI have
been globally observed. The additional TLBI can use any operation that
is broadcast to affected CPUs, and the additional DSB can use any option
that is sufficient to complete the additional TLBI.

The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate
the issue. Enable this workaround for affected CPUs, and update the
silicon errata documentation accordingly.

Note that due to the manner in which Arm develops IP and tracks errata,
some CPUs share a common erratum number.
Comment 1 Mauro Matteo Cascella 2026-07-01 18:02:23 UTC 
Upstream advisory:
https://lore.kernel.org/linux-cve-announce/2026070147-CVE-2026-53354-f606@gregkh/T