Bug 2535352 (CVE-2026-89812)

Summary: CVE-2026-89812 kernel: drm/amdgpu: force complete the MES ring fences on reset
Product: [Other] Security Response Reporter: OSIDB Bzimport <bzimport>
Component: vulnerabilityAssignee: Product Security DevOps Team <prodsec-dev>
Status: NEW --- QA Contact:
Severity: low Docs Contact:
Priority: low    
Version: unspecifiedCC: akhatavk, aos-team-art-private, asdas, dpaolell, jdelft, jupierce, lgarciaa, mbiarnes, ppalepu, ppostler, prdhamdh, rhel-process-autobot, sghai, sidsharm, suppawar, vlaad, watson-tool-maintainers
Target Milestone: ---Keywords: Security
Target Release: ---   
Hardware: All   
OS: Linux   
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A flaw was found in the Linux kernel's AMD GPU (Graphics Processing Unit) driver. When the Multimedia Engine Scheduler (MES) ring stops responding and a system reset is triggered, the MES ring fences are not properly completed. This can lead to the system becoming unresponsive after resuming from the reset, requiring a hard reboot to restore functionality. This vulnerability can result in a denial of service for a local user.
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oVirt Team: --- RHEL 7.3 requirements from Atomic Host:
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Description OSIDB Bzimport 2026-09-16 12:14:46 UTC 
In the Linux kernel, the following vulnerability has been resolved:

drm/amdgpu: force complete the MES ring fences on reset

The MES scheduler ring has no drm scheduler (no_scheduler = true), so it is
skipped by the force-completion loop in amdgpu_device_pre_asic_reset(). It uses
a polling fence whose hw value lives in wb (GTT) memory and survives a MODE1
reset, while fence_drv.sync_seq keeps advancing for every packet.

When the reset is triggered because MES itself stopped responding, the
timed-out packets advance sync_seq past the last hw fence value MES wrote.
After resume the first MES submission polls forever on a seq that is never
written back, failing the resume and wedging the box on a second reset:

  amdgpu: MES ring buffer is full.
  amdgpu: *ERROR* ring gfx_0.0.0 test failed (-110)
  amdgpu: resume of IP block <gfx_v11_0> failed -110
  amdgpu: GPU reset end with ret = -110

Force complete the MES scheduler ring fences together with the scheduler rings
so their hw fence is realigned to sync_seq.

v2: cover all XCCs (one scheduler ring each), not just mes.ring[0].
Comment 1 Mauro Matteo Cascella 2026-09-21 16:02:58 UTC 
Upstream advisory:
https://git.kernel.org/pub/scm/linux/security/vulns.git/plain/cve/published/2026/CVE-2026-89812.mbox