Bug 13805 - patch to add PCI-X capability printing
patch to add PCI-X capability printing
Status: CLOSED RAWHIDE
Product: Red Hat Linux
Classification: Retired
Component: pciutils (Show other bugs)
7.1
i386 Linux
medium Severity medium
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: ---
Assigned To: Bill Nottingham
:
Depends On:
Blocks:
  Show dependency treegraph
 
Reported: 2000-07-12 12:06 EDT by Matt Domsch
Modified: 2014-03-16 22:14 EDT (History)
1 user (show)

See Also:
Fixed In Version:
Doc Type: Bug Fix
Doc Text:
Story Points: ---
Clone Of:
Environment:
Last Closed: 2000-07-12 12:22:27 EDT
Type: ---
Regression: ---
Mount Type: ---
Documentation: ---
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Category: ---
oVirt Team: ---
RHEL 7.3 requirements from Atomic Host:
Cloudforms Team: ---


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Description Matt Domsch 2000-07-12 12:06:48 EDT
I don't have any PCI-X hardware to test this with yet, but here's my first 
pass at a patch to add describing the PCI-X capabilities to lspci.

Thanks,
Matt Domsch
Dell Enterprise Systems Group
Linux Development Team


diff -burN pciutils-2.1.8.orig/lib/header.h pciutils-2.1.8/lib/header.h
--- pciutils-2.1.8.orig/lib/header.h	Mon May  1 16:34:49 2000
+++ pciutils-2.1.8/lib/header.h	Sun Jul  9 13:41:24 2000
@@ -185,6 +185,7 @@
 #define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
 #define  PCI_CAP_ID_MSI		0x05	/* Message Signalled 
Interrupts */
 #define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
+#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
 #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 
bits) */
 #define PCI_CAP_SIZEOF		4
@@ -256,6 +257,56 @@
 #define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if 
PCI_MSI_FLAGS_64BIT set) */
 #define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-
bit devices */
 #define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-
bit devices */
+
+/* PCI-X */
+#define PCI_PCIX_COMMAND                                                
2  /* Command register offset */
+#define PCI_PCIX_COMMAND_DPERE                                     
0x0001  /* Data Parity Error Recover Enable */
+#define PCI_PCIX_COMMAND_ERO                                       
0x0002  /* Enable Relaxed Ordering */
+#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT                   
0x000c  /* Maximum Memory Read Byte Count */
+#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS               
0x0070  
+#define PCI_PCIX_COMMAND_RESERVED                                   0xf80
+#define PCI_PCIX_STATUS                                                 
4  /* Status register offset */
+#define PCI_PCIX_STATUS_FUNCTION                               0x00000007
+#define PCI_PCIX_STATUS_DEVICE                                 0x000000f8
+#define PCI_PCIX_STATUS_BUS                                    0x0000ff00
+#define PCI_PCIX_STATUS_64BIT                                  0x00010000
+#define PCI_PCIX_STATUS_133MHZ                                 0x00020000
+#define PCI_PCIX_STATUS_SC_DISCARDED                           
0x00040000 /* Split Completion Discarded */
+#define PCI_PCIX_STATUS_UNEXPECTED_SC                          
0x00080000 /* Unexpected Split Completion */
+#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY                      
0x00100000 /* 0 = simple device, 1 = bridge device */
+#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT       
0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
+#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS   0x03800000
+#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE      0x1c000000
+#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS                       
0x20000000 /* Received Split Completion Error Message */
+#define PCI_PCIX_STATUS_RESERVED         0xc0000000
+#define PCI_PCIX_SIZEOF		4
+
+/* PCI-X Bridges */
+#define PCI_PCIX_BRIDGE_SEC_STATUS                                      
2  /* Secondary bus status register offset */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT                           0x0001
+#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ                          0x0002
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED                    
0x0004 /* Split Completion Discarded on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC                   
0x0008 /* Unexpected Split Completion on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN                      
0x0010 /* Split Completion Overrun on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED           0x0020
+#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ                      0x01c0
+#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED                        0xfe00
+#define PCI_PCIX_BRIDGE_STATUS                                          
4 /* Primary bus status register offset */
+#define PCI_PCIX_BRIDGE_STATUS_FUNCTION                        0x00000007
+#define PCI_PCIX_BRIDGE_STATUS_DEVICE                          0x000000f8
+#define PCI_PCIX_BRIDGE_STATUS_BUS                             0x0000ff00
+#define PCI_PCIX_BRIDGE_STATUS_64BIT                           0x00010000
+#define PCI_PCIX_BRIDGE_STATUS_133MHZ                          0x00020000
+#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED                    
0x00040000 /* Split Completion Discarded */
+#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC                   
0x00080000 /* Unexpected Split Completion */
+#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN                      
0x00100000 /* Split Completion Overrun */
+#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED           0x00200000
+#define PCI_PCIX_BRIDGE_STATUS_RESERVED                        0xffc00000
+#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL                       
8 /* Upstream Split Transaction Register offset */
+#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL                    
12 /* Downstream Split Transaction Register offset */
+#define PCI_PCIX_BRIDGE_STR_CAPACITY                           0x0000ffff
+#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT                   0xffff0000
+#define PCI_PCIX_BRIDGE_SIZEOF 12
 
 /*
  * The PCI interface treats multi-function devices as independent
diff -burN pciutils-2.1.8.orig/lspci.c pciutils-2.1.8/lspci.c
--- pciutils-2.1.8.orig/lspci.c	Sat May 20 09:36:02 2000
+++ pciutils-2.1.8/lspci.c	Sun Jul  9 14:30:45 2000
@@ -457,6 +457,89 @@
 	 rate);
 }
 
+
+static void
+show_pcix_nobridge(struct device *d, int where)
+{
+  unsigned int command  = get_conf_word(d, where + PCI_PCIX_COMMAND);
+  unsigned long status  = get_conf_long(d, where + PCI_PCIX_STATUS);
+  printf("PCI-X non-bridge device.\n");
+  if (verbose < 2)
+    return;
+  printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
+	 FLAG(command, PCI_PCIX_COMMAND_DPERE),
+	 FLAG(command, PCI_PCIX_COMMAND_ERO),
+	 ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U),
+	 ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U));
+  printf("\t\tStatus: Bus=%lu Dev=%lu Func=%lu 64bit%c 133MHz%c SCD%c USC%
c, DC=%s, DMMRBC=%lu, DMOST=%lu, DMCRS=%lu, RSCEM%c",
+	 ((status >> 8) & 0xffU), // bus
+	 ((status >> 3) & 0x1fU), // dev
+	 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
+	 FLAG(status, PCI_PCIX_STATUS_64BIT),
+	 FLAG(status, PCI_PCIX_STATUS_133MHZ),
+	 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
+	 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
+	 ((status & 
PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
+	 ((status >> 21) & 3U),
+	 ((status >> 23) & 7U),
+	 ((status >> 26) & 7U),
+	 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS));
+}
+
+static void
+show_pcix_bridge(struct device *d, int where)
+{
+  unsigned int secstatus;
+  unsigned long status, upstcr, downstcr;
+  printf("PCI-X bridge device.\n");
+  if (verbose < 2)
+    return;
+  secstatus  = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
+  printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, 
SRD%c Freq=%d\n",
+	 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
+	 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
+	 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
+	 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
+	 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
+	 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
+	 ((secstatus >> 6) & 7));
+  status    = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
+  printf("\t\tStatus: Bus=%lu Dev=%lu Func=%lu 64bit%c 133MHz%c SCD%c USC%
c, SCO%c, SRD%c\n", 
+	 ((status >> 8) & 0xff), // bus
+	 ((status >> 3) & 0x1f), // dev
+	 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
+	 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
+	 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
+	 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
+	 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
+	 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
+	 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
+  upstcr = get_conf_long(d, where + 
PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
+  printf("\t\t: Upstream: Capacity=%lu, Commitment Limit=%lu\n",
+	 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
+	 (upstcr >> 16) & 0xffff);
+  downstcr = get_conf_long(d, where + 
PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
+  printf("\t\t: Downstream: Capacity=%lu, Commitment Limit=%lu\n",
+	 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
+	 (downstcr >> 16) & 0xffff);
+}
+
+static void
+show_pcix(struct device *d, int where)
+{
+  switch (d->dev->hdrtype) {
+  case PCI_HEADER_TYPE_NORMAL:
+    show_pcix_nobridge(d, where);
+    break;
+  case PCI_HEADER_TYPE_BRIDGE:
+    show_pcix_bridge(d, where);
+    break;
+  default:
+    break;
+  }
+}
+
+
 static void
 show_rom(struct device *d)
 {
@@ -558,6 +641,9 @@
 	      break;
 	    case PCI_CAP_ID_MSI:
 	      show_msi(d, where, cap);
+	      break;
+	    case PCI_CAP_ID_PCIX:
+	      show_pcix(d, where);
 	      break;
 	    default:
 	      printf("#%02x [%04x]\n", id, cap);
Comment 1 Bill Nottingham 2000-07-12 12:13:06 EDT
Is this the same one you posted to the list, or an updated version?
Comment 2 Matt Domsch 2000-07-12 12:17:01 EDT
Exactly the same as I posted to the list.
Comment 3 Bill Nottingham 2000-07-12 12:22:25 EDT
OK, then it's in pciutils-2.1.8-5.
Comment 4 Matt Domsch 2000-07-21 15:48:08 EDT
Winston Beta 4 includes pciutils-2.1.8-6, which includes this patch. Closed.

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