Red Hat Bugzilla – Bug 210595
PCI cache line set incorrectly was showed up in dmesg.
Last modified: 2007-11-16 20:14:46 EST
Description of problem:
PCI cache line size set incorrectly show up in dmesg. PCI cache line is ready
only, BIOS cannot modify it. But, why dmesg will try to set PCI cache line and
said set incorrectly. This issue only happened on RH3 64bit, other RHs don't
have this messeges.
Version-Release number of selected component (if applicable):
1.Boot to RH3 U7 64bit . 2.Check dmesg 3.Find the event log: "PCI: 00:02.1
cache line size set incorrectly (0 bytes) by BIOS/FW." "PCI: 00:02.1 cache
line size corrected to 64"
Steps to Reproduce:
Tested platform is AMD Opetron F processor, nVidia MCP55P chipset.
That sounds like a kernel or dmesg bug though, reassigning to kernel for now.
Read ya, Phil
Is there any update on it?
Removing bogus dependency on RHEL5 bug 226674.
John please do not create BZ dependencies across RHEL versions. It
does not make sense for a RHEL3 bug to be dependent on a RHEL5 bug.
sorry, typo adding bz 226674 to my tracker bug
This bug is filed against RHEL 3, which is in maintenance phase.
During the maintenance phase, only security errata and select mission
critical bug fixes will be released for enterprise products. Since
this bug does not meet that criteria, it is now being closed.
For more information of the RHEL errata support policy, please visit:
If you feel this bug is indeed mission critical, please contact your
support representative. You may be asked to provide detailed
information on how this bug is affecting you.