Bug 468515 - Review Request: verilator - A fast simulator for synthesizable verilog HDL
Review Request: verilator - A fast simulator for synthesizable verilog HDL
Status: CLOSED NOTABUG
Product: Fedora
Classification: Fedora
Component: Package Review (Show other bugs)
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All Linux
medium Severity medium
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Assigned To: Nobody's working on this, feel free to take it
Fedora Extras Quality Assurance
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Reported: 2008-10-25 10:08 EDT by Lane
Modified: 2008-10-25 10:16 EDT (History)
2 users (show)

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Doc Type: Bug Fix
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Last Closed: 2008-10-25 10:16:14 EDT
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Description Lane 2008-10-25 10:08:07 EDT
Spec URL: http://brooks.nu/~lane/verilator.spec
SRPM URL: http://brooks.nu/~lane/verilator-3.680-2.fc10.src.rpm
Description: 
Verilator is the fastest free Verilog HDL simulator. It compiles
synthesizable Verilog (not test-bench code!), plus some PSL,
SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of
primary concern, and is especially well suited to create executable
models of CPUs for embedded software design teams.

Because of systemc licensing issues, the verilator dependancies on
systemc are not included with this package.  This means the
perl-verilog, perl-systemc, and systemc functionality that is
integrated into verilator will only work if those packages are
installed separately.  This package, therefore, supports the verilog
features of verilator (including vcd generation via the --trace
option).
Comment 1 Lane 2008-10-25 10:16:14 EDT
I created this under the wrong bugzilla account by mistake.  Please delete this request as I will make the same request under the correct bugzilla account.

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