Spec URL: http://brooks.nu/~lane/verilator.spec SRPM URL: http://brooks.nu/~lane/verilator-3.680-2.fc10.src.rpm Description: Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Because of systemc licensing issues, the verilator dependancies on systemc are not included with this package. This means the perl-verilog, perl-systemc, and systemc functionality that is integrated into verilator will only work if those packages are installed separately. This package, therefore, supports the verilog features of verilator (including vcd generation via the --trace option).
I created this under the wrong bugzilla account by mistake. Please delete this request as I will make the same request under the correct bugzilla account.