Bug 518324 - dmidecode wrong on newer processors
Summary: dmidecode wrong on newer processors
Keywords:
Status: CLOSED NOTABUG
Alias: None
Product: Red Hat Enterprise Linux 5
Classification: Red Hat
Component: dmidecode
Version: 5.3
Hardware: All
OS: Linux
medium
medium
Target Milestone: rc
: ---
Assignee: Anton Arapov
QA Contact: BaseOS QE
URL:
Whiteboard:
Depends On:
Blocks:
TreeView+ depends on / blocked
 
Reported: 2009-08-19 20:54 UTC by Issue Tracker
Modified: 2018-10-27 15:50 UTC (History)
5 users (show)

Fixed In Version:
Doc Type: Bug Fix
Doc Text:
Clone Of:
Environment:
Last Closed: 2010-01-20 10:17:25 UTC


Attachments (Terms of Use)
dmi dump (3.95 KB, application/octet-stream)
2009-12-18 18:03 UTC, Kent Baxley
no flags Details

Description Issue Tracker 2009-08-19 20:54:08 UTC
Escalated to Bugzilla from IssueTracker

Comment 1 Issue Tracker 2009-08-19 20:54:10 UTC
Event posted on 08-19-2009 04:06pm EDT by woodard

From: tdhooge@llnl.gov
To: Ben Woodard <woodard@redhat.com>
Subject: dmidecode and AMD istanbul
Date: Wed, 19 Aug 2009 08:10:16 -0700
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Cc: Mark Grondona <mgrondona@llnl.gov>
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X-Scanned-By: MIMEDefang 2.67 on 10.5.11.20
X-Scanned-By: MIMEDefang 2.67 on 10.5.110.13

I think something is confussed in dmidecode. The AMD Istanbul has

L1 - 128KB * 6
L2 - 512KB * 6
L3 - 6MB

But I see this in dmidecode. I could be confused, but dmidecode / lshw seems 
to make sense to me for the Shanghai and Barcelona. See nodes hype[1-4]

Cache Information
        Socket Designation: L1-Cache
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Varies With Memory Address
        Location: Internal
        Installed Size: 1024 KB
        Maximum Size: 1024 KB

        Socket Designation: L2-Cache
        Configuration: Enabled, Not Socketed, Level 2
        Operational Mode: Varies With Memory Address
        Location: Internal
        Installed Size: 4096 KB
        Maximum Size: 4096 KB

        Socket Designation: L3-Cache
        Configuration: Enabled, Not Socketed, Level 3
        Operational Mode: Varies With Memory Address
        Location: Internal
        Installed Size: 96 KB
        Maximum Size: 96 KB

----------
The problem seems a bit worse than Trent indicates. In particular look at the L3-Cache.

Dual-Core AMD Opteron(tm) Processor 8216
According to: http://products.amd.com/en-us/OpteronCPUDetail.aspx?id=328&f1=&f2=&f3=&f4=&f5=&f6=&f7=&f8=&f9=&f10=&
L1 Cache Size (KB) 128 * 2
L2 Cache Size (KB) 1024 * 2

Cache Information
        Socket Designation: L1-Cache
        Installed Size: 128 KB
Cache Information
        Socket Designation: L2-Cache
        Installed Size: 2048 KB
Cache Information
        Socket Designation: L3-Cache
        Configuration: Disabled, Not Socketed, Level 3
        Installed Size: 0 KB

Looks right.

Quad-Core AMD Opteron(tm) Processor 8350
http://products.amd.com/en-us/OpteronCPUDetail.aspx?id=334&f1=&f2=&f3=&f4=&f5=&f6=&f7=&f8=&f9=&f10=&
L1 Cache Size (KB) 128 * 4
L2 Cache Size (KB) 512 * 4
L3 Cache Size (KB) 2048
Cache Information
        Socket Designation: L1-Cache
        Installed Size: 512 KB
Cache Information
        Socket Designation: L2-Cache
        Installed Size: 2048 KB
Cache Information
        Socket Designation: L3-Cache
        Installed Size: 16 KB

Note that L3 is wrong.

But on: 

Then on the Six-Core AMD Opteron(tm) Processor 8435
According to: http://products.amd.com/en-us/OpteronCPUDetail.aspx?id=554&f1=&f2=&f3=&f4=&f5=&f6=&f7=&f8=&f9=&f10=&
L1 Cache Size (KB) 128 * 6 = 768KB
L2 Cache Size (KB) 512 * 6 = 3072KB
L3 Cache Size (KB) 6144

From dmidecode:
Cache Information
        Socket Designation: L1-Cache
        Installed Size: 1024 KB

Cache Information
        Socket Designation: L2-Cache
        Installed Size: 4096 KB

Cache Information
        Socket Designation: L3-Cache
        Installed Size: 96 KB

So since dmidecode seems to multiply the caches for the various cores together all these numbers are wrong.
This event sent from IssueTracker by kbaxley  [LLNL (HPC)]
 issue 332468

Comment 2 Issue Tracker 2009-08-19 20:54:12 UTC
Event posted on 08-19-2009 04:37pm EDT by woodard

hype1@ben:rpm -qf /usr/sbin/dmidecode 
dmidecode-2.7-1.28.2.el5 
Will try dmidecode-2.9-1.el5


woodard assigned to issue for LLNL (HPC).

This event sent from IssueTracker by kbaxley  [LLNL (HPC)]
 issue 332468

Comment 3 Issue Tracker 2009-08-19 20:54:13 UTC
Event posted on 08-19-2009 04:40pm EDT by woodard

hype1@ben:sudo rpm -Uvh dmidecode-2.9-1.el5.x86_64.rpm 
Password: 
warning: dmidecode-2.9-1.el5.x86_64.rpm: Header V3 DSA signature: NOKEY,
key ID 897da07a
Preparing...                ###########################################
[100%]
   1:dmidecode              ###########################################
[100%]
hype1@ben:sudo /usr/sbin/dmidecode | less
hype1@ben:rpm -q dmidecode
dmidecode-2.9-1.el5

Same problem:
Cache Information
        Socket Designation: L1-Cache
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Varies With Memory Address
        Location: Internal
        Installed Size: 1024 KB
        Maximum Size: 1024 KB
        Supported SRAM Types:
                Pipeline Burst
        Installed SRAM Type: Pipeline Burst
        Speed: Unknown
        Error Correction Type: Single-bit ECC
        System Type: Data
        Associativity: 4-way Set-associative

Handle 0x0006, DMI type 7, 19 bytes
Cache Information
        Socket Designation: L2-Cache
        Configuration: Enabled, Not Socketed, Level 2
        Operational Mode: Varies With Memory Address
        Location: Internal
        Installed Size: 4096 KB
        Maximum Size: 4096 KB
        Supported SRAM Types:
                Pipeline Burst
        Installed SRAM Type: Pipeline Burst
        Speed: Unknown
        Error Correction Type: Single-bit ECC
        System Type: Unified
        Associativity: 4-way Set-associative

Handle 0x0007, DMI type 7, 19 bytes
Cache Information
        Socket Designation: L3-Cache
        Configuration: Enabled, Not Socketed, Level 3
        Operational Mode: Varies With Memory Address
        Location: Internal
        Installed Size: 96 KB
        Maximum Size: 96 KB
        Supported SRAM Types:
                Pipeline Burst
        Installed SRAM Type: Pipeline Burst
        Speed: Unknown
        Error Correction Type: Single-bit ECC
        System Type: Unified
        Associativity: 4-way Set-associative



This event sent from IssueTracker by kbaxley  [LLNL (HPC)]
 issue 332468

Comment 4 Jarod Wilson 2009-08-27 13:29:42 UTC
Please pass along the just-built dmidecode-2.10-1.el5 package for testing. With luck, it already fixes all the problems. If not, we have some additional work to do...

Comment 7 Anton Arapov 2009-11-09 10:56:49 UTC
hmm... I do not see any logic in the sources that counts the cache size by multiplying by the number of cores, could be the incorrect dmi data, could you provide the dump file generated by # dmidecode --dump-bin FILE

thanks,

Comment 10 Anton Arapov 2009-11-18 08:08:27 UTC
Ben, can you provide kernel-2.6.18-174.el5 kernel to Customer for test? I'm not sure whether the patch(bug 526315) there will fix this bug... Some additional bits might be required. Thanks!

Comment 15 Issue Tracker 2009-12-17 19:55:51 UTC
Event posted on 12-17-2009 02:55pm EST by kbaxley

So the three kernel patches went into 2.6.18-164.9.1.el5..I wasn't aware
of that.

Anyway, it still doesn't look like things are being reported correctly
even with the latest RHEL5 kernel:

On an AMD Istanbul, 8435

dmidecode-2.10-2.el5


Cache Information
       Socket Designation: L1-Cache
       Configuration: Enabled, Not Socketed, Level 1
       Operational Mode: Varies With Memory Address
       Location: Internal
       Installed Size: 1024 kB
       Maximum Size: 1024 kB
       Supported SRAM Types:
               Pipeline Burst
       Installed SRAM Type: Pipeline Burst
       Speed: Unknown
       Error Correction Type: Single-bit ECC
       System Type: Data
       Associativity: 4-way Set-associative

Handle 0x0006, DMI type 7, 19 bytes
Cache Information
       Socket Designation: L2-Cache
       Configuration: Enabled, Not Socketed, Level 2
       Operational Mode: Varies With Memory Address
       Location: Internal
       Installed Size: 4096 kB
       Maximum Size: 4096 kB
       Supported SRAM Types:
               Pipeline Burst
       Installed SRAM Type: Pipeline Burst
       Speed: Unknown
       Error Correction Type: Single-bit ECC
       System Type: Unified
       Associativity: 4-way Set-associative

Handle 0x0007, DMI type 7, 19 bytes
Cache Information
       Socket Designation: L3-Cache
       Configuration: Enabled, Not Socketed, Level 3
       Operational Mode: Varies With Memory Address
       Location: Internal
       Installed Size: 96 kB
       Maximum Size: 96 kB
       Supported SRAM Types:
               Pipeline Burst
       Installed SRAM Type: Pipeline Burst
       Speed: Unknown
       Error Correction Type: Single-bit ECC
       System Type: Unified
       Associativity: 4-way Set-associative

So still not right.


This event sent from IssueTracker by kbaxley 
 issue 332468

Comment 17 Anton Arapov 2009-12-18 10:44:56 UTC
Kent, I'd you to provide dmi dump: 'dmidecode --dump-bin FILE'

  I see correct data from the 2423 model of istambul in dmidecode. I'm going to check whether different istanbul cpus are handled same way in kernel and at the dmi dump. And will have the conclusion after that.

Thanks,

Comment 18 Kent Baxley 2009-12-18 18:03:04 UTC
Created attachment 379259 [details]
dmi dump

Comment 19 Anton Arapov 2009-12-23 12:51:57 UTC
  dmidecode reads the required bits from the /dev/mem, which is mapped to first megabyte of memory on x86 systems. There are no code to handle any particular x86 cpu/chipset neither in kernel nor in dmidecode.
  That said dmidecode just gets what the BIOS exposes and interpret it accordingly to DMTF Standard, v2.6.1 (http://www.dmtf.org/standards/smbios/)

  Conclusion: This is purely BIOS issue, please try to look whether updated BIOS available for your system or report the issue to AMD.


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