Bug 108616
| Summary: | RHEL4 (IPF): Support for Additional function in Intel's Monticeto processor (HW) | ||
|---|---|---|---|
| Product: | Red Hat Enterprise Linux 4 | Reporter: | Matt Webbink <mattwebb> |
| Component: | kernel | Assignee: | Geoff Gustafson <grgustaf> |
| Status: | CLOSED ERRATA | QA Contact: | |
| Severity: | high | Docs Contact: | |
| Priority: | high | ||
| Version: | 4.0 | CC: | jbaron, sdenham, tao |
| Target Milestone: | --- | Keywords: | MoveUpstream |
| Target Release: | --- | ||
| Hardware: | ia64 | ||
| OS: | Linux | ||
| URL: | IT_28884 | ||
| Whiteboard: | Kernel | ||
| Fixed In Version: | RHSA-2006-0132 | Doc Type: | Bug Fix |
| Doc Text: | Story Points: | --- | |
| Clone Of: | Environment: | ||
| Last Closed: | 2006-03-07 18:28:49 UTC | Type: | --- |
| Regression: | --- | Mount Type: | --- |
| Documentation: | --- | CRM: | |
| Verified Versions: | Category: | --- | |
| oVirt Team: | --- | RHEL 7.3 requirements from Atomic Host: | |
| Cloudforms Team: | --- | Target Upstream Version: | |
| Embargoed: | |||
| Bug Depends On: | |||
| Bug Blocks: | 168429 | ||
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Description
Matt Webbink
2003-10-30 18:28:56 UTC
Montecito is Intel's dual-core, dual- and multiprocessor follow-on to the Madison 9n processor. Due early 2005. Has larger caches than Madison, plus 9nm technologies. Conditionally accept if patches are upstream by May (A2). HP will provide patches upstream for Arches by April 1; hardware as well (Montecito and Arches) by April 1. SUBMIT_UPSTREAM for the code part, leaving open as NEEDINFO due to the requirement for hardware. HP-IPF is currently evaluating schema to see whether any o/s changes need to be submitted upstream; to date, none is identified. Hardware (functional prototypes) (Montecito is the processor; Arches is the I/O chipset) now scheduled to be available to RH in April. Production protos to RH by early June; final systems to RH by August. (They'll replace the functional and production protos when final production systems out.) *** Bug 108806 has been marked as a duplicate of this bug. *** Update to this: Charline checking dates on when functional prototypes will be available. Was supposed to be April. FROM HP-IPF:
> ISSUE #28884 Support for Montecito and Arches: Intel is
> making changes for Montecito, and HP may have additional
> changes once we learn more about this new CPU (e.g.
> enhancements to MCA handling). Including support for HPET
> and async clocks Yes, on Arches support (that we know of to-date)
No on HPET. Code complete, but waiting on Intel to validate ia32 issues before
going into 2.6. HP would still like to get this into RHEL 4.
HARDWARE DEADLINE was 4/01. Per above, Charline checking dates on when
functional prototypes will be available.
Wasn't specified in time. Won't commit to do this for RHEL4. They have missed the deadline for RHEL4. Systems may work with RHEL4, but we can't guarantee it at this point, nor will it be a fully-supported configuration. Splitting this out into two FZ's.
* Arches hardware won't be available until 2Q2005 so new FZ created
with target RHEL4_U1.
* Montecito support is in U1 and will be base RHEL4. (this FZ)
- Leaving this CLOSED-DEFERRED in case any new Monticeto fucntion
is being requested per comment #11 above.
Arches FZ is Bug 124923 Base Montecito support shipped in RHEL3 U1 and will be in the RHEL4 base. If HP identifies additional support based on Intel's Monticeto changes and provides hardware, RH will make a best effort to incorporate these changes into RHEL4. However, if there are significant kernel updates required, they will need to wait for RHEL4 U1. PM ACK for U2. An advisory has been issued which should help the problem described in this bug report. This report is therefore being closed with a resolution of ERRATA. For more information on the solution and/or where to find the updated files, please follow the link below. You may reopen this bug report if the solution does not work for you. http://rhn.redhat.com/errata/RHSA-2006-0132.html |