Bug 1547854
Summary: | Latest rt56 real time kernel on Intel i9 has broken TSC | ||
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Product: | Red Hat Enterprise MRG | Reporter: | Kazu Yoshida <kyoshida> |
Component: | realtime-kernel | Assignee: | Daniel Bristot de Oliveira <daolivei> |
Status: | CLOSED ERRATA | QA Contact: | Jiri Kastner <jkastner> |
Severity: | high | Docs Contact: | Petr Bokoc <pbokoc> |
Priority: | high | ||
Version: | 2.5 | CC: | bhu, daolivei, lgoncalv, mgaykar, pbokoc, prarit, williams |
Target Milestone: | 2.5 | ||
Target Release: | --- | ||
Hardware: | x86_64 | ||
OS: | Linux | ||
Whiteboard: | |||
Fixed In Version: | kernel-rt-3.10.0-693.24.1.rt56.609.el6rt | Doc Type: | Bug Fix |
Doc Text: |
Intel Core X-Series (Skylake) processors use a hardcoded Time Stamp Counter (TSC) frequency of 25 MHz. In some cases this can be imprecise and lead to timing-related problems such as time drift, timers being triggered early, or TSC clock instability. This update mitigates these problems by no longer using the "native_calibrate_tsc()" function to define the TSC frequency. Refined calibration is now used to update the clock rate accordingly in these cases.
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Story Points: | --- |
Clone Of: | Environment: | ||
Last Closed: | 2018-04-17 15:34:33 UTC | Type: | Bug |
Regression: | --- | Mount Type: | --- |
Documentation: | --- | CRM: | |
Verified Versions: | Category: | --- | |
oVirt Team: | --- | RHEL 7.3 requirements from Atomic Host: | |
Cloudforms Team: | --- | Target Upstream Version: | |
Embargoed: |
Description
Kazu Yoshida
2018-02-22 06:27:27 UTC
Hi Petr, It is ok, Thanks! -- Daniel Since the problem described in this bug report should be resolved in a recent advisory, it has been closed with a resolution of ERRATA. For information on the advisory, and where to find the updated files, follow the link below. If the solution does not work for you, open a new bug report. https://access.redhat.com/errata/RHSA-2018:1170 |