Bug 562037
| Summary: | cpu performance is not improved with advanced cpu flag | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Product: | Red Hat Enterprise Linux 5 | Reporter: | Suqin Huang <shuang> | ||||||||||
| Component: | kvm | Assignee: | john cooper <john.cooper> | ||||||||||
| Status: | CLOSED NOTABUG | QA Contact: | Virtualization Bugs <virt-bugs> | ||||||||||
| Severity: | medium | Docs Contact: | |||||||||||
| Priority: | low | ||||||||||||
| Version: | 5.5 | CC: | acathrow, cpelland, dshaks, john.cooper, llim, mwagner, nobody, shuang, tburke, virt-maint, ykaul | ||||||||||
| Target Milestone: | rc | ||||||||||||
| Target Release: | --- | ||||||||||||
| Hardware: | All | ||||||||||||
| OS: | Linux | ||||||||||||
| Whiteboard: | |||||||||||||
| Fixed In Version: | Doc Type: | Bug Fix | |||||||||||
| Doc Text: | Story Points: | --- | |||||||||||
| Clone Of: | Environment: | ||||||||||||
| Last Closed: | 2011-01-13 19:51:50 UTC | Type: | --- | ||||||||||
| Regression: | --- | Mount Type: | --- | ||||||||||
| Documentation: | --- | CRM: | |||||||||||
| Verified Versions: | Category: | --- | |||||||||||
| oVirt Team: | --- | RHEL 7.3 requirements from Atomic Host: | |||||||||||
| Cloudforms Team: | --- | Target Upstream Version: | |||||||||||
| Embargoed: | |||||||||||||
| Bug Depends On: | |||||||||||||
| Bug Blocks: | 580948 | ||||||||||||
| Attachments: |
|
||||||||||||
|
Description
Suqin Huang
2010-02-05 03:48:16 UTC
Created attachment 388967 [details]
sandra muti-media test report
Mark, Do you have any suggestion for the performance benchmark testing. Dor, Do you have any suggestion for the testing result? The differences on physical machines might be bigger since it is not only the flags that were changed. Can you post the /proc/cpuinfo of the guest? Since sandra sees sse4_2 it does work, not sure if it is a real bug. Maybe there is a sse4_2 unit test that can provide better results? Maybe use this: http://software.intel.com/en-us/articles/motion-estimation-with-intel-streaming-simd-extensions-4-intel-sse4/ (In reply to comment #3) > The differences on physical machines might be bigger since it is not only the > flags that were changed. Can you post the /proc/cpuinfo of the guest? Please include an "x86info -a -f" dump in addition to /proc/cpuinfo as reading the raw cpuid data is the best confirmation of the flag state. > Since sandra sees sse4_2 it does work, not sure if it is a real bug. Yea, seems to be. Just to validate that assumption how does the Sandra Benchmark react if an sse4.2 instruction isn't discovered? Might be useful to attach a log of that scenario here for reference. sandra benchmark is tested on windows, can not cat "x86info -a -f" info. get cpu flag with CPUID: sse sse2 sse3 ssse3 sse4.1 sse4.2 VT (In reply to comment #6) > sandra benchmark is tested on windows, can not cat "x86info -a -f" info. > get cpu flag with CPUID: sse sse2 sse3 ssse3 sse4.1 sse4.2 VT So using the exact command line, just boot it from a Live CD with Linux. I'm pretty sure for start the flags won't change. [Forgot to set the "need additional info" request in previous comment.] 1. host: kernel: 2.6.18-232.el5 kvm: kvm-83-215.el5 cpu: processor : 7 vendor_id : GenuineIntel cpu family : 6 model : 26 model name : Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx rdtscp lm constant_tsc ida nonstop_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr sse4_1 sse4_2 popcnt lahf_lm 2. guest window2008r2 Sandra: http://download1us.softpedia.com/dl/bd9271c3262ac3049ef0134f3f538b57/4cee0a6d/100005280/software/system/info/san1720.exe 3. x86info boot with sse4.1,sse4.2 x87info v1.21. Dave Jones 2001-2007 Feedback to <davej>. Found 2 CPUs -------------------------------------------------------------------------- CPU #1 Family: 6 Model: 6 Stepping: 3 Type: 0 Brand: 0 CPU Model: Celeron / Mobile Pentium II Original OEM Feature flags: fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh mmx fxsr sse sse2 Extended feature flags: sse3 [19] [20] [31] [0] [2] [3] [4] [5] [6] [7] [8] [9] SYSCALL [13] [15] [16] xd [23] [24] em64t Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L2 unified cache: 2MB, sectored, 8-way associative. 64 byte line size. TLB info -------------------------------------------------------------------------- CPU #2 Family: 6 Model: 6 Stepping: 3 Type: 0 Brand: 0 CPU Model: Celeron / Mobile Pentium II Original OEM Feature flags: fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh mmx fxsr sse sse2 Extended feature flags: sse3 [19] [20] [31] [0] [2] [3] [4] [5] [6] [7] [8] [9] SYSCALL [13] [15] [16] xd [23] [24] em64t Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L2 unified cache: 2MB, sectored, 8-way associative. 64 byte line size. TLB info -------------------------------------------------------------------------- WARNING: Detected SMP, but unable to access cpuid driver. Used Uniprocessor CPU routines. Results inaccurate. Created attachment 463057 [details]
have some improvement
Created attachment 463058 [details]
without sse4.1, sse4.2
This request was evaluated by Red Hat Product Management for inclusion in the current release of Red Hat Enterprise Linux. Because the affected component is not scheduled to be updated in the current release, Red Hat is unfortunately unable to address this request at this time. Red Hat invites you to ask your support representative to propose this request, if appropriate and relevant, in the next release of Red Hat Enterprise Linux. This request was erroneously denied for the current release of Red Hat Enterprise Linux. The error has been fixed and this request has been re-proposed for the current release. Looks like a benchmark issue citing comment/attachements #20/#21 above which indicate a ~50% improvement in the case of +sse4_1,+sse4_2. |