ISSUE DESCRIPTION
=================

On real hardware, a 32-bit PAE guest must leave the USER and RW bit
clear in L3 pagetable entries, but the pagetable walk behaves as if
they were set. (The L3 entries are cached in processor registers, and
don't actually form part of the pagewalk.)

When running a 32-bit PV guest on a 64-bit Xen, Xen must always OR in
the USER and RW bits for L3 updates for the guest to observe
architectural behaviour. This is unsafe in combination with recursive
pagetables.

As there is no way to construct an L3 recursive pagetable in native
32-bit PAE mode, disallow this option in 32-bit PV guests.

IMPACT
======

A malicious 32-bit PV guest administrator can escalate their privilege
to that of the host.

VULNERABLE SYSTEMS
==================

All versions of Xen are vulnerable.

Only 64-bit builds of the hypervisor are vulnerable. For Xen 4.3 and
earlier, 32-bit builds of the hypervisor are not vulnerable.

The vulnerability is only exposed to 32-bit PV guests on x86 hardware.

The vulnerability is not exposed to 64-bit PV guests, x86 HVM guests,
or ARM guests.

MITIGATION
==========

Running only 64-bit PV or HVM guests will avoid this vulnerability.

RESOLUTION
==========

Applying the attached patch resolves this issue.

xsa185.patch xen-unstable - Xen 4.4

$ sha256sum xsa185*
7d3d3b47cff671d3772fdbaeae88f2336e0033a772dbe3da5e91bc4ed64c1bda xsa185.patch
$