On a mixed cluster of CPUs like an ARM big.LITTLE SoC lscpu miss reports some of the details of the CPUs. util-linux-2.32.1-1.fc29.aarch64 For example in the output below for a Rockchips 3399 we have a 6 core SoC with 2* Cortex-A72 and 4* Cortex-A53. There's a couple of problems here, first is that it reports them all as A53s, second it sees it as 3 cores per "socket" where the break down is really 2 and 4. A slightly different point is they're not really NUMA as the memory access is actually uniform, it's the CPUs themselves that aren't, although I'm not sure there's a proper term. # lscpu Architecture: aarch64 Byte Order: Little Endian CPU(s): 6 On-line CPU(s) list: 0-5 Thread(s) per core: 1 Core(s) per socket: 3 Socket(s): 2 NUMA node(s): 1 Vendor ID: ARM Model: 4 Model name: Cortex-A53 Stepping: r0p4 BogoMIPS: 48.00 NUMA node0 CPU(s): 0-5 Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid Output of /proc/cpuinfo processor : 0 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 processor : 1 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 processor : 2 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 processor : 3 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 processor : 4 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd08 CPU revision : 2 processor : 5 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd08 CPU revision : 2
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Still an issue
This scenario is unsupported by lscpu. It assumes the same CPUs in all sockets and all topology is estimated from CPU0. It will require huge changes to fix it :-( Anyway, added to the upstream TODO file. We'll see. Thanks for your report. It would be nice to have a dump from your unique /sys and /proc for testing purposes. Please, send me output (tarball) from https://raw.githubusercontent.com/karelzak/util-linux/master/tests/ts/lscpu/mk-input.sh. Thanks!
Created attachment 1659239 [details] Output of mk-input.sh
(In reply to Karel Zak from comment #3) > This scenario is unsupported by lscpu. It assumes the same CPUs in all > sockets and all topology is > estimated from CPU0. It will require huge changes to fix it :-( Yes, sadly asymetric processors are a thing, in the early cases of arm's big.LITTLE they were clusters of processor types, initially 2 now up to 4 (I think). With their next gen of this, called DynamIQ, each processor core could be different and they're all independent. Intel is also introducing a similar technology on some of their devices so sadly it's not some weird short lived thing. > It would be nice to have a dump from your unique /sys and /proc for testing > purposes. > > Please, send me output (tarball) from Attached.
I'm working on a new lscpu code (https://github.com/karelzak/util-linux/tree/topic/lscpu), but it's not ready yet. I'll close this issue here as we need to resolve it in upstream tree first.
Small update, debug message from new lscpu on your /sys and /proc 428128: lscpu: TYPE: [0x611000000040]: reading 0x41/0xd03/ topology 428128: lscpu: TYPE: [0x611000000040]: nthreads: 4 428128: lscpu: TYPE: [0x611000000040]: ncores: 4 428128: lscpu: TYPE: [0x611000000040]: nsockets: 1 428128: lscpu: TYPE: [0x611000000040]: nbooks: 0 428128: lscpu: TYPE: [0x611000000040]: ndrawers: 0 428128: lscpu: TYPE: [0x611000000540]: reading 0x41/0xd08/ topology 428128: lscpu: TYPE: [0x611000000540]: nthreads: 2 428128: lscpu: TYPE: [0x611000000540]: ncores: 2 428128: lscpu: TYPE: [0x611000000540]: nsockets: 1 428128: lscpu: TYPE: [0x611000000540]: nbooks: 0 428128: lscpu: TYPE: [0x611000000540]: ndrawers: 0 I guess the numbers are correct for each of the types.
(In reply to Karel Zak from comment #7) > Small update, debug message from new lscpu on your /sys and /proc > > 428128: lscpu: TYPE: [0x611000000040]: reading 0x41/0xd03/ topology > 428128: lscpu: TYPE: [0x611000000040]: nthreads: 4 > 428128: lscpu: TYPE: [0x611000000040]: ncores: 4 > 428128: lscpu: TYPE: [0x611000000040]: nsockets: 1 > 428128: lscpu: TYPE: [0x611000000040]: nbooks: 0 > 428128: lscpu: TYPE: [0x611000000040]: ndrawers: 0 > 428128: lscpu: TYPE: [0x611000000540]: reading 0x41/0xd08/ topology > 428128: lscpu: TYPE: [0x611000000540]: nthreads: 2 > 428128: lscpu: TYPE: [0x611000000540]: ncores: 2 > 428128: lscpu: TYPE: [0x611000000540]: nsockets: 1 > 428128: lscpu: TYPE: [0x611000000540]: nbooks: 0 > 428128: lscpu: TYPE: [0x611000000540]: ndrawers: 0 > > I guess the numbers are correct for each of the types. The number of cores are, what does the name map through to for the lookup? Should be Cortex-A72 for the second pair and Cortex-53 for the quad group. Not sure of the stepping/revision.
The implementer and type are translated later in the code, it's: 0x41, "ARM" 0xd03, "Cortex-A53" (4 cores) 0xd08, "Cortex-A72" (2 cores) The question is how to display mixed CPUs on lscpu output, maybe for humans CPU(s): 6 ├─ Cortex-A53 │ Thread(s) per core: 1 │ Core(s) per socket: 4 │ Socket(s): 1 └─ Cortex-A72 Thread(s) per core: 1 Core(s) per socket: 2 Socket(s): 1
> 0xd03, "Cortex-A53" (4 cores) > 0xd08, "Cortex-A72" (2 cores) That's correct. > The question is how to display mixed CPUs on lscpu output, maybe for humans That's a very good question. So for this generation of HW I think the below is about correct. The term that is used is "clusters" and most will have two clusters, in some of the newer high end devices there's actually 3 clusters, often in 2/2/4 or 2/4/4 combinations. > CPU(s): 6 > ├─ Cortex-A53 > │ Thread(s) per core: 1 > │ Core(s) per socket: 4 > │ Socket(s): 1 > └─ Cortex-A72 > Thread(s) per core: 1 > Core(s) per socket: 2 > Socket(s): 1 In the newer generations there's a technology that Arm calls DynamIQ [1] which means the cores are basically all independent and they can power any or nearly all cores off and they can come and go. Intel is doing something similar with their latest gen too. I'm not sure what would be the best way to display those and I don't currently have access to a DynamIQ system to even poke and see. [1] https://www.arm.com/why-arm/technologies/dynamiq
It's interesting that /sys in your dump does not provide any information about caches, for "standard" CPUs there is /sys/devices/system/cpu/cpu0/cache/ directory with info about caches.