Bug 177492 - Early panic in "io_apic_get_unique_id" on 4CPU, dual-core HT enabled EM64T System
Early panic in "io_apic_get_unique_id" on 4CPU, dual-core HT enabled EM64T Sy...
Status: CLOSED ERRATA
Product: Red Hat Enterprise Linux 4
Classification: Red Hat
Component: kernel (Show other bugs)
4.0
All Linux
medium Severity medium
: ---
: ---
Assigned To: Jim Paradis
Brian Brock
:
Depends On:
Blocks: 168429
  Show dependency treegraph
 
Reported: 2006-01-11 04:00 EST by Martin Knoblauch
Modified: 2013-08-05 21:17 EDT (History)
2 users (show)

See Also:
Fixed In Version: RHSA-2006-0132
Doc Type: Bug Fix
Doc Text:
Story Points: ---
Clone Of:
Environment:
Last Closed: 2006-03-07 16:11:11 EST
Type: ---
Regression: ---
Mount Type: ---
Documentation: ---
CRM:
Verified Versions:
Category: ---
oVirt Team: ---
RHEL 7.3 requirements from Atomic Host:
Cloudforms Team: ---


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Description Martin Knoblauch 2006-01-11 04:00:30 EST
Description of problem:

 We have an Intel SR6850HW4 box with 4 dual-core, ht-enabled CPUs on test. After
upping NR_CPUS to 16 (see bugzilla 177445) to be able to use all 16 logical
CPUs, we got the panic from "arch/x86_64/kernel/io_apic.c":

  panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);

 Googling around shows that this problem seem to be known and fixed in mainline.
Solution seem to be to remove the call to "io_apic_get_unique_id" in "mpparse.c"

--- linux-2.6.9/arch/x86_64/kernel/mpparse.c-orig       2006-01-09
18:25:18.000000000 +0100
+++ linux-2.6.9/arch/x86_64/kernel/mpparse.c    2006-01-09 18:05:26.000000000 +0100
@@ -763,7 +763,8 @@
        mp_ioapics[idx].mpc_apicaddr = address;

        set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
-       mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
+//     mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
+       mp_ioapics[idx].mpc_apicid = id;
        mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);

        /*

 After this the box boots fine and works like expected with 16 CPUs showing. In
mainline the fix is slightly bigger, as the routine "io_apic_get_unique_id" is
removed alltogether from the tree.

 Please consider fixing this for official RHEL4 kernels.

Version-Release number of selected component (if applicable):

Linux muvpl404 2.6.9-22.EL.smp #1 SMP Mon Jan 9 18:33:30 CET 2006 x86_64 x86_64
x86_64 GNU/Linux

How reproducible:

100% on decribed hardware

Steps to Reproduce:
1. Rebuild kernel with NR_CPUS=16
2. Install on descibed hardware
3. Reboot with "earlyprintk=vga" -> Panic
  
Actual results:

Panic

Expected results:

Boot

Additional info:

[root@muvpl404 SOURCES]# lspci
00:00.0 Host bridge: Intel Corporation E8500 Hub Interface 1.5 (rev 10)
00:01.0 PCI bridge: Intel Corporation E8500 PCI Express x4 Port D (rev 10)
00:02.0 PCI bridge: Intel Corporation E8500 PCI Express x8 Port C (rev 10)
00:03.0 PCI bridge: Intel Corporation E8500 PCI Express x4 Port C1 (rev 10)
00:04.0 PCI bridge: Intel Corporation E8500 PCI Express x4 Port B0 (rev 10)
00:05.0 PCI bridge: Intel Corporation E8500 PCI Express x4 Port B1 (rev 10)
00:06.0 PCI bridge: Intel Corporation E8500 PCI Express x4 Port A0 (rev 10)
00:07.0 PCI bridge: Intel Corporation E8500 PCI Express x4 Port A1 (rev 10)
00:08.0 Host bridge: Intel Corporation E8500 IMI Registers (rev 10)
00:09.0 RAM memory: Intel Corporation E8500 eXternal Memory Bridge (rev 10)
00:09.1 RAM memory: Intel Corporation E8500 XMB Miscellaneous Registers (rev 10)
00:09.2 RAM memory: Intel Corporation E8500 XMB Memory Interleaving Registers
(rev 10)
00:09.3 RAM memory: Intel Corporation E8500 XMB DDR Initialization and
Calibration (rev 10)
00:09.4 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:09.5 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:09.6 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:09.7 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0a.0 Host bridge: Intel Corporation E8500 IMI Registers (rev 10)
00:0b.0 RAM memory: Intel Corporation E8500 eXternal Memory Bridge (rev 10)
00:0b.1 RAM memory: Intel Corporation E8500 XMB Miscellaneous Registers (rev 10)
00:0b.2 RAM memory: Intel Corporation E8500 XMB Memory Interleaving Registers
(rev 10)
00:0b.3 RAM memory: Intel Corporation E8500 XMB DDR Initialization and
Calibration (rev 10)
00:0b.4 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0b.5 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0b.6 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0b.7 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0c.0 Host bridge: Intel Corporation E8500 IMI Registers (rev 10)
00:0d.0 RAM memory: Intel Corporation E8500 eXternal Memory Bridge (rev 10)
00:0d.1 RAM memory: Intel Corporation E8500 XMB Miscellaneous Registers (rev 10)
00:0d.2 RAM memory: Intel Corporation E8500 XMB Memory Interleaving Registers
(rev 10)
00:0d.3 RAM memory: Intel Corporation E8500 XMB DDR Initialization and
Calibration (rev 10)
00:0d.4 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0d.5 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0d.6 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0d.7 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0e.0 Host bridge: Intel Corporation E8500 IMI Registers (rev 10)
00:0f.0 RAM memory: Intel Corporation E8500 eXternal Memory Bridge (rev 10)
00:0f.1 RAM memory: Intel Corporation E8500 XMB Miscellaneous Registers (rev 10)
00:0f.2 RAM memory: Intel Corporation E8500 XMB Memory Interleaving Registers
(rev 10)
00:0f.3 RAM memory: Intel Corporation E8500 XMB DDR Initialization and
Calibration (rev 10)
00:0f.4 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0f.5 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0f.6 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:0f.7 RAM memory: Intel Corporation E8500 XMB Reserved Registers (rev 10)
00:10.0 Host bridge: Intel Corporation E8500 Front Side Bus, Boot, and Interrupt
Registers (rev 10)
00:10.1 Host bridge: Intel Corporation E8500 Address Mapping Registers (rev 10)
00:10.2 Host bridge: Intel Corporation E8500 RAS Registers (rev 10)
00:11.0 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:11.1 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:11.2 Host bridge: Intel Corporation E8500 Miscellaneous Registers (rev 10)
00:13.0 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:13.1 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:13.2 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:13.3 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:13.4 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:13.5 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:13.6 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:13.7 Host bridge: Intel Corporation E8500 Reserved Registers (rev 10)
00:1d.0 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI
Controller #1 (rev 02)
00:1d.1 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI
Controller #2 (rev 02)
00:1d.2 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI
Controller #3 (rev 02)
00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI
Controller (rev 02)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev c2)
00:1f.0 ISA bridge: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface
Bridge (rev 02)
00:1f.2 IDE interface: Intel Corporation 82801EB (ICH5) SATA Controller (rev 02)
00:1f.3 SMBus: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller (rev 02)
0a:00.0 PCI bridge: Intel Corporation 6700PXH PCI Express-to-PCI Bridge A (rev 09)
0a:00.2 PCI bridge: Intel Corporation 6700PXH PCI Express-to-PCI Bridge B (rev 09)
0c:02.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5704 Gigabit
Ethernet (rev 10)
0c:02.1 Ethernet controller: Broadcom Corporation NetXtreme BCM5704 Gigabit
Ethernet (rev 10)
0e:00.0 PCI bridge: Intel Corporation 80332 [Dobson] I/O processor (A-Segment
Bridge) (rev 07)
0e:00.2 PCI bridge: Intel Corporation 80332 [Dobson] I/O processor (B-Segment
Bridge) (rev 07)
0f:05.0 SCSI storage controller: LSI Logic / Symbios Logic 53c1030 PCI-X
Fusion-MPT Dual Ultra320 SCSI (rev 08)
0f:05.1 SCSI storage controller: LSI Logic / Symbios Logic 53c1030 PCI-X
Fusion-MPT Dual Ultra320 SCSI (rev 08)
11:00.0 VGA compatible controller: ATI Technologies Inc Radeon RV100 QY [Radeon
7000/VE]
Comment 1 Martin Knoblauch 2006-01-11 10:35:50 EST
Just to add more info. Here is the related discussion on the x86_64 list:

http://www.x86-64.org/lists/discuss/msg06590.html

Cheers
Martin
Comment 2 Jim Paradis 2006-01-11 13:52:19 EST

*** This bug has been marked as a duplicate of 168604 ***
Comment 4 Red Hat Bugzilla 2006-03-07 16:11:11 EST
An advisory has been issued which should help the problem
described in this bug report. This report is therefore being
closed with a resolution of ERRATA. For more information
on the solution and/or where to find the updated files,
please follow the link below. You may reopen this bug report
if the solution does not work for you.

http://rhn.redhat.com/errata/RHSA-2006-0132.html

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