When a guest accesses certain Model Specific Registers, Xen first reads the value from hardware to use as the basis for auditing the guest access. For the MISC_ENABLE MSR, which is an Intel specific MSR, this MSR read is performed without error handling for a #GP fault, which is the consequence of trying to read this MSR on non-Intel hardware.
Acknowledgments: Name: the Xen project
Statement: Only x86 systems which do not implement the MISC_ENABLE MSR (0x1a0) are vulnerable and only Xen versions 4.11 and onwards are vulnerable. Red Hat Enterprise Linux 5 is not affected by this flaw, as it shipped an older version of Xen.
Mitigation: Running only HVM/PVH guests avoids the vulnerability.
Created xen tracking bugs for this issue: Affects: fedora-all [bug 1881619]
This bug is now closed. Further updates for individual products will be reflected on the CVE page(s): https://access.redhat.com/security/cve/cve-2020-25602
External References: https://xenbits.xen.org/xsa/advisory-333.html