Bug 2155622 - L1 Cache info not correct
Summary: L1 Cache info not correct
Keywords:
Status: ASSIGNED
Alias: None
Product: Container Native Virtualization (CNV)
Classification: Red Hat
Component: Virtualization
Version: 4.10.9
Hardware: x86_64
OS: Linux
medium
medium
Target Milestone: ---
: 4.14.0
Assignee: Barak
QA Contact: Kedar Bidarkar
URL:
Whiteboard:
Depends On:
Blocks:
TreeView+ depends on / blocked
 
Reported: 2022-12-21 16:24 UTC by Nils Koenig
Modified: 2023-07-31 12:42 UTC (History)
5 users (show)

Fixed In Version:
Doc Type: If docs needed, set a value
Doc Text:
Clone Of:
Environment:
Last Closed:
Target Upstream Version:
Embargoed:


Attachments (Terms of Use)
libvirt domain xml (19.34 KB, text/plain)
2022-12-21 16:24 UTC, Nils Koenig
no flags Details


Links
System ID Private Priority Status Summary Last Updated
Red Hat Issue Tracker CNV-23525 0 None None None 2022-12-21 16:33:22 UTC

Description Nils Koenig 2022-12-21 16:24:34 UTC
Created attachment 1933987 [details]
libvirt domain xml

Description of problem:

The information which CPUs and their hyperthread share which cache seems to be wrong in the guest.


Version-Release number of selected component (if applicable):

oc version
Client Version: 4.10.45
Server Version: 4.10.45
Kubernetes Version: v1.23.12+8a6bfe4


How reproducible:

Guest

# lscpu --all --extended

CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE
0   0    0      0    0:0:0:0       yes
1   0    0      0    1:1:0:0       yes
2   0    0      1    2:2:1:0       yes
3   0    0      1    3:3:1:0       yes
4   0    0      2    4:4:2:0       yes
5   0    0      2    5:5:2:0       yes

Dom XML

    <vcpupin vcpu='0' cpuset='1'/>
    <vcpupin vcpu='1' cpuset='113'/>
    <vcpupin vcpu='2' cpuset='2'/>
    <vcpupin vcpu='3' cpuset='114'/>
    <vcpupin vcpu='4' cpuset='3'/>
    <vcpupin vcpu='5' cpuset='115'/>


Bare metal host

lscpu --all --extended
CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE MAXMHZ    MINMHZ
0   0    0      0    0:0:0:0       yes    4300.0000 1000.0000
1   0    0      1    1:1:1:0       yes    4300.0000 1000.0000
2   0    0      2    2:2:2:0       yes    4300.0000 1000.0000
3   0    0      3    3:3:3:0       yes    4300.0000 1000.0000
...
112 0    0      0    0:0:0:0       yes    4300.0000 1000.0000
113 0    0      1    1:1:1:0       yes    4300.0000 1000.0000
114 0    0      2    2:2:2:0       yes    4300.0000 1000.0000
115 0    0      3    3:3:3:0       yes    4300.0000 1000.0000


Note that on the HW the it's indicated that a CPU and it's Hyperthread share all caches (e.g. cpu1 and cpu113 have 1:1:1:0).

In the guest the coresponding cpu0 and cpu1 have a different line there 0:0:0:0  
 vs 1:1:0:0.

Now I can't tell if thats a real issue or just a cosmetic thing but it's definately different and should be corrected.


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