Description of problem: When booting an P4 machine with HT support and turning the HT support off in the BIOS, the orporfile support is still reported as i386/p4-ht in /dev/oprofile/cpu_type. This means that only the first half of the event counters is available (4 instead of 8 in most cases). The oprofile support should recognize that only one thread is running (on SMP machines per socket) and change the type to i386/p4 and then make all 8 registers available. Version-Release number of selected component (if applicable): 2.6.18-1.2239 How reproducible: always Steps to Reproduce: 1.get P4 machine with HT support and HT turned off in BIOS 2.opcontrol --list-events 3.cat /dev/oprofile/cpu_type Actual results: i386/p4-ht Expected results: i386/p4 Additional info: I tested this on FC5 since this is the OS I run on that machine. Since it's an update based on 2.6.18 I assume the sae bug exists in the FC5 and RHEL5 kernel.
Are the processors in this machine multi-core? On perfmon2 there were some problems with the cpu id code that appeared to identify multicore P4 processors as hyperthreaded processors. Could the /proc/cpuinfo for both HT and HT disabled be included in the bug report to see whether this is similar problem?
No, simple P4 HT, no multicore. Without HT (disabled in BIOS): processor : 0 vendor_id : GenuineIntel cpu family : 15 model : 4 model name : Intel(R) Pentium(R) 4 CPU 3.60GHz stepping : 1 cpu MHz : 3591.169 cache size : 1024 KB physical id : 0 siblings : 1 core id : 0 cpu cores : 1 fpu : yes fpu_exception : yes cpuid level : 3 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc up pni monitor ds_cpl tm2 cid cx16 xtpr bogomips : 7187.51 clflush size : 64 cache_alignment : 128 address sizes : 36 bits physical, 48 bits virtual power management: With HT enabled: processor : 0 vendor_id : GenuineIntel cpu family : 15 model : 4 model name : Intel(R) Pentium(R) 4 CPU 3.60GHz stepping : 1 cpu MHz : 3591.167 cache size : 1024 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 1 fpu : yes fpu_exception : yes cpuid level : 3 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl tm2 cid cx16 xtpr bogomips : 7187.52 clflush size : 64 cache_alignment : 128 address sizes : 36 bits physical, 48 bits virtual power management: processor : 1 vendor_id : GenuineIntel cpu family : 15 model : 4 model name : Intel(R) Pentium(R) 4 CPU 3.60GHz stepping : 1 cpu MHz : 3591.167 cache size : 1024 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 1 fpu : yes fpu_exception : yes cpuid level : 3 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl tm2 cid cx16 xtpr bogomips : 7182.05 clflush size : 64 cache_alignment : 128 address sizes : 36 bits physical, 48 bits virtual power management:
I can replicate this problem on RHEL-4U4 system: 2.6.9-42.0.3.ELsmp #1 SMP Mon Sep 25 17:24:31 EDT 2006 x86_64 x86_64 x86_64 GNU/Linux The oprofile kernel module is mis identifying the whether the ht is on or off.
Created attachment 144140 [details] Determine number of logical processors active The attached patch was discussed on the oprofile mailing list. Not sure that this will deal properly with the case of multiple cores in a package.
Created attachment 226031 [details] Check the number of processors that are actually active I check out the current 2.6.23 kernel via git and was able to replicate the problem on a xeon (net burst based machine) running the upstream kernel. The attached patch allowed the oprofile module to correctly identify the processor and non-hyperthreaded when it was diabled in the bios. The question is are there any intel processors that have more than one net burst core in the same socket? If so, this patch may still fail. If Intel doesn't have any multicore netburst processors, this change should be sufficient.
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