Bug 2541258 (CVE-2026-97587) - CVE-2026-97587 kernel: perf: RISC-V: store available counter mask as bitmap
Summary: CVE-2026-97587 kernel: perf: RISC-V: store available counter mask as bitmap
Keywords:
Status: NEW
Alias: CVE-2026-97587
Product: Security Response
Classification: Other
Component: vulnerability
Version: unspecified
Hardware: All
OS: Linux
medium
medium
Target Milestone: ---
Assignee: Product Security DevOps Team
QA Contact:
URL:
Whiteboard:
Depends On:
Blocks:
TreeView+ depends on / blocked
 
Reported: 2026-09-25 11:11 UTC by OSIDB Bzimport
Modified: 2026-09-29 09:15 UTC (History)
17 users (show)

Fixed In Version:
Clone Of:
Environment:
Last Closed:
Embargoed:


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Description OSIDB Bzimport 2026-09-25 11:11:29 UTC
In the Linux kernel, the following vulnerability has been resolved:

perf: RISC-V: store available counter mask as bitmap

The available-counter mask was a single unsigned long, but iteration
uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object.
Filling with an unsigned-long bit at index 32 and above is also wrong.

Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word
into CFG_MATCH when checking events, when allocating an index, and when
stopping all counters. Set the counter base to i times BITS_PER_LONG.
Share the CFG_MATCH ecall through a small helper so the 32-bit argument
split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits
above XLEN set, so the first word alone is not enough.

[pjw: updated to apply; fixed checkpatch.pl issues]


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