Bug 2555005 (CVE-2026-98639) - CVE-2026-98639 kernel: kernel: Incorrect TLB flushing in RISC-V KVM via improper nested acceleration update order
Summary: CVE-2026-98639 kernel: kernel: Incorrect TLB flushing in RISC-V KVM via impro...
Keywords:
Status: NEW
Alias: CVE-2026-98639
Product: Security Response
Classification: Other
Component: vulnerability
Version: unspecified
Hardware: All
OS: Linux
high
high
Target Milestone: ---
Assignee: Product Security DevOps Team
QA Contact:
URL:
Whiteboard:
Depends On:
Blocks:
TreeView+ depends on / blocked
 
Reported: 2026-10-18 15:38 UTC by OSIDB Bzimport
Modified: 2026-10-21 01:57 UTC (History)
2 users (show)

Fixed In Version:
Clone Of:
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Description OSIDB Bzimport 2026-10-18 15:38:41 UTC
In the Linux kernel, the following vulnerability has been resolved:

KVM: riscv: Fix NACL hfence entry update order

The SBI v3.0 specification (section 15.1.2) requires a nested HFENCE
entry to be populated as follows:
1) find an unused entry with Config.Pending == 0
2) update the Page_Number and Page_Count words
3) update the Config word with Config.Pending set

__kvm_riscv_nacl_hfence() writes the Config word first, so the SBI
implementation (or NACL hardware) can observe a pending entry with
pnum/pcount values left over from the previous use of that entry,
resulting in incorrect TLB flush ranges.

Write pnum and pcount first and the Config word last. Since the
consumer is an external agent on coherent shared memory, use
WRITE_ONCE() to stop the compiler from reordering the stores and
smp_wmb() to make the parameter words globally visible before the
Pending bit is set.


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