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Clark, I commented on BZ 641009 about the content you've attached here. :) Thanks.
Draft content for the "NUMA and multi-core support" section has not been received, though. Any idea of a date for this?
Created attachment 520442[details]
NUMA topology diagram
I'm not sure I like the example of numa topology in sectin 4.2:
"The performance of a NUMA system can be improved primarily by ensuring that information travels efficiently. To do so, you must be aware of your system's topology - the CPUs, the memory banks, and the paths between them. The numbered servers in Figure 4.1, “An example of NUMA topology” represent the CPUs and memory banks of a system, and the paths between them represent the interconnects between those CPUs and memory banks. If an application's code resides on memory bank 1, and CPU 2 wants to execute that code, then the most efficient path is 123."
This example doesn't really make sense with the diagram given. There are six servers shown in the diagram and if you assume that there is one core and one memory bank per server, then if "CPU 2 wants to execute that code" (on bank 1) then it's one hop between 1 and 2; 3 is not a component of that access path.
I'm no graphic artist, but attached is a quick-n-dirty representation of a two node NUMA system with 4 cpus per node and one memory bank per node. In this example system, any cpu on node 1 has direct access to the memory on that node. If any cpu on node 1 wants to access the memory on node two it has to go through the node 2 controller, meaning that the access takes at least twice as long.
Created attachment 521689[details]
NUMA paper and charts used (Shak/Tim/Larry/Rik/Peter/Andy)
Feel free to use openoffice paper and graphs to describe NUMA in RHEL6 and performance improvements.
Created attachment 489493 [details] First draft of section 4.1 CPUs and NUMA Topology Initial draft of section 4.1