Bug 824147 - asimut: structural model simulation gives incorrect results (i.e. undefined outputs)
asimut: structural model simulation gives incorrect results (i.e. undefined o...
Status: CLOSED WONTFIX
Product: Fedora
Classification: Fedora
Component: alliance (Show other bugs)
18
Unspecified Unspecified
unspecified Severity unspecified
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Assigned To: Chitlesh GOORAH
Fedora Extras Quality Assurance
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Depends On:
Blocks:
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Reported: 2012-05-22 16:09 EDT by Ashwith Rego
Modified: 2014-02-05 06:58 EST (History)
2 users (show)

See Also:
Fixed In Version:
Doc Type: Bug Fix
Doc Text:
Story Points: ---
Clone Of:
Environment:
Last Closed: 2014-02-05 06:58:21 EST
Type: Bug
Regression: ---
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oVirt Team: ---
RHEL 7.3 requirements from Atomic Host:
Cloudforms Team: ---


Attachments (Terms of Use)
Source files required for reproducing the bug. (10.00 KB, application/x-tar)
2012-05-22 16:09 EDT, Ashwith Rego
no flags Details

  None (edit)
Description Ashwith Rego 2012-05-22 16:09:59 EDT
Created attachment 586156 [details]
Source files required for reproducing the bug.

Description of problem:

I'm getting "?u" in the output pattern file when I use asimut to run a schematic model based simulation.

I first wrote a behavioral vbe file to describe an inverter. I next used boog to convert this to it's vst equivalent.

Next I ran a simulation with an input pattern. I saw ?u at the output.


Version-Release:

alliance-5.0-32.20090901snap.fc15.x86_64


How reproducible:

Happens every time


Steps to Reproduce:

1. Untar the attachment invg.tar
2. Run 
      boog invg invg -x 1 -m 2
3. Next, run
      asimut invg invg_in invg_out
  

Actual results:

Here is the output pattern (input is a, output is x):

--                                 vva x 
--                                 ds    
--                                 ds    

                                 : 100?u;
                                 : 101?u;

Expected results:

--                                 vva x 
--                                 ds    
--                                 ds    

                                 : 100?1;
                                 : 101?0;


Additional info:

I checked that this issue occurs with an AND gate and OR gate description as well. This is my first time with alliance so I'm sorry if I've done something wrong in the procedure itself.

The attachment contains 

invg.vbe - the behavioral description of the inverter
invg_in.pat - the input pattern
Comment 1 Ashwith Rego 2012-05-22 16:32:02 EDT
The Description section of the report has a typo. 
I ran a simulation of a structural description (not schematic).
Comment 2 Ashwith Rego 2012-06-28 13:41:41 EDT
Changed version to 17 as the issue is present on Fedora 17 as well. Package installed is: alliance-5.0-34.20090901snap.fc17.x86_64
Comment 3 Ashwith Rego 2013-02-26 14:03:35 EST
Updating version to Fedora 18.
Comment 4 Fedora End Of Life 2013-12-21 03:36:33 EST
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Comment 5 Fedora End Of Life 2014-02-05 06:58:24 EST
Fedora 18 changed to end-of-life (EOL) status on 2014-01-14. Fedora 18 is
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