Created attachment 586156 [details] Source files required for reproducing the bug. Description of problem: I'm getting "?u" in the output pattern file when I use asimut to run a schematic model based simulation. I first wrote a behavioral vbe file to describe an inverter. I next used boog to convert this to it's vst equivalent. Next I ran a simulation with an input pattern. I saw ?u at the output. Version-Release: alliance-5.0-32.20090901snap.fc15.x86_64 How reproducible: Happens every time Steps to Reproduce: 1. Untar the attachment invg.tar 2. Run boog invg invg -x 1 -m 2 3. Next, run asimut invg invg_in invg_out Actual results: Here is the output pattern (input is a, output is x): -- vva x -- ds -- ds : 100?u; : 101?u; Expected results: -- vva x -- ds -- ds : 100?1; : 101?0; Additional info: I checked that this issue occurs with an AND gate and OR gate description as well. This is my first time with alliance so I'm sorry if I've done something wrong in the procedure itself. The attachment contains invg.vbe - the behavioral description of the inverter invg_in.pat - the input pattern
The Description section of the report has a typo. I ran a simulation of a structural description (not schematic).
Changed version to 17 as the issue is present on Fedora 17 as well. Package installed is: alliance-5.0-34.20090901snap.fc17.x86_64
Updating version to Fedora 18.
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Fedora 18 changed to end-of-life (EOL) status on 2014-01-14. Fedora 18 is no longer maintained, which means that it will not receive any further security or bug fix updates. As a result we are closing this bug. If you can reproduce this bug against a currently maintained version of Fedora please feel free to reopen this bug against that version. If you are unable to reopen this bug, please file a new report against the current release. If you experience problems, please add a comment to this bug. Thank you for reporting this bug and we are sorry it could not be fixed.