Red Hat Bugzilla – Bug 824147
asimut: structural model simulation gives incorrect results (i.e. undefined outputs)
Last modified: 2014-02-05 06:58:24 EST
Created attachment 586156 [details]
Source files required for reproducing the bug.
Description of problem:
I'm getting "?u" in the output pattern file when I use asimut to run a schematic model based simulation.
I first wrote a behavioral vbe file to describe an inverter. I next used boog to convert this to it's vst equivalent.
Next I ran a simulation with an input pattern. I saw ?u at the output.
Happens every time
Steps to Reproduce:
1. Untar the attachment invg.tar
boog invg invg -x 1 -m 2
3. Next, run
asimut invg invg_in invg_out
Here is the output pattern (input is a, output is x):
-- vva x
-- vva x
I checked that this issue occurs with an AND gate and OR gate description as well. This is my first time with alliance so I'm sorry if I've done something wrong in the procedure itself.
The attachment contains
invg.vbe - the behavioral description of the inverter
invg_in.pat - the input pattern
The Description section of the report has a typo.
I ran a simulation of a structural description (not schematic).
Changed version to 17 as the issue is present on Fedora 17 as well. Package installed is: alliance-5.0-34.20090901snap.fc17.x86_64
Updating version to Fedora 18.
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