Several caching issues have been uncovered and will be addressed here.
Similar changes have been made in MiqHyperVDisk via separate PR.

1) Cache requests where the request overlapped an existing cache entry
both at the start and end resulted in new entry duplicating the existing
entry plus the data at start and end. This will instead be addressed by
creating new entries for the start and end and using the existing entry.
This is a performance issue.

2) Cache requests where the end of the request (but not the start) was present
in an existing cache entry used the incorrect offset into the entry for the data
returned. This is a data integrity issue.

3) The range of blocks cached for new entries was determined incorrectly.
Depending upon the request from the disk module less data might be cached than required.
This is a performance issue.

4) Concatenating cache entries with recursive calls to bread_cached used the "+"
operator exclusively. When possible this is changed to "<<" to eliminate some
temporary buffer allocation and speed things up a little.

5) Comments also added for clarity.